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Wed, 06 May 2026 08:15:47 -0700 (PDT) X-Received: by 2002:a17:90a:e7d1:b0:35f:bc9f:e1b6 with SMTP id 98e67ed59e1d1-365a96b6eb6mr2734310a91.1.1778080546676; Wed, 06 May 2026 08:15:46 -0700 (PDT) Received: from [10.204.101.47] ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-365b4f70e8asm4011790a91.11.2026.05.06.08.15.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 06 May 2026 08:15:46 -0700 (PDT) Message-ID: <734e8ad0-54e0-4fcd-a3b4-8e99fb521ea1@oss.qualcomm.com> Date: Wed, 6 May 2026 20:45:38 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 10/13] media: iris: Add power sequence for Glymur To: Vishnu Reddy , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Joerg Roedel , Will Deacon , Robin Murphy , Bjorn Andersson , Konrad Dybcio Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev References: <20260505-glymur-v4-0-17571dbd1caa@oss.qualcomm.com> <20260505-glymur-v4-10-17571dbd1caa@oss.qualcomm.com> Content-Language: en-US From: Vikash Garodia In-Reply-To: <20260505-glymur-v4-10-17571dbd1caa@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=YYCNIQRf c=1 sm=1 tr=0 ts=69fb5b24 cx=c_pps a=RP+M6JBNLl+fLTcSJhASfg==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=Um2Pa8k9VHT-vaBCBUpS:22 a=EUspDBNiAAAA:8 a=4ZKAssT4AknkAVwkBooA:9 a=QEXdDO2ut3YA:10 a=iS9zxrgQBfv6-_F4QbHw:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA2MDE1MCBTYWx0ZWRfXy3qPfnU7AXop GkWfXQRUGlu7CZZrw6DN5AfvxkgCp3J+4KicNXjPXSOe0TuFK0drmZ7K//yjnQ0+J3ilv9ZKd/k n/dETLtruZZt4by5Zuhrn8S55XZiHQLZwsd0ZaeBz+U4RnAYEQj0iK5u+RN8uh0lf5i3FWqDNnu Of1KFmRQCZE8KaTW74Qo4MimCbO+Wgx1lYeeMzaNe9Bxq9+8z/FyO+orlVjgdWUp0mv1JOUl6Np ZVEU4dll+FOIwfIVw/b2SUfqAKYoExzTIwMHHf89hg/mmFQL8kJFuxLklNqWhxY91SO1Zl+1g2S sOFiU03q9I3fWTiu2a8pzB5hpV9N4BfQiecZ/is8h/cok/HGfrLCPjEm2zp09m2+nsa5JRp8v7w VuImK8GB3SWP0jOsu3E2DgDasSxuj/WFRUBwbPJk9DAwunC0Pe5OwlkqF7itdBGSk05M3ZPm1YX 8RuDs4Tx0blf6JM7POA== X-Proofpoint-ORIG-GUID: 55YyRmnkPffG9WFCDkWDxDVaYgMcjd6k X-Proofpoint-GUID: 55YyRmnkPffG9WFCDkWDxDVaYgMcjd6k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-06_01,2026-05-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 adultscore=0 impostorscore=0 malwarescore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605060150 On 5/5/2026 12:29 PM, Vishnu Reddy wrote: > Glymur has a secondary video codec core (vcodec1), equivalent to the > primary core (vcodec0), but with independent power domains, clocks, > and reset lines. Reuse the existing code wherever possible and add > power sequence for vcodec1. > > Signed-off-by: Vishnu Reddy > --- > .../platform/qcom/iris/iris_platform_common.h | 4 + > drivers/media/platform/qcom/iris/iris_vpu3x.c | 137 +++++++++++++++++++++ > drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + > .../platform/qcom/iris/iris_vpu_register_defines.h | 7 ++ > 4 files changed, 149 insertions(+) > > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h > index 7d59e6364e9d..8995136ad29e 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h > @@ -61,6 +61,9 @@ enum platform_clk_type { > IRIS_VPP0_HW_CLK, > IRIS_VPP1_HW_CLK, > IRIS_APV_HW_CLK, > + IRIS_AXI_VCODEC1_CLK, > + IRIS_VCODEC1_CLK, > + IRIS_VCODEC1_FREERUN_CLK, > }; > > struct platform_clk_data { > @@ -210,6 +213,7 @@ enum platform_pm_domain_type { > IRIS_VPP0_HW_POWER_DOMAIN, > IRIS_VPP1_HW_POWER_DOMAIN, > IRIS_APV_HW_POWER_DOMAIN, > + IRIS_VCODEC1_POWER_DOMAIN, > }; > > struct platform_pd_data { > diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c > index 13fbb21c2182..0d0a239f9feb 100644 > --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c > +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c > @@ -27,6 +27,16 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) > return pwr_status ? false : true; > } > > +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) > +{ > + u32 value, pwr_status; > + > + value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); > + pwr_status = value & BIT(4); define these bits position #define VCODEC0_POWER_STATUS BIT(1) #define VCODEC1_POWER_STATUS BIT(4) with this, Reviewed-by: Vikash Garodia