From: Xingyu Wu <xingyu.wu@starfivetech.com>
To: Conor Dooley <conor@kernel.org>
Cc: <linux-riscv@lists.infradead.org>, <devicetree@vger.kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
<linux-kernel@vger.kernel.org>, <linux-clk@vger.kernel.org>
Subject: Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module
Date: Tue, 9 May 2023 14:52:27 +0800 [thread overview]
Message-ID: <735dd2fb-107c-5ecf-4477-70b569cad884@starfivetech.com> (raw)
In-Reply-To: <7527C059-95A2-49EA-AFE0-B089D3651A6B@kernel.org>
On 2023/5/9 14:35, Conor Dooley wrote:
>
>
> On 9 May 2023 07:23:18 IST, Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>>On 2023/5/9 3:24, Conor Dooley wrote:
>>> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote:
>>>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
>>>> > From: William Qiu <william.qiu@starfivetech.com>
>>>> >
>>>> > Add documentation to describe StarFive System Controller Registers.
>>>> >
>>>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>> > ---
>>>> > .../soc/starfive/starfive,jh7110-syscon.yaml | 58 +++++++++++++++++++
>>>> > MAINTAINERS | 6 ++
>>>> > 2 files changed, 64 insertions(+)
>>>> > create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> >
>>>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> > new file mode 100644
>>>> > index 000000000000..de086e74a229
>>>> > --- /dev/null
>>>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> > @@ -0,0 +1,58 @@
>>>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> > +%YAML 1.2
>>>> > +---
>>>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>>> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> > +
>>>> > +title: StarFive JH7110 SoC system controller
>>>> > +
>>>> > +maintainers:
>>>> > + - William Qiu <william.qiu@starfivetech.com>
>>>> > +
>>>> > +description: |
>>>> > + The StarFive JH7110 SoC system controller provides register information such
>>>> > + as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>> > +
>>>> > +properties:
>>>> > + compatible:
>>>> > + oneOf:
>>>> > + - items:
>>>> > + - enum:
>>>> > + - starfive,jh7110-aon-syscon
>>>> > + - starfive,jh7110-sys-syscon
>>>> > + - const: syscon
>>>> > + - const: simple-mfd
>>>> > + - items:
>>>> > + - const: starfive,jh7110-stg-syscon
>>>> > + - const: syscon
>>>> > +
>>>> > + reg:
>>>> > + maxItems: 1
>>>> > +
>>>> > + clock-controller:
>>>> > + $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>>>> > + type: object
>>>> > +
>>>> > + power-controller:
>>>> > + $ref: /schemas/power/starfive,jh7110-pmu.yaml#
>>>> > + type: object
>>>>
>>>> My plan was to grab this patch after the merge window, but there's been
>>>> some back and forth [1] about what exactly should be a power-controller
>>>> here. Given the merge window is open & I know Emil wants to look at the
>>>> various clock bits for the JH7110, I don't think there's a pressing need
>>>> for you to do anything here, but figured I'd at least mention how things
>>>> are going on this thread too.
>>>
>>> To follow up on this, it transpired in that thread that this node, not a
>>> child node, should be the power controller.
>>>
>>> Up to you StarFive folk how you wish to resend, but I am fine with it
>>> being in this series, I shall just not pick up the soc driver patches
>>> until the resent binding is applied by Stephen.
>>>
>>
>>Thanks. I had discussed with changhuang.liang about this. And I will drop
>>the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset.
>>Changhuang will take these in his patchset.
>
> Won't that result in broken bindings, since there's a ref to the pll binding?
> Keeping it in the same series (i.e. this one) makes
> the most sense to me.
>
I will keep the 'sys-syscon' and 'stg-syscon'. The ref just follows the 'sys-syscon'
so I also keep it and the pll binding.
I also hope to add the 'aon-syscon' in this same series but it should be the power
controller, so I have to give up it.
Best regards,
Xingyu Wu
next prev parent reply other threads:[~2023-05-09 6:55 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-14 2:41 [PATCH v3 0/7] Add PLL clocks driver for StarFive JH7110 SoC Xingyu Wu
2023-04-14 2:41 ` [PATCH v3 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-04-14 2:41 ` [PATCH v3 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-04-14 2:41 ` [PATCH v3 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-04-14 2:41 ` [PATCH v3 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source Xingyu Wu
2023-04-14 2:41 ` [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-04-14 12:37 ` Rob Herring
2023-04-17 7:43 ` Xingyu Wu
2023-04-17 20:36 ` Rob Herring
2023-04-17 20:37 ` Rob Herring
2023-04-24 17:15 ` Conor Dooley
2023-05-08 19:24 ` Conor Dooley
2023-05-09 6:23 ` Xingyu Wu
2023-05-09 6:35 ` Conor Dooley
2023-05-09 6:52 ` Xingyu Wu [this message]
2023-05-11 6:59 ` Xingyu Wu
2023-04-14 2:41 ` [PATCH v3 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-04-14 2:41 ` [PATCH v3 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node Xingyu Wu
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