[PATCH v3 0/7] Add PLL clocks driver for StarFive JH7110 SoC

[PATCH v3 0/7] Add PLL clocks driver for StarFive JH7110 SoC

[Xingyu Wu]

This patch serises are to add PLL clocks driver and providers by writing
and reading syscon registers for the StarFive JH7110 RISC-V SoC. And add
documentation to describe StarFive System Controller(syscon) Registers.

PLL are high speed, low jitter frequency synthesizers in JH7110.
Each PLL clocks work in integer mode or fraction mode by some dividers,
and the dividers are set in several syscon registers.
The formula for calculating frequency is: 
Fvco = Fref * (NI + NF) / M / Q1

The first patch adds docunmentation to describe PLL clock bindings,
and the second patch adds driver to support PLL clocks for JH7110.
The patch 3 modifies the SYSCRG dibindings and adds PLL clock inputs.
The patch 4 modifies the system clock driver and changes PLL clock source
from PLL clock controller instead of the fixed factor clocks. The patch 5
adds documentation to decribe syscon registers. And the patch 6 adds the
stg/sys/aon syscon nodes for JH7110 SoC. The last patch adds PLL 
clock node and modifies the syscrg node in JH7110 dts file.

This patchset should be applied after these patchset about JH7110 basic
clock drivers(Accepted and will merged in v6.4)[1].
[1] https://lore.kernel.org/all/20230401111934.130844-1-hal.feng@starfivetech.com/

Changes since v2:
- Rebased on latest JH7110 basic clock drivers.
- Added the complete documentation to describe syscon register.
- Added syscon node in JH7110 dts file.
- Modified the clock rate selection to match the closest rate in
  PLL driver when setting rate.

v2: https://lore.kernel.org/all/20230316030514.137427-1-xingyu.wu@starfivetech.com/

Changes since v1: 
- Changed PLL clock node to be child of syscon node in dts.
- Modifed the definitions and names of function in PLL clock driver.
- Added commit to update syscon and syscrg dt-bindings.

v1: https://lore.kernel.org/all/20230221141147.303642-1-xingyu.wu@starfivetech.com/

William Qiu (2):
  dt-bindings: soc: starfive: Add StarFive syscon module
  riscv: dts: starfive: jh7110: Add syscon nodes

Xingyu Wu (5):
  dt-bindings: clock: Add StarFive JH7110 PLL clock generator
  clk: starfive: Add StarFive JH7110 PLL clock driver
  dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs
  clk: starfive: jh7110-sys: Modify PLL clocks source
  riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg
    node

 .../bindings/clock/starfive,jh7110-pll.yaml   |  46 ++
 .../clock/starfive,jh7110-syscrg.yaml         |  20 +-
 .../soc/starfive/starfive,jh7110-syscon.yaml  |  58 +++
 MAINTAINERS                                   |  12 +
 arch/riscv/boot/dts/starfive/jh7110.dtsi      |  29 +-
 drivers/clk/starfive/Kconfig                  |   9 +
 drivers/clk/starfive/Makefile                 |   1 +
 .../clk/starfive/clk-starfive-jh7110-pll.c    | 427 ++++++++++++++++++
 .../clk/starfive/clk-starfive-jh7110-pll.h    | 293 ++++++++++++
 .../clk/starfive/clk-starfive-jh7110-sys.c    |  31 +-
 .../dt-bindings/clock/starfive,jh7110-crg.h   |   6 +
 11 files changed, 903 insertions(+), 29 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h


base-commit: 197b6b60ae7bc51dd0814953c562833143b292aa
prerequisite-patch-id: 388b8adbb0fe2daf4d07a21eafd4f1bd50ce2403
prerequisite-patch-id: 1117ecaa40a353c667b71802ab34ecf9568d8bb2
prerequisite-patch-id: b00c6b21fbd0353d88b7c9b09093ba30b765f45b
prerequisite-patch-id: 08ec9027e8a5c6fdf201726833168c7464a9b94d
prerequisite-patch-id: fb5120248e48fe1faf053ae0b490c92507ec2b44
prerequisite-patch-id: 4b93d8d590b0a2abe7b4be5287232c494c35be4a
prerequisite-patch-id: 89f049f951e5acf75aab92541992f816fd0acc0d
prerequisite-patch-id: c09c4c68af017b8e5c97b515cb50b70c18a2e705
prerequisite-patch-id: 0df8ccb0e848c2df4c2da95026494bebecede92d
prerequisite-patch-id: 315303931e4b6499de7127a88113763f86e97e16
prerequisite-patch-id: 40cb8212ddb024c20593f73d8b87d9894877e172
prerequisite-patch-id: a1673a9e9f19d6fab5a51abb721e54e36636f067
prerequisite-patch-id: d57cc467fb036241b9276320ff076c4a30d376d6
prerequisite-patch-id: 6e563d68bc5dbf951d4ced17897f9cc4d56169fe
prerequisite-patch-id: 61ec2caa21fd0fc60e57977f7d16d3f72b135745
prerequisite-patch-id: 1387a7e87b446329dfc21f3e575ceae7ebcf954c
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: 9007c8610fdcd387592475949864edde874c20a2
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 0a0ac5a8a90655b415f6b62e324f3db083cdaaee
-- 
2.25.1

[PATCH v3 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator

[Xingyu Wu]

Add bindings for the PLL clock generator on the JH7110 RISC-V SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 .../bindings/clock/starfive,jh7110-pll.yaml   | 46 +++++++++++++++++++
 .../dt-bindings/clock/starfive,jh7110-crg.h   |  6 +++
 2 files changed, 52 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
new file mode 100644
index 000000000000..8aa8c7b8e42f
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 PLL Clock Generator
+
+description:
+  This PLL are high speed, low jitter frequency synthesizers in JH7110.
+  Each PLL clocks work in integer mode or fraction mode by some dividers,
+  and the configuration registers and dividers are set in several syscon
+  registers. So pll node should be a child of SYS-SYSCON node.
+  The formula for calculating frequency is that,
+  Fvco = Fref * (NI + NF) / M / Q1
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+properties:
+  compatible:
+    const: starfive,jh7110-pll
+
+  clocks:
+    maxItems: 1
+    description: Main Oscillator (24 MHz)
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+required:
+  - compatible
+  - clocks
+  - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    pll-clock-controller {
+      compatible = "starfive,jh7110-pll";
+      clocks = <&osc>;
+      #clock-cells = <1>;
+    };
diff --git a/include/dt-bindings/clock/starfive,jh7110-crg.h b/include/dt-bindings/clock/starfive,jh7110-crg.h
index 06257bfd9ac1..086a6ddcf380 100644
--- a/include/dt-bindings/clock/starfive,jh7110-crg.h
+++ b/include/dt-bindings/clock/starfive,jh7110-crg.h
@@ -6,6 +6,12 @@
 #ifndef __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
 #define __DT_BINDINGS_CLOCK_STARFIVE_JH7110_CRG_H__
 
+/* PLL clocks */
+#define JH7110_CLK_PLL0_OUT			0
+#define JH7110_CLK_PLL1_OUT			1
+#define JH7110_CLK_PLL2_OUT			2
+#define JH7110_PLLCLK_END			3
+
 /* SYSCRG clocks */
 #define JH7110_SYSCLK_CPU_ROOT			0
 #define JH7110_SYSCLK_CPU_CORE			1
-- 
2.25.1

[PATCH v3 2/7] clk: starfive: Add StarFive JH7110 PLL clock driver

[Xingyu Wu]

Add driver for the StarFive JH7110 PLL clock controller
and they work by reading and setting syscon registers.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 MAINTAINERS                                   |   6 +
 drivers/clk/starfive/Kconfig                  |   8 +
 drivers/clk/starfive/Makefile                 |   1 +
 .../clk/starfive/clk-starfive-jh7110-pll.c    | 427 ++++++++++++++++++
 .../clk/starfive/clk-starfive-jh7110-pll.h    | 293 ++++++++++++
 5 files changed, 735 insertions(+)
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.c
 create mode 100644 drivers/clk/starfive/clk-starfive-jh7110-pll.h

diff --git a/MAINTAINERS b/MAINTAINERS
index 4c0b39c44957..03051ae2e9e5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19911,6 +19911,12 @@ S:	Supported
 F:	Documentation/devicetree/bindings/mmc/starfive*
 F:	drivers/mmc/host/dw_mmc-starfive.c
 
+STARFIVE JH7110 PLL CLOCK DRIVER
+M:	Xingyu Wu <xingyu.wu@starfivetech.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
+F:	drivers/clk/starfive/clk-starfive-jh7110-pll.*
+
 STARFIVE JH71X0 CLOCK DRIVERS
 M:	Emil Renner Berthing <kernel@esmil.dk>
 M:	Hal Feng <hal.feng@starfivetech.com>
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index 71c1148ee5f6..e306edf4defa 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -21,6 +21,14 @@ config CLK_STARFIVE_JH7100_AUDIO
 	  Say Y or M here to support the audio clocks on the StarFive JH7100
 	  SoC.
 
+config CLK_STARFIVE_JH7110_PLL
+	bool "StarFive JH7110 PLL clock support"
+	depends on ARCH_STARFIVE || COMPILE_TEST
+	default ARCH_STARFIVE
+	help
+	  Say yes here to support the PLL clock controller on the
+	  StarFive JH7110 SoC.
+
 config CLK_STARFIVE_JH7110_SYS
 	bool "StarFive JH7110 system clock support"
 	depends on ARCH_STARFIVE || COMPILE_TEST
diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile
index f3df7d957b1e..b48e539e52b0 100644
--- a/drivers/clk/starfive/Makefile
+++ b/drivers/clk/starfive/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_CLK_STARFIVE_JH71X0)	+= clk-starfive-jh71x0.o
 obj-$(CONFIG_CLK_STARFIVE_JH7100)	+= clk-starfive-jh7100.o
 obj-$(CONFIG_CLK_STARFIVE_JH7100_AUDIO)	+= clk-starfive-jh7100-audio.o
 
+obj-$(CONFIG_CLK_STARFIVE_JH7110_PLL)	+= clk-starfive-jh7110-pll.o
 obj-$(CONFIG_CLK_STARFIVE_JH7110_SYS)	+= clk-starfive-jh7110-sys.o
 obj-$(CONFIG_CLK_STARFIVE_JH7110_AON)	+= clk-starfive-jh7110-aon.o
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.c b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
new file mode 100644
index 000000000000..43d707ea45c7
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.c
@@ -0,0 +1,427 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * StarFive JH7110 PLL Clock Generator Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ *
+ * This driver is about to register JH7110 PLL clock generator and support ops.
+ * The JH7110 have three PLL clock, PLL0, PLL1 and PLL2.
+ * Each PLL clocks work in integer mode or fraction mode by some dividers,
+ * and the configuration registers and dividers are set in several syscon registers.
+ * The formula for calculating frequency is:
+ * Fvco = Fref * (NI + NF) / M / Q1
+ * Fref: OSC source clock rate
+ * NI: integer frequency dividing ratio of feedback divider, set by fbdiv[11:0].
+ * NF: fractional frequency dividing ratio, set by frac[23:0]. NF = frac[23:0] / 2^24 = 0 ~ 0.999.
+ * M: frequency dividing ratio of pre-divider, set by prediv[5:0].
+ * Q1: frequency dividing ratio of post divider, set by postdiv1[1:0], Q1= 1,2,4,8.
+ */
+
+#include <linux/clk-provider.h>
+#include <linux/debugfs.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+#include "clk-starfive-jh7110-pll.h"
+
+static struct jh7110_clk_pll_data *jh7110_pll_data_from(struct clk_hw *hw)
+{
+	return container_of(hw, struct jh7110_clk_pll_data, hw);
+}
+
+static struct jh7110_clk_pll_priv *jh7110_pll_priv_from(struct jh7110_clk_pll_data *data)
+{
+	return container_of(data, struct jh7110_clk_pll_priv, data[data->idx]);
+}
+
+/* Read register value from syscon and calculate PLL(x) frequency */
+static unsigned long jh7110_pll_get_freq(struct jh7110_clk_pll_data *data,
+					 unsigned long parent_rate)
+{
+	struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data);
+	struct jh7110_pll_syscon_offset *offset = &data->offset;
+	struct jh7110_pll_syscon_mask *mask = &data->mask;
+	struct jh7110_pll_syscon_shift *shift = &data->shift;
+	unsigned long freq = 0;
+	unsigned long frac_cal;
+	u32 dacpd;
+	u32 dsmpd;
+	u32 fbdiv;
+	u32 prediv;
+	u32 postdiv1;
+	u32 frac;
+	u32 reg_val;
+
+	if (regmap_read(priv->syscon_regmap, offset->dacpd, &reg_val))
+		goto read_error;
+	dacpd = (reg_val & mask->dacpd) >> shift->dacpd;
+
+	if (regmap_read(priv->syscon_regmap, offset->dsmpd, &reg_val))
+		goto read_error;
+	dsmpd = (reg_val & mask->dsmpd) >> shift->dsmpd;
+
+	if (regmap_read(priv->syscon_regmap, offset->fbdiv, &reg_val))
+		goto read_error;
+	fbdiv = (reg_val & mask->fbdiv) >> shift->fbdiv;
+	/* fbdiv value should be 8 to 4095 */
+	if (fbdiv < 8)
+		goto read_error;
+
+	if (regmap_read(priv->syscon_regmap, offset->prediv, &reg_val))
+		goto read_error;
+	prediv = (reg_val & mask->prediv) >> shift->prediv;
+
+	if (regmap_read(priv->syscon_regmap, offset->postdiv1, &reg_val))
+		goto read_error;
+	/* postdiv1 = 2 ^ reg_val */
+	postdiv1 = 1 << ((reg_val & mask->postdiv1) >> shift->postdiv1);
+
+	if (regmap_read(priv->syscon_regmap, offset->frac, &reg_val))
+		goto read_error;
+	frac = (reg_val & mask->frac) >> shift->frac;
+
+	/*
+	 * Integer Mode (Both 1) or Fraction Mode (Both 0).
+	 * And the decimal places are counted by expanding them by
+	 * a factor of STARFIVE_PLL_FRAC_PATR_SIZE.
+	 */
+	if (dacpd == 1 && dsmpd == 1)
+		frac_cal = 0;
+	else if (dacpd == 0 && dsmpd == 0)
+		frac_cal = (unsigned long)frac * STARFIVE_PLL_FRAC_PATR_SIZE / (1 << 24);
+	else
+		goto read_error;
+
+	/* Fvco = Fref * (NI + NF) / M / Q1 */
+	freq = parent_rate / STARFIVE_PLL_FRAC_PATR_SIZE *
+	       (fbdiv * STARFIVE_PLL_FRAC_PATR_SIZE + frac_cal) / prediv / postdiv1;
+
+read_error:
+	return freq;
+}
+
+static unsigned long jh7110_pll_rate_sub_fabs(unsigned long rate1, unsigned long rate2)
+{
+	return rate1 > rate2 ? (rate1 - rate2) : (rate2 - rate1);
+}
+
+/* Select the appropriate frequency from the already configured registers value */
+static void jh7110_pll_select_near_freq_id(struct jh7110_clk_pll_data *data,
+					   unsigned long rate)
+{
+	const struct starfive_pll_syscon_value *syscon_val;
+	unsigned int id;
+	unsigned int pll_arry_size;
+	unsigned long rate_diff;
+
+	if (data->idx == JH7110_CLK_PLL0_OUT)
+		pll_arry_size = ARRAY_SIZE(jh7110_pll0_syscon_freq);
+	else if (data->idx == JH7110_CLK_PLL1_OUT)
+		pll_arry_size = ARRAY_SIZE(jh7110_pll1_syscon_freq);
+	else
+		pll_arry_size = ARRAY_SIZE(jh7110_pll2_syscon_freq);
+
+	/* compare the frequency one by one from small to large in order */
+	for (id = 0; id < pll_arry_size; id++) {
+		if (data->idx == JH7110_CLK_PLL0_OUT)
+			syscon_val = &jh7110_pll0_syscon_freq[id];
+		else if (data->idx == JH7110_CLK_PLL1_OUT)
+			syscon_val = &jh7110_pll1_syscon_freq[id];
+		else
+			syscon_val = &jh7110_pll2_syscon_freq[id];
+
+		if (rate == syscon_val->freq)
+			goto match_end;
+
+		/* select near frequency */
+		if (rate < syscon_val->freq) {
+			/* The last frequency is closer to the target rate than this time. */
+			if (id > 0)
+				if (rate_diff < jh7110_pll_rate_sub_fabs(rate, syscon_val->freq))
+					id--;
+
+			goto match_end;
+		} else {
+			rate_diff = jh7110_pll_rate_sub_fabs(rate, syscon_val->freq);
+		}
+	}
+
+match_end:
+	data->freq_select_idx = id;
+}
+
+static int jh7110_pll_set_freq_syscon(struct jh7110_clk_pll_data *data)
+{
+	struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data);
+	struct jh7110_pll_syscon_offset *offset = &data->offset;
+	struct jh7110_pll_syscon_mask *mask = &data->mask;
+	struct jh7110_pll_syscon_shift *shift = &data->shift;
+	unsigned int freq_idx = data->freq_select_idx;
+	const struct starfive_pll_syscon_value *syscon_val;
+	int ret;
+
+	if (data->idx == JH7110_CLK_PLL0_OUT)
+		syscon_val = &jh7110_pll0_syscon_freq[freq_idx];
+	else if (data->idx == JH7110_CLK_PLL1_OUT)
+		syscon_val = &jh7110_pll1_syscon_freq[freq_idx];
+	else
+		syscon_val = &jh7110_pll2_syscon_freq[freq_idx];
+
+	ret = regmap_update_bits(priv->syscon_regmap, offset->dacpd, mask->dacpd,
+				 (syscon_val->dacpd << shift->dacpd));
+	if (ret)
+		goto set_failed;
+
+	ret = regmap_update_bits(priv->syscon_regmap, offset->dsmpd, mask->dsmpd,
+				 (syscon_val->dsmpd << shift->dsmpd));
+	if (ret)
+		goto set_failed;
+
+	ret = regmap_update_bits(priv->syscon_regmap, offset->prediv, mask->prediv,
+				 (syscon_val->prediv << shift->prediv));
+	if (ret)
+		goto set_failed;
+
+	ret = regmap_update_bits(priv->syscon_regmap, offset->fbdiv, mask->fbdiv,
+				 (syscon_val->fbdiv << shift->fbdiv));
+	if (ret)
+		goto set_failed;
+
+	ret = regmap_update_bits(priv->syscon_regmap, offset->postdiv1, mask->postdiv1,
+				 ((syscon_val->postdiv1 >> 1) << shift->postdiv1));
+	if (ret)
+		goto set_failed;
+
+	/* frac: Integer Mode (Both 1) or Fraction Mode (Both 0) */
+	if (syscon_val->dacpd == 0 && syscon_val->dsmpd == 0)
+		ret = regmap_update_bits(priv->syscon_regmap, offset->frac, mask->frac,
+					 (syscon_val->frac << shift->frac));
+	else if (syscon_val->dacpd != syscon_val->dsmpd)
+		ret = -EINVAL;
+
+set_failed:
+	return ret;
+}
+
+static unsigned long jh7110_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
+{
+	struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+
+	return jh7110_pll_get_freq(data, parent_rate);
+}
+
+static int jh7110_pll_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
+{
+	struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+
+	jh7110_pll_select_near_freq_id(data, req->rate);
+
+	if (data->idx == JH7110_CLK_PLL0_OUT)
+		req->rate = jh7110_pll0_syscon_freq[data->freq_select_idx].freq;
+	else if (data->idx == JH7110_CLK_PLL1_OUT)
+		req->rate = jh7110_pll1_syscon_freq[data->freq_select_idx].freq;
+	else
+		req->rate = jh7110_pll2_syscon_freq[data->freq_select_idx].freq;
+
+	return 0;
+}
+
+static int jh7110_pll_set_rate(struct clk_hw *hw, unsigned long rate,
+			       unsigned long parent_rate)
+{
+	struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+
+	return jh7110_pll_set_freq_syscon(data);
+}
+
+#ifdef CONFIG_DEBUG_FS
+static void jh7110_pll_debug_init(struct clk_hw *hw, struct dentry *dentry)
+{
+	static const struct debugfs_reg32 jh7110_clk_pll_reg = {
+		.name = "CTRL",
+		.offset = 0,
+	};
+	struct jh7110_clk_pll_data *data = jh7110_pll_data_from(hw);
+	struct jh7110_clk_pll_priv *priv = jh7110_pll_priv_from(data);
+	struct debugfs_regset32 *regset;
+
+	regset = devm_kzalloc(priv->dev, sizeof(*regset), GFP_KERNEL);
+	if (!regset)
+		return;
+
+	regset->regs = &jh7110_clk_pll_reg;
+	regset->nregs = 1;
+
+	debugfs_create_regset32("registers", 0400, dentry, regset);
+}
+#else
+#define jh7110_pll_debug_init NULL
+#endif
+
+static const struct clk_ops jh7110_pll_ops = {
+	.recalc_rate = jh7110_pll_recalc_rate,
+	.determine_rate = jh7110_pll_determine_rate,
+	.set_rate = jh7110_pll_set_rate,
+	.debug_init = jh7110_pll_debug_init,
+};
+
+/* get offset, mask and shift of PLL(x) syscon */
+static int jh7110_pll_data_get(struct jh7110_clk_pll_data *data, int index)
+{
+	struct jh7110_pll_syscon_offset *offset = &data->offset;
+	struct jh7110_pll_syscon_mask *mask = &data->mask;
+	struct jh7110_pll_syscon_shift *shift = &data->shift;
+
+	if (index == JH7110_CLK_PLL0_OUT) {
+		offset->dacpd = STARFIVE_JH7110_PLL0_DACPD_OFFSET;
+		offset->dsmpd = STARFIVE_JH7110_PLL0_DSMPD_OFFSET;
+		offset->fbdiv = STARFIVE_JH7110_PLL0_FBDIV_OFFSET;
+		offset->frac = STARFIVE_JH7110_PLL0_FRAC_OFFSET;
+		offset->prediv = STARFIVE_JH7110_PLL0_PREDIV_OFFSET;
+		offset->postdiv1 = STARFIVE_JH7110_PLL0_POSTDIV1_OFFSET;
+
+		mask->dacpd = STARFIVE_JH7110_PLL0_DACPD_MASK;
+		mask->dsmpd = STARFIVE_JH7110_PLL0_DSMPD_MASK;
+		mask->fbdiv = STARFIVE_JH7110_PLL0_FBDIV_MASK;
+		mask->frac = STARFIVE_JH7110_PLL0_FRAC_MASK;
+		mask->prediv = STARFIVE_JH7110_PLL0_PREDIV_MASK;
+		mask->postdiv1 = STARFIVE_JH7110_PLL0_POSTDIV1_MASK;
+
+		shift->dacpd = STARFIVE_JH7110_PLL0_DACPD_SHIFT;
+		shift->dsmpd = STARFIVE_JH7110_PLL0_DSMPD_SHIFT;
+		shift->fbdiv = STARFIVE_JH7110_PLL0_FBDIV_SHIFT;
+		shift->frac = STARFIVE_JH7110_PLL0_FRAC_SHIFT;
+		shift->prediv = STARFIVE_JH7110_PLL0_PREDIV_SHIFT;
+		shift->postdiv1 = STARFIVE_JH7110_PLL0_POSTDIV1_SHIFT;
+
+	} else if (index == JH7110_CLK_PLL1_OUT) {
+		offset->dacpd = STARFIVE_JH7110_PLL1_DACPD_OFFSET;
+		offset->dsmpd = STARFIVE_JH7110_PLL1_DSMPD_OFFSET;
+		offset->fbdiv = STARFIVE_JH7110_PLL1_FBDIV_OFFSET;
+		offset->frac = STARFIVE_JH7110_PLL1_FRAC_OFFSET;
+		offset->prediv = STARFIVE_JH7110_PLL1_PREDIV_OFFSET;
+		offset->postdiv1 = STARFIVE_JH7110_PLL1_POSTDIV1_OFFSET;
+
+		mask->dacpd = STARFIVE_JH7110_PLL1_DACPD_MASK;
+		mask->dsmpd = STARFIVE_JH7110_PLL1_DSMPD_MASK;
+		mask->fbdiv = STARFIVE_JH7110_PLL1_FBDIV_MASK;
+		mask->frac = STARFIVE_JH7110_PLL1_FRAC_MASK;
+		mask->prediv = STARFIVE_JH7110_PLL1_PREDIV_MASK;
+		mask->postdiv1 = STARFIVE_JH7110_PLL1_POSTDIV1_MASK;
+
+		shift->dacpd = STARFIVE_JH7110_PLL1_DACPD_SHIFT;
+		shift->dsmpd = STARFIVE_JH7110_PLL1_DSMPD_SHIFT;
+		shift->fbdiv = STARFIVE_JH7110_PLL1_FBDIV_SHIFT;
+		shift->frac = STARFIVE_JH7110_PLL1_FRAC_SHIFT;
+		shift->prediv = STARFIVE_JH7110_PLL1_PREDIV_SHIFT;
+		shift->postdiv1 = STARFIVE_JH7110_PLL1_POSTDIV1_SHIFT;
+
+	} else if (index == JH7110_CLK_PLL2_OUT) {
+		offset->dacpd = STARFIVE_JH7110_PLL2_DACPD_OFFSET;
+		offset->dsmpd = STARFIVE_JH7110_PLL2_DSMPD_OFFSET;
+		offset->fbdiv = STARFIVE_JH7110_PLL2_FBDIV_OFFSET;
+		offset->frac = STARFIVE_JH7110_PLL2_FRAC_OFFSET;
+		offset->prediv = STARFIVE_JH7110_PLL2_PREDIV_OFFSET;
+		offset->postdiv1 = STARFIVE_JH7110_PLL2_POSTDIV1_OFFSET;
+
+		mask->dacpd = STARFIVE_JH7110_PLL2_DACPD_MASK;
+		mask->dsmpd = STARFIVE_JH7110_PLL2_DSMPD_MASK;
+		mask->fbdiv = STARFIVE_JH7110_PLL2_FBDIV_MASK;
+		mask->frac = STARFIVE_JH7110_PLL2_FRAC_MASK;
+		mask->prediv = STARFIVE_JH7110_PLL2_PREDIV_MASK;
+		mask->postdiv1 = STARFIVE_JH7110_PLL2_POSTDIV1_MASK;
+
+		shift->dacpd = STARFIVE_JH7110_PLL2_DACPD_SHIFT;
+		shift->dsmpd = STARFIVE_JH7110_PLL2_DSMPD_SHIFT;
+		shift->fbdiv = STARFIVE_JH7110_PLL2_FBDIV_SHIFT;
+		shift->frac = STARFIVE_JH7110_PLL2_FRAC_SHIFT;
+		shift->prediv = STARFIVE_JH7110_PLL2_PREDIV_SHIFT;
+		shift->postdiv1 = STARFIVE_JH7110_PLL2_POSTDIV1_SHIFT;
+
+	} else {
+		return -ENOENT;
+	}
+
+	return 0;
+}
+
+static struct clk_hw *jh7110_pll_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct jh7110_clk_pll_priv *priv = data;
+	unsigned int idx = clkspec->args[0];
+
+	if (idx < JH7110_PLLCLK_END)
+		return &priv->data[idx].hw;
+
+	return ERR_PTR(-EINVAL);
+}
+
+static int jh7110_pll_probe(struct platform_device *pdev)
+{
+	const char *pll_name[JH7110_PLLCLK_END] = {
+		"pll0_out",
+		"pll1_out",
+		"pll2_out"
+	};
+	struct jh7110_clk_pll_priv *priv;
+	struct jh7110_clk_pll_data *data;
+	int ret;
+	unsigned int idx;
+
+	priv = devm_kzalloc(&pdev->dev, struct_size(priv, data, JH7110_PLLCLK_END),
+			    GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	priv->dev = &pdev->dev;
+	priv->syscon_regmap = syscon_node_to_regmap(priv->dev->of_node->parent);
+	if (IS_ERR(priv->syscon_regmap))
+		return PTR_ERR(priv->syscon_regmap);
+
+	for (idx = 0; idx < JH7110_PLLCLK_END; idx++) {
+		struct clk_parent_data parents = {
+			.index = 0,
+		};
+		struct clk_init_data init = {
+			.name = pll_name[idx],
+			.ops = &jh7110_pll_ops,
+			.parent_data = &parents,
+			.num_parents = 1,
+			.flags = 0,
+		};
+
+		data = &priv->data[idx];
+
+		ret = jh7110_pll_data_get(data, idx);
+		if (ret)
+			return ret;
+
+		data->hw.init = &init;
+		data->idx = idx;
+
+		ret = devm_clk_hw_register(&pdev->dev, &data->hw);
+		if (ret)
+			return ret;
+	}
+
+	return devm_of_clk_add_hw_provider(&pdev->dev, jh7110_pll_get, priv);
+}
+
+static const struct of_device_id jh7110_pll_match[] = {
+	{ .compatible = "starfive,jh7110-pll" },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, jh7110_pll_match);
+
+static struct platform_driver jh7110_pll_driver = {
+	.driver = {
+		.name = "clk-starfive-jh7110-pll",
+		.of_match_table = jh7110_pll_match,
+	},
+};
+builtin_platform_driver_probe(jh7110_pll_driver, jh7110_pll_probe);
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-pll.h b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
new file mode 100644
index 000000000000..2cbfa9630c98
--- /dev/null
+++ b/drivers/clk/starfive/clk-starfive-jh7110-pll.h
@@ -0,0 +1,293 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * StarFive JH7110 PLL Clock Generator Driver
+ *
+ * Copyright (C) 2023 StarFive Technology Co., Ltd.
+ */
+
+#ifndef _CLK_STARFIVE_JH7110_PLL_H_
+#define _CLK_STARFIVE_JH7110_PLL_H_
+
+#include <linux/bits.h>
+
+/* The decimal places are counted by expanding them by a factor of STARFIVE_PLL_FRAC_PATR_SIZE */
+#define STARFIVE_PLL_FRAC_PATR_SIZE		1000
+
+#define STARFIVE_JH7110_PLL0_DACPD_OFFSET	0x18
+#define STARFIVE_JH7110_PLL0_DACPD_SHIFT	24
+#define STARFIVE_JH7110_PLL0_DACPD_MASK		BIT(24)
+#define STARFIVE_JH7110_PLL0_DSMPD_OFFSET	0x18
+#define STARFIVE_JH7110_PLL0_DSMPD_SHIFT	25
+#define STARFIVE_JH7110_PLL0_DSMPD_MASK		BIT(25)
+#define STARFIVE_JH7110_PLL0_FBDIV_OFFSET	0x1c
+#define STARFIVE_JH7110_PLL0_FBDIV_SHIFT	0
+#define STARFIVE_JH7110_PLL0_FBDIV_MASK		GENMASK(11, 0)
+#define STARFIVE_JH7110_PLL0_FRAC_OFFSET	0x20
+#define STARFIVE_JH7110_PLL0_FRAC_SHIFT		0
+#define STARFIVE_JH7110_PLL0_FRAC_MASK		GENMASK(23, 0)
+#define STARFIVE_JH7110_PLL0_POSTDIV1_OFFSET	0x20
+#define STARFIVE_JH7110_PLL0_POSTDIV1_SHIFT	28
+#define STARFIVE_JH7110_PLL0_POSTDIV1_MASK	GENMASK(29, 28)
+#define STARFIVE_JH7110_PLL0_PREDIV_OFFSET	0x24
+#define STARFIVE_JH7110_PLL0_PREDIV_SHIFT	0
+#define STARFIVE_JH7110_PLL0_PREDIV_MASK	GENMASK(5, 0)
+
+#define STARFIVE_JH7110_PLL1_DACPD_OFFSET	0x24
+#define STARFIVE_JH7110_PLL1_DACPD_SHIFT	15
+#define STARFIVE_JH7110_PLL1_DACPD_MASK		BIT(15)
+#define STARFIVE_JH7110_PLL1_DSMPD_OFFSET	0x24
+#define STARFIVE_JH7110_PLL1_DSMPD_SHIFT	16
+#define STARFIVE_JH7110_PLL1_DSMPD_MASK		BIT(16)
+#define STARFIVE_JH7110_PLL1_FBDIV_OFFSET	0x24
+#define STARFIVE_JH7110_PLL1_FBDIV_SHIFT	17
+#define STARFIVE_JH7110_PLL1_FBDIV_MASK		GENMASK(28, 17)
+#define STARFIVE_JH7110_PLL1_FRAC_OFFSET	0x28
+#define STARFIVE_JH7110_PLL1_FRAC_SHIFT		0
+#define STARFIVE_JH7110_PLL1_FRAC_MASK		GENMASK(23, 0)
+#define STARFIVE_JH7110_PLL1_POSTDIV1_OFFSET	0x28
+#define STARFIVE_JH7110_PLL1_POSTDIV1_SHIFT	28
+#define STARFIVE_JH7110_PLL1_POSTDIV1_MASK	GENMASK(29, 28)
+#define STARFIVE_JH7110_PLL1_PREDIV_OFFSET	0x2c
+#define STARFIVE_JH7110_PLL1_PREDIV_SHIFT	0
+#define STARFIVE_JH7110_PLL1_PREDIV_MASK	GENMASK(5, 0)
+
+#define STARFIVE_JH7110_PLL2_DACPD_OFFSET	0x2c
+#define STARFIVE_JH7110_PLL2_DACPD_SHIFT	15
+#define STARFIVE_JH7110_PLL2_DACPD_MASK		BIT(15)
+#define STARFIVE_JH7110_PLL2_DSMPD_OFFSET	0x2c
+#define STARFIVE_JH7110_PLL2_DSMPD_SHIFT	16
+#define STARFIVE_JH7110_PLL2_DSMPD_MASK		BIT(16)
+#define STARFIVE_JH7110_PLL2_FBDIV_OFFSET	0x2c
+#define STARFIVE_JH7110_PLL2_FBDIV_SHIFT	17
+#define STARFIVE_JH7110_PLL2_FBDIV_MASK		GENMASK(28, 17)
+#define STARFIVE_JH7110_PLL2_FRAC_OFFSET	0x30
+#define STARFIVE_JH7110_PLL2_FRAC_SHIFT		0
+#define STARFIVE_JH7110_PLL2_FRAC_MASK		GENMASK(23, 0)
+#define STARFIVE_JH7110_PLL2_POSTDIV1_OFFSET	0x30
+#define STARFIVE_JH7110_PLL2_POSTDIV1_SHIFT	28
+#define STARFIVE_JH7110_PLL2_POSTDIV1_MASK	GENMASK(29, 28)
+#define STARFIVE_JH7110_PLL2_PREDIV_OFFSET	0x34
+#define STARFIVE_JH7110_PLL2_PREDIV_SHIFT	0
+#define STARFIVE_JH7110_PLL2_PREDIV_MASK	GENMASK(5, 0)
+
+struct jh7110_pll_syscon_offset {
+	unsigned int dacpd;
+	unsigned int dsmpd;
+	unsigned int fbdiv;
+	unsigned int frac;
+	unsigned int prediv;
+	unsigned int postdiv1;
+};
+
+struct jh7110_pll_syscon_mask {
+	u32 dacpd;
+	u32 dsmpd;
+	u32 fbdiv;
+	u32 frac;
+	u32 prediv;
+	u32 postdiv1;
+};
+
+struct jh7110_pll_syscon_shift {
+	char dacpd;
+	char dsmpd;
+	char fbdiv;
+	char frac;
+	char prediv;
+	char postdiv1;
+};
+
+struct jh7110_clk_pll_data {
+	struct clk_hw hw;
+	unsigned int idx;
+	unsigned int freq_select_idx;
+
+	struct jh7110_pll_syscon_offset offset;
+	struct jh7110_pll_syscon_mask mask;
+	struct jh7110_pll_syscon_shift shift;
+};
+
+struct jh7110_clk_pll_priv {
+	struct device *dev;
+	struct regmap *syscon_regmap;
+	struct jh7110_clk_pll_data data[];
+};
+
+struct starfive_pll_syscon_value {
+	unsigned long freq;
+	u32 prediv;
+	u32 fbdiv;
+	u32 postdiv1;
+/* Both daxpd and dsmpd set 1 while integer mode */
+/* Both daxpd and dsmpd set 0 while fraction mode */
+	u32 dacpd;
+	u32 dsmpd;
+/* frac value should be decimals multiplied by 2^24 */
+	u32 frac;
+};
+
+enum starfive_pll0_freq_index {
+	PLL0_FREQ_375 = 0,
+	PLL0_FREQ_500,
+	PLL0_FREQ_625,
+	PLL0_FREQ_750,
+	PLL0_FREQ_875,
+	PLL0_FREQ_1000,
+	PLL0_FREQ_1250,
+	PLL0_FREQ_1375,
+	PLL0_FREQ_1500,
+	PLL0_FREQ_MAX
+};
+
+enum starfive_pll1_freq_index {
+	PLL1_FREQ_1066 = 0,
+	PLL1_FREQ_1200,
+	PLL1_FREQ_1400,
+	PLL1_FREQ_1600,
+	PLL1_FREQ_MAX
+};
+
+enum starfive_pll2_freq_index {
+	PLL2_FREQ_1188 = 0,
+	PLL2_FREQ_12288,
+	PLL2_FREQ_MAX
+};
+
+/*
+ * Because the pll frequency is relatively fixed,
+ * it cannot be set arbitrarily, so it needs a specific configuration.
+ * PLL0 frequency should be multiple of 125MHz (USB frequency).
+ */
+static const struct starfive_pll_syscon_value
+	jh7110_pll0_syscon_freq[PLL0_FREQ_MAX] = {
+	[PLL0_FREQ_375] = {
+		.freq = 375000000,
+		.prediv = 8,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_500] = {
+		.freq = 500000000,
+		.prediv = 6,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_625] = {
+		.freq = 625000000,
+		.prediv = 24,
+		.fbdiv = 625,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_750] = {
+		.freq = 750000000,
+		.prediv = 4,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_875] = {
+		.freq = 875000000,
+		.prediv = 24,
+		.fbdiv = 875,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_1000] = {
+		.freq = 1000000000,
+		.prediv = 3,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_1250] = {
+		.freq = 1250000000,
+		.prediv = 12,
+		.fbdiv = 625,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_1375] = {
+		.freq = 1375000000,
+		.prediv = 24,
+		.fbdiv = 1375,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL0_FREQ_1500] = {
+		.freq = 1500000000,
+		.prediv = 2,
+		.fbdiv = 125,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+};
+
+static const struct starfive_pll_syscon_value
+	jh7110_pll1_syscon_freq[PLL1_FREQ_MAX] = {
+	[PLL1_FREQ_1066] = {
+		.freq = 1066000000,
+		.prediv = 12,
+		.fbdiv = 533,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL1_FREQ_1200] = {
+		.freq = 1200000000,
+		.prediv = 1,
+		.fbdiv = 50,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL1_FREQ_1400] = {
+		.freq = 1400000000,
+		.prediv = 6,
+		.fbdiv = 350,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL1_FREQ_1600] = {
+		.freq = 1600000000,
+		.prediv = 3,
+		.fbdiv = 200,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+};
+
+static const struct starfive_pll_syscon_value
+	jh7110_pll2_syscon_freq[PLL2_FREQ_MAX] = {
+	[PLL2_FREQ_1188] = {
+		.freq = 1188000000,
+		.prediv = 2,
+		.fbdiv = 99,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+	[PLL2_FREQ_12288] = {
+		.freq = 1228800000,
+		.prediv = 5,
+		.fbdiv = 256,
+		.postdiv1 = 1,
+		.dacpd = 1,
+		.dsmpd = 1,
+	},
+};
+
+#endif
-- 
2.25.1

[PATCH v3 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs

[Xingyu Wu]

Add PLL clock inputs from PLL clock generator.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 .../clock/starfive,jh7110-syscrg.yaml         | 20 +++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
index 84373ae31644..55d4e7f09cd5 100644
--- a/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
+++ b/Documentation/devicetree/bindings/clock/starfive,jh7110-syscrg.yaml
@@ -27,6 +27,9 @@ properties:
           - description: External I2S RX left/right channel clock
           - description: External TDM clock
           - description: External audio master clock
+          - description: PLL0
+          - description: PLL1
+          - description: PLL2
 
       - items:
           - description: Main Oscillator (24 MHz)
@@ -38,6 +41,9 @@ properties:
           - description: External I2S RX left/right channel clock
           - description: External TDM clock
           - description: External audio master clock
+          - description: PLL0
+          - description: PLL1
+          - description: PLL2
 
   clock-names:
     oneOf:
@@ -52,6 +58,9 @@ properties:
           - const: i2srx_lrck_ext
           - const: tdm_ext
           - const: mclk_ext
+          - const: pll0_out
+          - const: pll1_out
+          - const: pll2_out
 
       - items:
           - const: osc
@@ -63,6 +72,9 @@ properties:
           - const: i2srx_lrck_ext
           - const: tdm_ext
           - const: mclk_ext
+          - const: pll0_out
+          - const: pll1_out
+          - const: pll2_out
 
   '#clock-cells':
     const: 1
@@ -93,12 +105,16 @@ examples:
                  <&gmac1_rgmii_rxin>,
                  <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
                  <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-                 <&tdm_ext>, <&mclk_ext>;
+                 <&tdm_ext>, <&mclk_ext>,
+                 <&pllclk JH7110_CLK_PLL0_OUT>,
+                 <&pllclk JH7110_CLK_PLL1_OUT>,
+                 <&pllclk JH7110_CLK_PLL2_OUT>;
         clock-names = "osc", "gmac1_rmii_refin",
                       "gmac1_rgmii_rxin",
                       "i2stx_bclk_ext", "i2stx_lrck_ext",
                       "i2srx_bclk_ext", "i2srx_lrck_ext",
-                      "tdm_ext", "mclk_ext";
+                      "tdm_ext", "mclk_ext",
+                      "pll0_out", "pll1_out", "pll2_out";
         #clock-cells = <1>;
         #reset-cells = <1>;
     };
-- 
2.25.1

[PATCH v3 4/7] clk: starfive: jh7110-sys: Modify PLL clocks source

[Xingyu Wu]

Modify PLL clocks source to be got from dts instead of
the fixed factor clocks.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 drivers/clk/starfive/Kconfig                  |  1 +
 .../clk/starfive/clk-starfive-jh7110-sys.c    | 31 ++++---------------
 2 files changed, 7 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index e306edf4defa..903a5097c642 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -35,6 +35,7 @@ config CLK_STARFIVE_JH7110_SYS
 	select AUXILIARY_BUS
 	select CLK_STARFIVE_JH71X0
 	select RESET_STARFIVE_JH7110
+	select CLK_STARFIVE_JH7110_PLL
 	default ARCH_STARFIVE
 	help
 	  Say yes here to support the system clock controller on the
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 5ec210644e1d..439999dc2191 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -395,29 +395,6 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
 
 	dev_set_drvdata(priv->dev, (void *)(&priv->base));
 
-	/*
-	 * These PLL clocks are not actually fixed factor clocks and can be
-	 * controlled by the syscon registers of JH7110. They will be dropped
-	 * and registered in the PLL clock driver instead.
-	 */
-	/* 24MHz -> 1000.0MHz */
-	priv->pll[0] = devm_clk_hw_register_fixed_factor(priv->dev, "pll0_out",
-							 "osc", 0, 125, 3);
-	if (IS_ERR(priv->pll[0]))
-		return PTR_ERR(priv->pll[0]);
-
-	/* 24MHz -> 1066.0MHz */
-	priv->pll[1] = devm_clk_hw_register_fixed_factor(priv->dev, "pll1_out",
-							 "osc", 0, 533, 12);
-	if (IS_ERR(priv->pll[1]))
-		return PTR_ERR(priv->pll[1]);
-
-	/* 24MHz -> 1188.0MHz */
-	priv->pll[2] = devm_clk_hw_register_fixed_factor(priv->dev, "pll2_out",
-							 "osc", 0, 99, 2);
-	if (IS_ERR(priv->pll[2]))
-		return PTR_ERR(priv->pll[2]);
-
 	for (idx = 0; idx < JH7110_SYSCLK_END; idx++) {
 		u32 max = jh7110_sysclk_data[idx].max;
 		struct clk_parent_data parents[4] = {};
@@ -455,8 +432,12 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
 				parents[i].fw_name = "tdm_ext";
 			else if (pidx == JH7110_SYSCLK_MCLK_EXT)
 				parents[i].fw_name = "mclk_ext";
-			else
-				parents[i].hw = priv->pll[pidx - JH7110_SYSCLK_PLL0_OUT];
+			else if (pidx == JH7110_SYSCLK_PLL0_OUT)
+				parents[i].fw_name = "pll0_out";
+			else if (pidx == JH7110_SYSCLK_PLL1_OUT)
+				parents[i].fw_name = "pll1_out";
+			else if (pidx == JH7110_SYSCLK_PLL2_OUT)
+				parents[i].fw_name = "pll2_out";
 		}
 
 		clk->hw.init = &init;
-- 
2.25.1

[PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Xingyu Wu]

From: William Qiu <william.qiu@starfivetech.com>

Add documentation to describe StarFive System Controller Registers.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
---
 .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
 MAINTAINERS                                   |  6 ++
 2 files changed, 64 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml

diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
new file mode 100644
index 000000000000..de086e74a229
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 SoC system controller
+
+maintainers:
+  - William Qiu <william.qiu@starfivetech.com>
+
+description: |
+  The StarFive JH7110 SoC system controller provides register information such
+  as offset, mask and shift to configure related modules such as MMC and PCIe.
+
+properties:
+  compatible:
+    oneOf:
+      - items:
+          - enum:
+              - starfive,jh7110-aon-syscon
+              - starfive,jh7110-sys-syscon
+          - const: syscon
+          - const: simple-mfd
+      - items:
+          - const: starfive,jh7110-stg-syscon
+          - const: syscon
+
+  reg:
+    maxItems: 1
+
+  clock-controller:
+    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
+    type: object
+
+  power-controller:
+    $ref: /schemas/power/starfive,jh7110-pmu.yaml#
+    type: object
+
+required:
+  - compatible
+  - reg
+
+additionalProperties: false
+
+examples:
+  - |
+    syscon@10240000 {
+        compatible = "starfive,jh7110-stg-syscon", "syscon";
+        reg = <0x10240000 0x1000>;
+    };
+
+    syscon@13030000 {
+        compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+        reg = <0x13030000 0x1000>;
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 03051ae2e9e5..0fafeea8ebdb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19917,6 +19917,11 @@ S:	Supported
 F:	Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
 F:	drivers/clk/starfive/clk-starfive-jh7110-pll.*
 
+STARFIVE JH7110 SYSCON
+M:	William Qiu <william.qiu@starfivetech.com>
+S:	Supported
+F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
+
 STARFIVE JH71X0 CLOCK DRIVERS
 M:	Emil Renner Berthing <kernel@esmil.dk>
 M:	Hal Feng <hal.feng@starfivetech.com>
@@ -19954,6 +19959,7 @@ STARFIVE SOC DRIVERS
 M:	Conor Dooley <conor@kernel.org>
 S:	Maintained
 T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
+F:	Documentation/devicetree/bindings/soc/starfive/
 F:	drivers/soc/starfive/
 
 STARFIVE TRNG DRIVER
-- 
2.25.1

[PATCH v3 6/7] riscv: dts: starfive: jh7110: Add syscon nodes

[Xingyu Wu]

From: William Qiu <william.qiu@starfivetech.com>

Add stg_syscon/sys_syscon/aon_syscon nodes for JH7110 Soc.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 4c5fdb905da8..f271c3184d3a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -353,6 +353,11 @@ i2c2: i2c@10050000 {
 			status = "disabled";
 		};
 
+		stg_syscon: syscon@10240000 {
+			compatible = "starfive,jh7110-stg-syscon", "syscon";
+			reg = <0x0 0x10240000 0x0 0x1000>;
+		};
+
 		uart3: serial@12000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x0 0x12000000 0x0 0x10000>;
@@ -457,6 +462,11 @@ syscrg: clock-controller@13020000 {
 			#reset-cells = <1>;
 		};
 
+		sys_syscon: syscon@13030000 {
+			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x13030000 0x0 0x1000>;
+		};
+
 		sysgpio: pinctrl@13040000 {
 			compatible = "starfive,jh7110-sys-pinctrl";
 			reg = <0x0 0x13040000 0x0 0x10000>;
@@ -486,6 +496,11 @@ aoncrg: clock-controller@17000000 {
 			#reset-cells = <1>;
 		};
 
+		aon_syscon: syscon@17010000 {
+			compatible = "starfive,jh7110-aon-syscon", "syscon", "simple-mfd";
+			reg = <0x0 0x17010000 0x0 0x1000>;
+		};
+
 		aongpio: pinctrl@17020000 {
 			compatible = "starfive,jh7110-aon-pinctrl";
 			reg = <0x0 0x17020000 0x0 0x10000>;
-- 
2.25.1

[PATCH v3 7/7] riscv: dts: starfive: jh7110: Add PLL clock node and modify syscrg node

[Xingyu Wu]

Add the PLL clock node for the Starfive JH7110 SoC and
modify the SYSCRG node to add PLL clocks input.

Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
---
 arch/riscv/boot/dts/starfive/jh7110.dtsi | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index f271c3184d3a..27f8ef37d029 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 {
 				 <&gmac1_rgmii_rxin>,
 				 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
 				 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
-				 <&tdm_ext>, <&mclk_ext>;
+				 <&tdm_ext>, <&mclk_ext>,
+				 <&pllclk JH7110_CLK_PLL0_OUT>,
+				 <&pllclk JH7110_CLK_PLL1_OUT>,
+				 <&pllclk JH7110_CLK_PLL2_OUT>;
 			clock-names = "osc", "gmac1_rmii_refin",
 				      "gmac1_rgmii_rxin",
 				      "i2stx_bclk_ext", "i2stx_lrck_ext",
 				      "i2srx_bclk_ext", "i2srx_lrck_ext",
-				      "tdm_ext", "mclk_ext";
+				      "tdm_ext", "mclk_ext",
+				      "pll0_out", "pll1_out", "pll2_out";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 		};
@@ -465,6 +469,12 @@ syscrg: clock-controller@13020000 {
 		sys_syscon: syscon@13030000 {
 			compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
 			reg = <0x0 0x13030000 0x0 0x1000>;
+
+			pllclk: clock-controller {
+				compatible = "starfive,jh7110-pll";
+				clocks = <&osc>;
+				#clock-cells = <1>;
+			};
 		};
 
 		sysgpio: pinctrl@13040000 {
-- 
2.25.1

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Rob Herring]

On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote:
> From: William Qiu <william.qiu@starfivetech.com>
> 
> Add documentation to describe StarFive System Controller Registers.
> 
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>  MAINTAINERS                                   |  6 ++
>  2 files changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-6-xingyu.wu@starfivetech.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Xingyu Wu]

On 2023/4/14 20:37, Rob Herring wrote:
> 
> On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote:
>> From: William Qiu <william.qiu@starfivetech.com>
>> 
>> Add documentation to describe StarFive System Controller Registers.
>> 
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> ---
>>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>>  MAINTAINERS                                   |  6 ++
>>  2 files changed, 64 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> 
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> ./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml
> 
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-6-xingyu.wu@starfivetech.com
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
> 

I have updated yamllint and dtschema, and tested it and didn't see this error.
I asked william and also didn't see this. This error says the file:
http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml was not found.
This file is added in patch 1 but patch 1 should be applied after these patchset
about JH7110 basic clock drivers. I don't know if that's the reason.

Best regards,
Xingyu Wu

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Rob Herring]

On Mon, Apr 17, 2023 at 03:43:48PM +0800, Xingyu Wu wrote:
> On 2023/4/14 20:37, Rob Herring wrote:
> > 
> > On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote:
> >> From: William Qiu <william.qiu@starfivetech.com>
> >> 
> >> Add documentation to describe StarFive System Controller Registers.
> >> 
> >> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> >> ---
> >>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
> >>  MAINTAINERS                                   |  6 ++
> >>  2 files changed, 64 insertions(+)
> >>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> >> 
> > 
> > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> > on your patch (DT_CHECKER_FLAGS is new in v5.13):
> > 
> > yamllint warnings/errors:
> > 
> > dtschema/dtc warnings/errors:
> > ./Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml: Unable to find schema file matching $id: http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml
> > 
> > doc reference errors (make refcheckdocs):
> > 
> > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-6-xingyu.wu@starfivetech.com
> > 
> > The base for the series is generally the latest rc1. A different dependency
> > should be noted in *this* patch.
> > 
> > If you already ran 'make dt_binding_check' and didn't see the above
> > error(s), then make sure 'yamllint' is installed and dt-schema is up to
> > date:
> > 
> > pip3 install dtschema --upgrade
> > 
> > Please check and re-submit after running the above command yourself. Note
> > that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> > your schema. However, it must be unset to test all examples with your schema.
> > 
> 
> I have updated yamllint and dtschema, and tested it and didn't see this error.
> I asked william and also didn't see this. This error says the file:
> http://devicetree.org/schemas/clock/starfive,jh7110-pll.yaml was not found.
> This file is added in patch 1 but patch 1 should be applied after these patchset
> about JH7110 basic clock drivers. I don't know if that's the reason.

Yes, patch 1 could not be applied[1].

Rob

[1] https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230414024157.53203-2-xingyu.wu@starfivetech.com/

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Rob Herring]

On Fri, 14 Apr 2023 10:41:55 +0800, Xingyu Wu wrote:
> From: William Qiu <william.qiu@starfivetech.com>
> 
> Add documentation to describe StarFive System Controller Registers.
> 
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>  MAINTAINERS                                   |  6 ++
>  2 files changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 3931 bytes --]

On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
> From: William Qiu <william.qiu@starfivetech.com>
> 
> Add documentation to describe StarFive System Controller Registers.
> 
> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> ---
>  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>  MAINTAINERS                                   |  6 ++
>  2 files changed, 64 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> 
> diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> new file mode 100644
> index 000000000000..de086e74a229
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> @@ -0,0 +1,58 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive JH7110 SoC system controller
> +
> +maintainers:
> +  - William Qiu <william.qiu@starfivetech.com>
> +
> +description: |
> +  The StarFive JH7110 SoC system controller provides register information such
> +  as offset, mask and shift to configure related modules such as MMC and PCIe.
> +
> +properties:
> +  compatible:
> +    oneOf:
> +      - items:
> +          - enum:
> +              - starfive,jh7110-aon-syscon
> +              - starfive,jh7110-sys-syscon
> +          - const: syscon
> +          - const: simple-mfd
> +      - items:
> +          - const: starfive,jh7110-stg-syscon
> +          - const: syscon
> +
> +  reg:
> +    maxItems: 1
> +
> +  clock-controller:
> +    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> +    type: object
> +
> +  power-controller:
> +    $ref: /schemas/power/starfive,jh7110-pmu.yaml#
> +    type: object

My plan was to grab this patch after the merge window, but there's been
some back and forth [1] about what exactly should be a power-controller
here. Given the merge window is open & I know Emil wants to look at the
various clock bits for the JH7110, I don't think there's a pressing need
for you to do anything here, but figured I'd at least mention how things
are going on this thread too.

Thanks,
Conor.

1 - https://lore.kernel.org/linux-riscv/20230419035646.43702-1-changhuang.liang@starfivetech.com/T/#m708770e9596098214df769bcc2bdaf9c1a46ca98

> +
> +required:
> +  - compatible
> +  - reg
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    syscon@10240000 {
> +        compatible = "starfive,jh7110-stg-syscon", "syscon";
> +        reg = <0x10240000 0x1000>;
> +    };
> +
> +    syscon@13030000 {
> +        compatible = "starfive,jh7110-sys-syscon", "syscon", "simple-mfd";
> +        reg = <0x13030000 0x1000>;
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 03051ae2e9e5..0fafeea8ebdb 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -19917,6 +19917,11 @@ S:	Supported
>  F:	Documentation/devicetree/bindings/clock/starfive,jh7110-pll.yaml
>  F:	drivers/clk/starfive/clk-starfive-jh7110-pll.*
>  
> +STARFIVE JH7110 SYSCON
> +M:	William Qiu <william.qiu@starfivetech.com>
> +S:	Supported
> +F:	Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> +
>  STARFIVE JH71X0 CLOCK DRIVERS
>  M:	Emil Renner Berthing <kernel@esmil.dk>
>  M:	Hal Feng <hal.feng@starfivetech.com>
> @@ -19954,6 +19959,7 @@ STARFIVE SOC DRIVERS
>  M:	Conor Dooley <conor@kernel.org>
>  S:	Maintained
>  T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
> +F:	Documentation/devicetree/bindings/soc/starfive/
>  F:	drivers/soc/starfive/
>  
>  STARFIVE TRNG DRIVER
> -- 
> 2.25.1
> 

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Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Conor Dooley]

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On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote:
> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
> > From: William Qiu <william.qiu@starfivetech.com>
> > 
> > Add documentation to describe StarFive System Controller Registers.
> > 
> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
> > ---
> >  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
> >  MAINTAINERS                                   |  6 ++
> >  2 files changed, 64 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> > 
> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> > new file mode 100644
> > index 000000000000..de086e74a229
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
> > @@ -0,0 +1,58 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: StarFive JH7110 SoC system controller
> > +
> > +maintainers:
> > +  - William Qiu <william.qiu@starfivetech.com>
> > +
> > +description: |
> > +  The StarFive JH7110 SoC system controller provides register information such
> > +  as offset, mask and shift to configure related modules such as MMC and PCIe.
> > +
> > +properties:
> > +  compatible:
> > +    oneOf:
> > +      - items:
> > +          - enum:
> > +              - starfive,jh7110-aon-syscon
> > +              - starfive,jh7110-sys-syscon
> > +          - const: syscon
> > +          - const: simple-mfd
> > +      - items:
> > +          - const: starfive,jh7110-stg-syscon
> > +          - const: syscon
> > +
> > +  reg:
> > +    maxItems: 1
> > +
> > +  clock-controller:
> > +    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
> > +    type: object
> > +
> > +  power-controller:
> > +    $ref: /schemas/power/starfive,jh7110-pmu.yaml#
> > +    type: object
> 
> My plan was to grab this patch after the merge window, but there's been
> some back and forth [1] about what exactly should be a power-controller
> here. Given the merge window is open & I know Emil wants to look at the
> various clock bits for the JH7110, I don't think there's a pressing need
> for you to do anything here, but figured I'd at least mention how things
> are going on this thread too.

To follow up on this, it transpired in that thread that this node, not a
child node, should be the power controller.

Up to you StarFive folk how you wish to resend, but I am fine with it
being in this series, I shall just not pick up the soc driver patches
until the resent binding is applied by Stephen.

Thanks,
Conor.

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Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Xingyu Wu]

On 2023/5/9 3:24, Conor Dooley wrote:
> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote:
>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
>> > From: William Qiu <william.qiu@starfivetech.com>
>> > 
>> > Add documentation to describe StarFive System Controller Registers.
>> > 
>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> > ---
>> >  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>> >  MAINTAINERS                                   |  6 ++
>> >  2 files changed, 64 insertions(+)
>> >  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> > 
>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> > new file mode 100644
>> > index 000000000000..de086e74a229
>> > --- /dev/null
>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>> > @@ -0,0 +1,58 @@
>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> > +%YAML 1.2
>> > +---
>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> > +
>> > +title: StarFive JH7110 SoC system controller
>> > +
>> > +maintainers:
>> > +  - William Qiu <william.qiu@starfivetech.com>
>> > +
>> > +description: |
>> > +  The StarFive JH7110 SoC system controller provides register information such
>> > +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>> > +
>> > +properties:
>> > +  compatible:
>> > +    oneOf:
>> > +      - items:
>> > +          - enum:
>> > +              - starfive,jh7110-aon-syscon
>> > +              - starfive,jh7110-sys-syscon
>> > +          - const: syscon
>> > +          - const: simple-mfd
>> > +      - items:
>> > +          - const: starfive,jh7110-stg-syscon
>> > +          - const: syscon
>> > +
>> > +  reg:
>> > +    maxItems: 1
>> > +
>> > +  clock-controller:
>> > +    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>> > +    type: object
>> > +
>> > +  power-controller:
>> > +    $ref: /schemas/power/starfive,jh7110-pmu.yaml#
>> > +    type: object
>> 
>> My plan was to grab this patch after the merge window, but there's been
>> some back and forth [1] about what exactly should be a power-controller
>> here. Given the merge window is open & I know Emil wants to look at the
>> various clock bits for the JH7110, I don't think there's a pressing need
>> for you to do anything here, but figured I'd at least mention how things
>> are going on this thread too.
> 
> To follow up on this, it transpired in that thread that this node, not a
> child node, should be the power controller.
> 
> Up to you StarFive folk how you wish to resend, but I am fine with it
> being in this series, I shall just not pick up the soc driver patches
> until the resent binding is applied by Stephen.
> 

Thanks. I had discussed with changhuang.liang about this. And I will drop
the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset.
Changhuang will take these in his patchset.

Best regards,
Xingyu Wu

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Conor Dooley]

On 9 May 2023 07:23:18 IST, Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>On 2023/5/9 3:24, Conor Dooley wrote:
>> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote:
>>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
>>> > From: William Qiu <william.qiu@starfivetech.com>
>>> > 
>>> > Add documentation to describe StarFive System Controller Registers.
>>> > 
>>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> > ---
>>> >  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>>> >  MAINTAINERS                                   |  6 ++
>>> >  2 files changed, 64 insertions(+)
>>> >  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> > 
>>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> > new file mode 100644
>>> > index 000000000000..de086e74a229
>>> > --- /dev/null
>>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>> > @@ -0,0 +1,58 @@
>>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>> > +%YAML 1.2
>>> > +---
>>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>> > +
>>> > +title: StarFive JH7110 SoC system controller
>>> > +
>>> > +maintainers:
>>> > +  - William Qiu <william.qiu@starfivetech.com>
>>> > +
>>> > +description: |
>>> > +  The StarFive JH7110 SoC system controller provides register information such
>>> > +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>>> > +
>>> > +properties:
>>> > +  compatible:
>>> > +    oneOf:
>>> > +      - items:
>>> > +          - enum:
>>> > +              - starfive,jh7110-aon-syscon
>>> > +              - starfive,jh7110-sys-syscon
>>> > +          - const: syscon
>>> > +          - const: simple-mfd
>>> > +      - items:
>>> > +          - const: starfive,jh7110-stg-syscon
>>> > +          - const: syscon
>>> > +
>>> > +  reg:
>>> > +    maxItems: 1
>>> > +
>>> > +  clock-controller:
>>> > +    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>>> > +    type: object
>>> > +
>>> > +  power-controller:
>>> > +    $ref: /schemas/power/starfive,jh7110-pmu.yaml#
>>> > +    type: object
>>> 
>>> My plan was to grab this patch after the merge window, but there's been
>>> some back and forth [1] about what exactly should be a power-controller
>>> here. Given the merge window is open & I know Emil wants to look at the
>>> various clock bits for the JH7110, I don't think there's a pressing need
>>> for you to do anything here, but figured I'd at least mention how things
>>> are going on this thread too.
>> 
>> To follow up on this, it transpired in that thread that this node, not a
>> child node, should be the power controller.
>> 
>> Up to you StarFive folk how you wish to resend, but I am fine with it
>> being in this series, I shall just not pick up the soc driver patches
>> until the resent binding is applied by Stephen.
>> 
>
>Thanks. I had discussed with changhuang.liang about this. And I will drop
>the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset.
>Changhuang will take these in his patchset.

Won't that result in broken bindings, since there's a ref to the pll binding?
Keeping it in the same series (i.e. this one) makes
the most sense to me.

Cheers,
Conor.

>
>Best regards,
>Xingyu Wu
>

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Xingyu Wu]

On 2023/5/9 14:35, Conor Dooley wrote:
> 
> 
> On 9 May 2023 07:23:18 IST, Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>>On 2023/5/9 3:24, Conor Dooley wrote:
>>> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote:
>>>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
>>>> > From: William Qiu <william.qiu@starfivetech.com>
>>>> > 
>>>> > Add documentation to describe StarFive System Controller Registers.
>>>> > 
>>>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>> > ---
>>>> >  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>>>> >  MAINTAINERS                                   |  6 ++
>>>> >  2 files changed, 64 insertions(+)
>>>> >  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> > 
>>>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> > new file mode 100644
>>>> > index 000000000000..de086e74a229
>>>> > --- /dev/null
>>>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>> > @@ -0,0 +1,58 @@
>>>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>> > +%YAML 1.2
>>>> > +---
>>>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>>> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>> > +
>>>> > +title: StarFive JH7110 SoC system controller
>>>> > +
>>>> > +maintainers:
>>>> > +  - William Qiu <william.qiu@starfivetech.com>
>>>> > +
>>>> > +description: |
>>>> > +  The StarFive JH7110 SoC system controller provides register information such
>>>> > +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>> > +
>>>> > +properties:
>>>> > +  compatible:
>>>> > +    oneOf:
>>>> > +      - items:
>>>> > +          - enum:
>>>> > +              - starfive,jh7110-aon-syscon
>>>> > +              - starfive,jh7110-sys-syscon
>>>> > +          - const: syscon
>>>> > +          - const: simple-mfd
>>>> > +      - items:
>>>> > +          - const: starfive,jh7110-stg-syscon
>>>> > +          - const: syscon
>>>> > +
>>>> > +  reg:
>>>> > +    maxItems: 1
>>>> > +
>>>> > +  clock-controller:
>>>> > +    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>>>> > +    type: object
>>>> > +
>>>> > +  power-controller:
>>>> > +    $ref: /schemas/power/starfive,jh7110-pmu.yaml#
>>>> > +    type: object
>>>> 
>>>> My plan was to grab this patch after the merge window, but there's been
>>>> some back and forth [1] about what exactly should be a power-controller
>>>> here. Given the merge window is open & I know Emil wants to look at the
>>>> various clock bits for the JH7110, I don't think there's a pressing need
>>>> for you to do anything here, but figured I'd at least mention how things
>>>> are going on this thread too.
>>> 
>>> To follow up on this, it transpired in that thread that this node, not a
>>> child node, should be the power controller.
>>> 
>>> Up to you StarFive folk how you wish to resend, but I am fine with it
>>> being in this series, I shall just not pick up the soc driver patches
>>> until the resent binding is applied by Stephen.
>>> 
>>
>>Thanks. I had discussed with changhuang.liang about this. And I will drop
>>the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset.
>>Changhuang will take these in his patchset.
> 
> Won't that result in broken bindings, since there's a ref to the pll binding?
> Keeping it in the same series (i.e. this one) makes
> the most sense to me.
> 

I will keep the 'sys-syscon' and 'stg-syscon'. The ref just follows the 'sys-syscon'
so I also keep it and the pll binding.
I also hope to add the 'aon-syscon' in this same series but it should be the power
controller, so I have to give up it.

Best regards,
Xingyu Wu

Re: [PATCH v3 5/7] dt-bindings: soc: starfive: Add StarFive syscon module

[Xingyu Wu]

On 2023/5/9 14:52, Xingyu Wu wrote:
> On 2023/5/9 14:35, Conor Dooley wrote:
>> 
>> 
>> On 9 May 2023 07:23:18 IST, Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>>>On 2023/5/9 3:24, Conor Dooley wrote:
>>>> On Mon, Apr 24, 2023 at 06:15:47PM +0100, Conor Dooley wrote:
>>>>> On Fri, Apr 14, 2023 at 10:41:55AM +0800, Xingyu Wu wrote:
>>>>> > From: William Qiu <william.qiu@starfivetech.com>
>>>>> > 
>>>>> > Add documentation to describe StarFive System Controller Registers.
>>>>> > 
>>>>> > Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>>>> > ---
>>>>> >  .../soc/starfive/starfive,jh7110-syscon.yaml  | 58 +++++++++++++++++++
>>>>> >  MAINTAINERS                                   |  6 ++
>>>>> >  2 files changed, 64 insertions(+)
>>>>> >  create mode 100644 Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>>> > 
>>>>> > diff --git a/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>>> > new file mode 100644
>>>>> > index 000000000000..de086e74a229
>>>>> > --- /dev/null
>>>>> > +++ b/Documentation/devicetree/bindings/soc/starfive/starfive,jh7110-syscon.yaml
>>>>> > @@ -0,0 +1,58 @@
>>>>> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>>>>> > +%YAML 1.2
>>>>> > +---
>>>>> > +$id: http://devicetree.org/schemas/soc/starfive/starfive,jh7110-syscon.yaml#
>>>>> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
>>>>> > +
>>>>> > +title: StarFive JH7110 SoC system controller
>>>>> > +
>>>>> > +maintainers:
>>>>> > +  - William Qiu <william.qiu@starfivetech.com>
>>>>> > +
>>>>> > +description: |
>>>>> > +  The StarFive JH7110 SoC system controller provides register information such
>>>>> > +  as offset, mask and shift to configure related modules such as MMC and PCIe.
>>>>> > +
>>>>> > +properties:
>>>>> > +  compatible:
>>>>> > +    oneOf:
>>>>> > +      - items:
>>>>> > +          - enum:
>>>>> > +              - starfive,jh7110-aon-syscon
>>>>> > +              - starfive,jh7110-sys-syscon
>>>>> > +          - const: syscon
>>>>> > +          - const: simple-mfd
>>>>> > +      - items:
>>>>> > +          - const: starfive,jh7110-stg-syscon
>>>>> > +          - const: syscon
>>>>> > +
>>>>> > +  reg:
>>>>> > +    maxItems: 1
>>>>> > +
>>>>> > +  clock-controller:
>>>>> > +    $ref: /schemas/clock/starfive,jh7110-pll.yaml#
>>>>> > +    type: object
>>>>> > +
>>>>> > +  power-controller:
>>>>> > +    $ref: /schemas/power/starfive,jh7110-pmu.yaml#
>>>>> > +    type: object
>>>>> 
>>>>> My plan was to grab this patch after the merge window, but there's been
>>>>> some back and forth [1] about what exactly should be a power-controller
>>>>> here. Given the merge window is open & I know Emil wants to look at the
>>>>> various clock bits for the JH7110, I don't think there's a pressing need
>>>>> for you to do anything here, but figured I'd at least mention how things
>>>>> are going on this thread too.
>>>> 
>>>> To follow up on this, it transpired in that thread that this node, not a
>>>> child node, should be the power controller.
>>>> 
>>>> Up to you StarFive folk how you wish to resend, but I am fine with it
>>>> being in this series, I shall just not pick up the soc driver patches
>>>> until the resent binding is applied by Stephen.
>>>> 
>>>
>>>Thanks. I had discussed with changhuang.liang about this. And I will drop
>>>the 'starfive,jh7110-aon-syscon' and 'power-controller' in next patchset.
>>>Changhuang will take these in his patchset.
>> 
>> Won't that result in broken bindings, since there's a ref to the pll binding?
>> Keeping it in the same series (i.e. this one) makes
>> the most sense to me.
>> 
> 
> I will keep the 'sys-syscon' and 'stg-syscon'. The ref just follows the 'sys-syscon'
> so I also keep it and the pll binding.
> I also hope to add the 'aon-syscon' in this same series but it should be the power
> controller, so I have to give up it.
> 

I synchronized with Chang Huang. It is decided to keep 'aon-syscon' as the power
controller in this and do not add child node in 'aon-syscon'.
And I will update it in the next version of patch.

Best regards,
Xingyu Wu