Re: Re: [PATCH v11 1/6] clk: sunxi-ng: h6-r: Add RTC gate clock

Jernej Škrabec
2022-05-06T16:12:09Z

Dne torek, 03. maj 2022 ob 04:06:59 CEST je Samuel Holland napisal(a):
> On 4/28/22 6:09 PM, Andre Przywara wrote:
> > The H6 and H616 feature an (undocumented) bus clock gate for accessing
> > the RTC registers. This seems to be enabled at reset (or by the BootROM),
> > so we got away without it so far, but exists regardless.
> > Since the new RTC clock binding for the H616 requires this "bus" clock
> > to be specified in the DT, add this to R_CCU clock driver and expose it
> > on the DT side with a new number.
> > We do this for both the H6 and H616, but mark it as IGNORE_UNUSED, as we
> > cannot reference it in any H6 DTs.
> >
> > Signed-off-by: Andre Przywara <andre.przywara@arm.com>
>
> Reviewed-by: Samuel Holland <samuel@sholland.org>
>
> One tiny nit below, if you resend.

Fixed and applied to sunxi/clk-for-5.19, thanks!

Best regards,
Jernej

>
> > ---
> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 5 +++++
> > drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h | 2 +-
> > include/dt-bindings/clock/sun50i-h6-r-ccu.h | 1 +
> > 3 files changed, 7 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c b/drivers/clk/sunxi-ng/
ccu-sun50i-h6-r.c
> > index 712e103382d8..88509339031e 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
> > @@ -98,6 +98,8 @@ static SUNXI_CCU_GATE(r_apb1_ir_clk, "r-apb1-ir",
"r-apb1",
> > 0x1cc, BIT(0), 0);
> > static SUNXI_CCU_GATE(r_apb1_w1_clk, "r-apb1-w1", "r-apb1",
> > 0x1ec, BIT(0), 0);
> > +static SUNXI_CCU_GATE(r_apb1_rtc_clk, "r-apb1-rtc", "r-apb1",
> > + 0x20c, BIT(0), CLK_IGNORE_UNUSED);
> >
> > /* Information of IR(RX) mod clock is gathered from BSP source code */
> > static const char * const r_mod0_default_parents[] = { "osc32k", "osc24M"
};
> > @@ -147,6 +149,7 @@ static struct ccu_common *sun50i_h616_r_ccu_clks[] = {
> > &r_apb2_i2c_clk.common,
> > &r_apb2_rsb_clk.common,
> > &r_apb1_ir_clk.common,
> > + &r_apb1_rtc_clk.common,
> > &ir_clk.common,
> > };
> >
> > @@ -163,6 +166,7 @@ static struct clk_hw_onecell_data sun50i_h6_r_hw_clks
= {
> > [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
> > [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
> > [CLK_R_APB1_IR] =
&r_apb1_ir_clk.common.hw,
> > + [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
> > [CLK_R_APB1_W1] =
&r_apb1_w1_clk.common.hw,
>
> The new clock should go after CLK_R_APB1_W1 to match the ordering above.
>
> > [CLK_IR] = &ir_clk.common.hw,
> > [CLK_W1] = &w1_clk.common.hw,
> > @@ -179,6 +183,7 @@ static struct clk_hw_onecell_data
sun50i_h616_r_hw_clks = {
> > [CLK_R_APB2_I2C] = &r_apb2_i2c_clk.common.hw,
> > [CLK_R_APB2_RSB] = &r_apb2_rsb_clk.common.hw,
> > [CLK_R_APB1_IR] =
&r_apb1_ir_clk.common.hw,
> > + [CLK_R_APB1_RTC] = &r_apb1_rtc_clk.common.hw,
> > [CLK_IR] = &ir_clk.common.hw,
> > },
> > .num = CLK_NUMBER,
> > diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h b/drivers/clk/sunxi-ng/
ccu-sun50i-h6-r.h
> > index 7e290b840803..10e9b66afc6a 100644
> > --- a/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
> > +++ b/drivers/clk/sunxi-ng/ccu-sun50i-h6-r.h
> > @@ -14,6 +14,6 @@
> >
> > #define CLK_R_APB2 3
> >
> > -#define CLK_NUMBER (CLK_R_APB2_RSB + 1)
> > +#define CLK_NUMBER (CLK_R_APB1_RTC + 1)
> >
> > #endif /* _CCU_SUN50I_H6_R_H */
> > diff --git a/include/dt-bindings/clock/sun50i-h6-r-ccu.h b/include/dt-
bindings/clock/sun50i-h6-r-ccu.h
> > index 890368d252c4..a96087abc86f 100644
> > --- a/include/dt-bindings/clock/sun50i-h6-r-ccu.h
> > +++ b/include/dt-bindings/clock/sun50i-h6-r-ccu.h
> > @@ -22,5 +22,6 @@
> > #define CLK_W1 12
> >
> > #define CLK_R_APB2_RSB 13
> > +#define CLK_R_APB1_RTC 14
> >
> > #endif /* _DT_BINDINGS_CLK_SUN50I_H6_R_CCU_H_ */
> >
>
>