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Thu, 11 Jun 2026 04:05:31 -0700 (PDT) X-Received: by 2002:a05:620a:1713:b0:902:daaf:22cd with SMTP id af79cd13be357-9160a4f660cmr192684285a.0.1781175930499; Thu, 11 Jun 2026 04:05:30 -0700 (PDT) Received: from [192.168.120.170] ([178.235.128.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-68e65867e7dsm10880036a12.20.2026.06.11.04.05.28 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 11 Jun 2026 04:05:29 -0700 (PDT) Message-ID: <73f700f2-7cba-4832-bd06-e82a7fd51a7a@oss.qualcomm.com> Date: Thu, 11 Jun 2026 13:05:26 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 5/8] irqchip/qcom-pdc: Configure PDC to pass through mode To: Maulik Shah , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Gleixner , Linus Walleij Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, Sneh Mankad References: <20260526-hamoa_pdc-v2-0-f6857af1ce91@oss.qualcomm.com> <20260526-hamoa_pdc-v2-5-f6857af1ce91@oss.qualcomm.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20260526-hamoa_pdc-v2-5-f6857af1ce91@oss.qualcomm.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=GbMnWwXL c=1 sm=1 tr=0 ts=6a2a967b cx=c_pps a=JbAStetqSzwMeJznSMzCyw==:117 a=PRfkaYvzSr8QmIIGAkY2Sg==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=avOr_zNKPfybmo9zg3EA:9 a=QEXdDO2ut3YA:10 a=uxP6HrT_eTzRwkO_Te1X:22 X-Proofpoint-ORIG-GUID: Pwwa-fi3RbCPLZwD6hmsW_I-j66l4jXc X-Proofpoint-GUID: Pwwa-fi3RbCPLZwD6hmsW_I-j66l4jXc X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjExMDExMSBTYWx0ZWRfX6nFoVRWMIehg 3vVUxcVkO9UMs6IAJWCCmp0ogCoxb9gzB6rsH8ldKHFe0BMylWxS+990wRWSruXeVLNhHN3uuYR kOrwDs55l+iJ6zzSYAdn7nlO4Jw5PHlw36fTH0vztyNsFlcs38QhcsoebF7NKZqq92EEhLPBZuK SfrrQTAwE5AfmxSKbHm6oWxxasgjlrnpxVa4xrHK6X3O5lBCTys3LIXyZ9MUo0X0SIRh94GJiJ+ yygQG5KwRT1McF4WnwQpSC5Ooww9kfso1nJJV4CZK/wcoeb1CVfSzQQ8NPnPlSS/onpKVHYm+5/ TTuxYMLlS3rY7MmnFiZBWkimwymC/n/xfMe5OT4b3JZ/cPCFCE7JI6YxN3v5KwMjQTH+5bZQXLC 4e4K0troWp8yWvKHRxoD77bHp1CDFJUNgQs/2o9nxCCxPwmgHvPgucQ50FDgEHeKktN/eqGZoLs P4mV87c6+K3nYx5oZSA== X-Proofpoint-Spam-Info: AW1haW4tMjYwNjExMDExMSBTYWx0ZWRfX9kUEATUXFxEF XqfJcxoDKJJwwIKosJT5fIxbb/cNw4BupLP25Jpgol2nKp6Whv9q6k7gLgzuLUVTAdqnDUFnm7M jtmbD589hJAwkKVf735kU0h4ezqBQ/A= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-11_02,2026-06-09_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 priorityscore=1501 bulkscore=0 adultscore=0 spamscore=0 impostorscore=0 clxscore=1015 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606110111 On 5/26/26 12:54 PM, Maulik Shah wrote: > All PDC irqchip supports pass through mode in which both Direct SPIs and > GPIO IRQs (as SPIs) are sent to GIC without latching at PDC. > > Newer PDCs (v3.0 onwards) also support additional secondary controller mode > where PDC latches GPIO IRQs and sends to GIC as level type IRQ. Direct SPIs > still works same as pass through mode without latching at PDC even in > secondary controller mode. > > All the SoCs so far default uses pass through mode with the exception of > x1e. x1e PDC may be set to secondary controller mode for builds on CRD > boards whereas it may be set to pass through mode for IoT-EVK boards. > The mode configuration is done in firmware and initially shipped windows > firmware did not have SCM interface to read or modify the PDC mode. > Later only write access is opened up for non secure world. > > Using the write access available add changes to modify the PDC mode to > pass through mode via SCM write. When the write fails (on older firmware) > assume to work in secondary mode. > > Co-developed-by: Sneh Mankad > Signed-off-by: Sneh Mankad > Signed-off-by: Maulik Shah > --- [...] > +static inline bool pdc_pin_uses_seconary_mode(int pin_out) Please add a comment somewhere near here, repeating what you said in the previous commit message (about the SPIs being mapped first, followed by GPIO-as-SPIs) Konrad