[PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920

devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed

* [PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920
       [not found] <CGME20241231063730epcas5p4137cc2e3d805cb08e1675b056ef186dc@epcas5p4.samsung.com>
@ 2024-12-31  6:43 ` Devang Tailor
  2024-12-31  7:43   ` Krzysztof Kozlowski
  0 siblings, 1 reply; 3+ messages in thread
From: Devang Tailor @ 2024-12-31  6:43 UTC (permalink / raw)
  To: alim.akhtar, dev.tailor, robh, krzk+dt, conor+dt
  Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel

Add CPU caches information to its dt nodes so that the same is
available to userspace via sysfs. This SoC has 64/64 KB I/D cache
for each cores and 256KB of L2 cache.

Signed-off-by: Devang Tailor <dev.tailor@samsung.com>
---
 .../arm64/boot/dts/exynos/exynosautov920.dtsi | 79 +++++++++++++++++++
 1 file changed, 79 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index eb446cdc4ab6..3ca4c8902aa1 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -89,6 +89,13 @@ cpu0: cpu@0 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x0>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu1: cpu@100 {
@@ -96,6 +103,13 @@ cpu1: cpu@100 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x100>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu2: cpu@200 {
@@ -103,6 +117,13 @@ cpu2: cpu@200 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x200>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu3: cpu@300 {
@@ -110,6 +131,13 @@ cpu3: cpu@300 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x300>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu4: cpu@10000 {
@@ -117,6 +145,13 @@ cpu4: cpu@10000 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x10000>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu5: cpu@10100 {
@@ -124,6 +159,13 @@ cpu5: cpu@10100 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x10100>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu6: cpu@10200 {
@@ -131,6 +173,13 @@ cpu6: cpu@10200 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x10200>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu7: cpu@10300 {
@@ -138,6 +187,13 @@ cpu7: cpu@10300 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x10300>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu8: cpu@20000 {
@@ -145,6 +201,13 @@ cpu8: cpu@20000 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x20000>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
 		};
 
 		cpu9: cpu@20100 {
@@ -152,6 +215,22 @@ cpu9: cpu@20100 {
 			compatible = "arm,cortex-a78ae";
 			reg = <0x0 0x20100>;
 			enable-method = "psci";
+			i-cache-size = <0x10000>;
+			i-cache-line-size = <64>;
+			i-cache-sets = <256>;
+			d-cache-size = <0x10000>;
+			d-cache-line-size = <64>;
+			d-cache-sets = <256>;
+			next-level-cache = <&cpu_l2>;
+		};
+
+		cpu_l2: l2-cache0 {
+			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
+			cache-size = <0x40000>;
+			cache-line-size = <64>;
+			cache-sets = <512>;
 		};
 	};
 
-- 
2.34.1


^ permalink raw reply related	[flat|nested] 3+ messages in thread

* Re: [PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920
  2024-12-31  6:43 ` [PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920 Devang Tailor
@ 2024-12-31  7:43   ` Krzysztof Kozlowski
  2025-01-06  8:39     ` Devang Tailor
  0 siblings, 1 reply; 3+ messages in thread
From: Krzysztof Kozlowski @ 2024-12-31  7:43 UTC (permalink / raw)
  To: Devang Tailor, alim.akhtar, robh, krzk+dt, conor+dt
  Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel

On 31/12/2024 07:43, Devang Tailor wrote:
>  
>  		cpu9: cpu@20100 {
> @@ -152,6 +215,22 @@ cpu9: cpu@20100 {
>  			compatible = "arm,cortex-a78ae";
>  			reg = <0x0 0x20100>;
>  			enable-method = "psci";
> +			i-cache-size = <0x10000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x10000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&cpu_l2>;
> +		};
> +
> +		cpu_l2: l2-cache0 {

Are there more l2-caches? '0' suggests that, so please add nodes for all
of them.



Best regards,
Krzysztof

^ permalink raw reply	[flat|nested] 3+ messages in thread

* RE: [PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920
  2024-12-31  7:43   ` Krzysztof Kozlowski
@ 2025-01-06  8:39     ` Devang Tailor
  0 siblings, 0 replies; 3+ messages in thread
From: Devang Tailor @ 2025-01-06  8:39 UTC (permalink / raw)
  To: 'Krzysztof Kozlowski', alim.akhtar, robh, krzk+dt,
	conor+dt
  Cc: devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel,
	'Faraz Ata'

Hi krzysztof,


-----Original Message-----
From: Krzysztof Kozlowski <krzk@kernel.org> 
Sent: 31 December 2024 13:13
To: Devang Tailor <dev.tailor@samsung.com>; alim.akhtar@samsung.com; robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org
Cc: devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; linux-kernel@vger.kernel.org
Subject: Re: [PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920

On 31/12/2024 07:43, Devang Tailor wrote:
>  
>  		cpu9: cpu@20100 {
> @@ -152,6 +215,22 @@ cpu9: cpu@20100 {
>  			compatible = "arm,cortex-a78ae";
>  			reg = <0x0 0x20100>;
>  			enable-method = "psci";
> +			i-cache-size = <0x10000>;
> +			i-cache-line-size = <64>;
> +			i-cache-sets = <256>;
> +			d-cache-size = <0x10000>;
> +			d-cache-line-size = <64>;
> +			d-cache-sets = <256>;
> +			next-level-cache = <&cpu_l2>;
> +		};
> +
> +		cpu_l2: l2-cache0 {

Are there more l2-caches? '0' suggests that, so please add nodes for all of them.
>
Thank you Krzysztof for your review. I will update other caches in v2 patch.


Best regards,
Krzysztof


^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2025-01-06 10:44 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
     [not found] <CGME20241231063730epcas5p4137cc2e3d805cb08e1675b056ef186dc@epcas5p4.samsung.com>
2024-12-31  6:43 ` [PATCH] arm64: dts: add cpu cache information to ExynosAuto-v920 Devang Tailor
2024-12-31  7:43   ` Krzysztof Kozlowski
2025-01-06  8:39     ` Devang Tailor

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).