* [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 [not found] <1629458622-4915-1-git-send-email-okukatla@codeaurora.org> @ 2021-08-20 11:23 ` Odelu Kukatla 2021-08-23 20:44 ` Rob Herring 2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla 1 sibling, 1 reply; 8+ messages in thread From: Odelu Kukatla @ 2021-08-20 11:23 UTC (permalink / raw) To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Georgi Djakov, Rob Herring, Sibi Sankar, linux-arm-msm, linux-pm, devicetree, linux-kernel Cc: sboyd, mdtipton, saravanak, okukatla, seansw, elder, linux-arm-msm-owner Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++- include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml index e701524..919fce4 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml @@ -18,13 +18,20 @@ properties: compatible: enum: - qcom,sc7180-osm-l3 + - qcom,sc7280-epss-l3 - qcom,sc8180x-osm-l3 - qcom,sdm845-osm-l3 - qcom,sm8150-osm-l3 - qcom,sm8250-epss-l3 reg: - maxItems: 1 + minItems: 1 + maxItems: 4 + items: + - description: OSM clock domain-0 base address and size + - description: OSM clock domain-1 base address and size + - description: OSM clock domain-2 base address and size + - description: OSM clock domain-3 base address and size clocks: items: diff --git a/include/dt-bindings/interconnect/qcom,osm-l3.h b/include/dt-bindings/interconnect/qcom,osm-l3.h index 61ef649..99534a5 100644 --- a/include/dt-bindings/interconnect/qcom,osm-l3.h +++ b/include/dt-bindings/interconnect/qcom,osm-l3.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0 */ /* - * Copyright (C) 2019 The Linux Foundation. All rights reserved. + * Copyright (C) 2019, 2021 The Linux Foundation. All rights reserved. */ #ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H @@ -11,5 +11,13 @@ #define MASTER_EPSS_L3_APPS 0 #define SLAVE_EPSS_L3_SHARED 1 +#define SLAVE_EPSS_L3_CPU0 2 +#define SLAVE_EPSS_L3_CPU1 3 +#define SLAVE_EPSS_L3_CPU2 4 +#define SLAVE_EPSS_L3_CPU3 5 +#define SLAVE_EPSS_L3_CPU4 6 +#define SLAVE_EPSS_L3_CPU5 7 +#define SLAVE_EPSS_L3_CPU6 8 +#define SLAVE_EPSS_L3_CPU7 9 #endif -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla @ 2021-08-23 20:44 ` Rob Herring 0 siblings, 0 replies; 8+ messages in thread From: Rob Herring @ 2021-08-23 20:44 UTC (permalink / raw) To: Odelu Kukatla Cc: elder, linux-kernel, evgreen, linux-pm, Rob Herring, Georgi Djakov, mdtipton, Andy Gross, linux-arm-msm-owner, devicetree, seansw, saravanak, sboyd, linux-arm-msm, bjorn.andersson, Sibi Sankar, georgi.djakov On Fri, 20 Aug 2021 16:53:39 +0530, Odelu Kukatla wrote: > Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > .../devicetree/bindings/interconnect/qcom,osm-l3.yaml | 9 ++++++++- > include/dt-bindings/interconnect/qcom,osm-l3.h | 10 +++++++++- > 2 files changed, 17 insertions(+), 2 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 8+ messages in thread
* [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider [not found] <1629458622-4915-1-git-send-email-okukatla@codeaurora.org> 2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla @ 2021-08-20 11:23 ` Odelu Kukatla 2021-09-03 19:06 ` Stephen Boyd 1 sibling, 1 reply; 8+ messages in thread From: Odelu Kukatla @ 2021-08-20 11:23 UTC (permalink / raw) To: georgi.djakov, bjorn.andersson, evgreen, Andy Gross, Rob Herring, linux-arm-msm, devicetree, linux-kernel Cc: sboyd, mdtipton, sibis, saravanak, okukatla, seansw, elder, linux-pm, linux-arm-msm-owner Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 SoCs. Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 53a21d0..cf59b47 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -1848,6 +1848,17 @@ }; }; + epss_l3: interconnect@18590000 { + compatible = "qcom,sc7280-epss-l3"; + reg = <0 0x18590000 0 1000>, + <0 0x18591000 0 0x100>, + <0 0x18592000 0 0x100>, + <0 0x18593000 0 0x100>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + #interconnect-cells = <1>; + }; + cpufreq_hw: cpufreq@18591000 { compatible = "qcom,cpufreq-epss"; reg = <0 0x18591100 0 0x900>, -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla @ 2021-09-03 19:06 ` Stephen Boyd 2021-09-15 5:05 ` okukatla 0 siblings, 1 reply; 8+ messages in thread From: Stephen Boyd @ 2021-09-03 19:06 UTC (permalink / raw) To: Andy Gross, Odelu Kukatla, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel Cc: mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner Quoting Odelu Kukatla (2021-08-20 04:23:41) > Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > SoCs. > > Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ > 1 file changed, 11 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 53a21d0..cf59b47 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -1848,6 +1848,17 @@ > }; > }; > > + epss_l3: interconnect@18590000 { > + compatible = "qcom,sc7280-epss-l3"; > + reg = <0 0x18590000 0 1000>, Is this supposed to be 0x1000? > + <0 0x18591000 0 0x100>, > + <0 0x18592000 0 0x100>, > + <0 0x18593000 0 0x100>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; > + clock-names = "xo", "alternate"; > + #interconnect-cells = <1>; > + }; > + > cpufreq_hw: cpufreq@18591000 { > compatible = "qcom,cpufreq-epss"; > reg = <0 0x18591100 0 0x900>, > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-09-03 19:06 ` Stephen Boyd @ 2021-09-15 5:05 ` okukatla 2021-09-15 6:26 ` okukatla 0 siblings, 1 reply; 8+ messages in thread From: okukatla @ 2021-09-15 5:05 UTC (permalink / raw) To: Stephen Boyd Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner On 2021-09-04 00:36, Stephen Boyd wrote: > Quoting Odelu Kukatla (2021-08-20 04:23:41) >> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >> SoCs. >> >> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> --- >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ >> 1 file changed, 11 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> index 53a21d0..cf59b47 100644 >> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> @@ -1848,6 +1848,17 @@ >> }; >> }; >> >> + epss_l3: interconnect@18590000 { >> + compatible = "qcom,sc7280-epss-l3"; >> + reg = <0 0x18590000 0 1000>, > > Is this supposed to be 0x1000? > No, This is 1000 or 0x3E8. >> + <0 0x18591000 0 0x100>, >> + <0 0x18592000 0 0x100>, >> + <0 0x18593000 0 0x100>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >> GCC_GPLL0>; >> + clock-names = "xo", "alternate"; >> + #interconnect-cells = <1>; >> + }; >> + >> cpufreq_hw: cpufreq@18591000 { >> compatible = "qcom,cpufreq-epss"; >> reg = <0 0x18591100 0 0x900>, >> -- >> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >> Forum, >> a Linux Foundation Collaborative Project >> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-09-15 5:05 ` okukatla @ 2021-09-15 6:26 ` okukatla 2021-09-15 19:40 ` Stephen Boyd 0 siblings, 1 reply; 8+ messages in thread From: okukatla @ 2021-09-15 6:26 UTC (permalink / raw) To: Stephen Boyd Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner, okukatla=codeaurora.org On 2021-09-15 10:35, okukatla@codeaurora.org wrote: > On 2021-09-04 00:36, Stephen Boyd wrote: >> Quoting Odelu Kukatla (2021-08-20 04:23:41) >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >>> SoCs. >>> >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >>> --- >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ >>> 1 file changed, 11 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> index 53a21d0..cf59b47 100644 >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >>> @@ -1848,6 +1848,17 @@ >>> }; >>> }; >>> >>> + epss_l3: interconnect@18590000 { >>> + compatible = "qcom,sc7280-epss-l3"; >>> + reg = <0 0x18590000 0 1000>, >> >> Is this supposed to be 0x1000? >> > No, This is 1000 or 0x3E8. We have mapped only required registers for L3 scaling, 1000/0x3E8 is suffice. But i will update it to 0x1000 in next revision so that entire clock domain region-0 is mapped. >>> + <0 0x18591000 0 0x100>, >>> + <0 0x18592000 0 0x100>, >>> + <0 0x18593000 0 0x100>; >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >>> GCC_GPLL0>; >>> + clock-names = "xo", "alternate"; >>> + #interconnect-cells = <1>; >>> + }; >>> + >>> cpufreq_hw: cpufreq@18591000 { >>> compatible = "qcom,cpufreq-epss"; >>> reg = <0 0x18591100 0 0x900>, >>> -- >>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora >>> Forum, >>> a Linux Foundation Collaborative Project >>> ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-09-15 6:26 ` okukatla @ 2021-09-15 19:40 ` Stephen Boyd 2021-09-16 8:00 ` okukatla 0 siblings, 1 reply; 8+ messages in thread From: Stephen Boyd @ 2021-09-15 19:40 UTC (permalink / raw) To: okukatla Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner, okukatla=codeaurora.org Quoting okukatla@codeaurora.org (2021-09-14 23:26:19) > On 2021-09-15 10:35, okukatla@codeaurora.org wrote: > > On 2021-09-04 00:36, Stephen Boyd wrote: > >> Quoting Odelu Kukatla (2021-08-20 04:23:41) > >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 > >>> SoCs. > >>> > >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> > >>> --- > >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ > >>> 1 file changed, 11 insertions(+) > >>> > >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> index 53a21d0..cf59b47 100644 > >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > >>> @@ -1848,6 +1848,17 @@ > >>> }; > >>> }; > >>> > >>> + epss_l3: interconnect@18590000 { > >>> + compatible = "qcom,sc7280-epss-l3"; > >>> + reg = <0 0x18590000 0 1000>, > >> > >> Is this supposed to be 0x1000? > >> > > No, This is 1000 or 0x3E8. Wow ok. Why is it the only size that isn't in hex format? Please try to be consistent and use hex throughout. > We have mapped only required registers for L3 scaling, 1000/0x3E8 is > suffice. > But i will update it to 0x1000 in next revision so that entire clock > domain region-0 is mapped. Doesn't that conflict with the cpufreq-hw device? > >>> + <0 0x18591000 0 0x100>, > >>> + <0 0x18592000 0 0x100>, > >>> + <0 0x18593000 0 0x100>; > >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc > >>> GCC_GPLL0>; > >>> + clock-names = "xo", "alternate"; > >>> + #interconnect-cells = <1>; > >>> + }; > >>> + > >>> cpufreq_hw: cpufreq@18591000 { > >>> compatible = "qcom,cpufreq-epss"; > >>> reg = <0 0x18591100 0 0x900>, ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider 2021-09-15 19:40 ` Stephen Boyd @ 2021-09-16 8:00 ` okukatla 0 siblings, 0 replies; 8+ messages in thread From: okukatla @ 2021-09-16 8:00 UTC (permalink / raw) To: Stephen Boyd Cc: Andy Gross, Rob Herring, bjorn.andersson, devicetree, evgreen, georgi.djakov, linux-arm-msm, linux-kernel, mdtipton, sibis, saravanak, seansw, elder, linux-pm, linux-arm-msm-owner, okukatla=codeaurora.org On 2021-09-16 01:10, Stephen Boyd wrote: > Quoting okukatla@codeaurora.org (2021-09-14 23:26:19) >> On 2021-09-15 10:35, okukatla@codeaurora.org wrote: >> > On 2021-09-04 00:36, Stephen Boyd wrote: >> >> Quoting Odelu Kukatla (2021-08-20 04:23:41) >> >>> Add Epoch Subsystem (EPSS) L3 interconnect provider node on SC7280 >> >>> SoCs. >> >>> >> >>> Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org> >> >>> --- >> >>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 11 +++++++++++ >> >>> 1 file changed, 11 insertions(+) >> >>> >> >>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> index 53a21d0..cf59b47 100644 >> >>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi >> >>> @@ -1848,6 +1848,17 @@ >> >>> }; >> >>> }; >> >>> >> >>> + epss_l3: interconnect@18590000 { >> >>> + compatible = "qcom,sc7280-epss-l3"; >> >>> + reg = <0 0x18590000 0 1000>, >> >> >> >> Is this supposed to be 0x1000? >> >> >> > No, This is 1000 or 0x3E8. > > Wow ok. Why is it the only size that isn't in hex format? Please try to > be consistent and use hex throughout. > Sure, will update it to hex format in new revision. >> We have mapped only required registers for L3 scaling, 1000/0x3E8 is >> suffice. >> But i will update it to 0x1000 in next revision so that entire clock >> domain region-0 is mapped. > > Doesn't that conflict with the cpufreq-hw device? > epss_l3 maps (0x18590000, size:0x1000) region which cpufreq-hw does not need. I will update size to 0x1000 for this region only. >> >>> + <0 0x18591000 0 0x100>, >> >>> + <0 0x18592000 0 0x100>, >> >>> + <0 0x18593000 0 0x100>; >> >>> + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc >> >>> GCC_GPLL0>; >> >>> + clock-names = "xo", "alternate"; >> >>> + #interconnect-cells = <1>; >> >>> + }; >> >>> + >> >>> cpufreq_hw: cpufreq@18591000 { >> >>> compatible = "qcom,cpufreq-epss"; >> >>> reg = <0 0x18591100 0 0x900>, ^ permalink raw reply [flat|nested] 8+ messages in thread
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[not found] <1629458622-4915-1-git-send-email-okukatla@codeaurora.org>
2021-08-20 11:23 ` [v7 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-08-23 20:44 ` Rob Herring
2021-08-20 11:23 ` [v7 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-09-03 19:06 ` Stephen Boyd
2021-09-15 5:05 ` okukatla
2021-09-15 6:26 ` okukatla
2021-09-15 19:40 ` Stephen Boyd
2021-09-16 8:00 ` okukatla
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