From mboxrd@z Thu Jan 1 00:00:00 1970 From: Stephen Warren Subject: RE: [PATCH V3] ARM: tegra: Define Tegra20 CAR binding Date: Wed, 15 Feb 2012 13:30:59 -0800 Message-ID: <74CDBE0F657A3D45AFBB94109FB122FF178FACB957@HQMAIL01.nvidia.com> References: <1329329667-26725-1-git-send-email-swarren@nvidia.com> <74CDBE0F657A3D45AFBB94109FB122FF178FACB8D6@HQMAIL01.nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: Content-Language: en-US Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Simon Glass Cc: Olof Johansson , Colin Cross , Grant Likely , "rob.herring-bsGFqQB8/DxBDgjK7y7TUQ@public.gmane.org" , Peter De Schrijver , Devicetree Discuss , "linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" List-Id: devicetree@vger.kernel.org Simon Glass wrote at Wednesday, February 15, 2012 1:25 PM: > On Wed, Feb 15, 2012 at 11:14 AM, Stephen Warren wrote: > > Simon Glass wrote at Wednesday, February 15, 2012 11:45 AM: > >> On Wed, Feb 15, 2012 at 10:14 AM, Stephen Warren wrote: > >> > The Tegra20 CAR (Clock And Reset) Controller controls most aspects of > >> > most clocks within Tegra20. The device tree binding models this as a > >> > single monolithic clock provider, which exports ~130 clocks. This reduces > >> > the number of nodes needed in device tree to represent these clocks. > >> > > >> > This binding is only useful for Tegra20; the set of clocks that exists on > >> > Tegra30 is sufficiently different to merit its own binding. > >> > >> It seems there is a large common element - they are almost backwards > >> compatible. Should we not at least look at this now? > > > > I don't believe there's any need for the clock IDs for the two chips to > > align in any way. These are two different chips, with different sets of > > clocks, different tegra*.dtsi files, different clock "drivers" that define > > the available clocks, etc. > > > > And while as you say, there are a lot of similarities, there are also a > > number of differences within these first 96 clocks which make having > > things completely aligned impractical. I imagine you'd rather that > > Tegra30's binding follow Tegra30's CLK_OUT_ENB register layouts exactly, > > rather than attempting to align with Tegra20 even in the face of > > differences in HW. > > OK my question was really more about how you deal with multi-arch in > Linux / U-Boot. Does it make sense to ignore the commonality. Perhaps > instead the range from 96 to 160 should be reserved? I'm having a hard time seeing the problem here; the correct mapping from device tree clock ID values to clock objects will be selected based on the SoC version you're running on; there's no need to try and tie the clock IDs for the two SoCs together, and there's always a way to know which SoC version's numbering you should be dealing with at runtime. -- nvpublic