Re: [PATCH 3/5] riscv: dts: add initial T-HEAD light SoC device tree

["Heiko Stübner" <heiko@sntech.de>]

Am Montag, 8. Mai 2023, 05:32:17 CEST schrieb Icenowy Zheng:
> 在 2023-05-07星期日的 22:35 +0100，Conor Dooley写道：
> > Hey Jisheng,
> > 
> > On Mon, May 08, 2023 at 02:23:02AM +0800, Jisheng Zhang wrote:
> > 
> > > +               c910_0: cpu@0 {
> > > +                       compatible = "thead,c910", "riscv";
> > > +                       device_type = "cpu";
> > > +                       riscv,isa = "rv64imafdc";
> > 
> > Does this support more than "rv64imafdc"?
> > I assume there's some _xtheadfoo extensions that it does support,
> > although I am not sure how we are proceeding with those - Heiko might
> > have a more nuanced take.

I guess the interesting question still is, are these part of the isa
string or more of an errata?

The binding currently says
      Identifies the specific RISC-V instruction set architecture
      supported by the hart.  These are documented in the RISC-V
      User-Level ISA document, available from
      https://riscv.org/specifications/


I guess if we decide to make them part of the isa-string the binding
then should get a paragraph mention _xfoo vendor-extensions too.

Personally, making these part of the ISA string definitly sounds like
the best solution though :-) .


> > > +               reset: reset-sample {
> > > +                       compatible = "thead,reset-sample";
> > 
> > What is a "reset-sample"?
> > 
> > > +                       entry-reg = <0xff 0xff019050>;
> > > +                       entry-cnt = <4>;
> > > +                       control-reg = <0xff 0xff015004>;
> > > +                       control-val = <0x1c>;
> > > +                       csr-copy = <0x7f3 0x7c0 0x7c1 0x7c2 0x7c3
> > > 0x7c5 0x7cc>;
> > > +               };
> > > +
> > > +               plic: interrupt-controller@ffd8000000 {
> > > +                       compatible = "thead,c910-plic";
> > > +                       reg = <0xff 0xd8000000 0x0 0x01000000>;
> > > +                       interrupts-extended = <&cpu0_intc 11>,
> > > <&cpu0_intc 9>,
> > > +                                             <&cpu1_intc 11>,
> > > <&cpu1_intc 9>,
> > > +                                             <&cpu2_intc 11>,
> > > <&cpu2_intc 9>,
> > > +                                             <&cpu3_intc 11>,
> > > <&cpu3_intc 9>;
> > > +                       interrupt-controller;
> > > +                       #interrupt-cells = <1>;
> > > +                       riscv,ndev = <240>;
> > > +               };
> > > +
> > > +               clint: timer@ffdc000000 {
> > > +                       compatible = "thead,c900-clint";
> > 
> > "c900"? That a typo or intentional. Hard to tell since this
> > compatible
> > is undocumented ;)
> 
> Intentional, for supporting both C906 and C910.
> 
> However, as we discussed in some binding patches, there should be a DT
> binding string per chip.
> 
> So here should be "thead,light-clint", "thead,c900-clint".
> 
> (Or use th1520, the marketing name, instead of light, the codename)

I'm definitly confused now :-)

c900 as well as something like c9xx should not be part of dt-bindings.
Binding-names should always denote _actual_ component names.

So you can do
	"thead,c906-clint"
and for example
	"thead,c910-clint", "thead,c906-clint"

to describe that the clint in the c910 is compatible with the one in c906


I don't think there should be a "thead,light-clint" ... the clint is part
of the cpu core itself so the soc itself shouldn't introduce any changes?


Heiko