From: Andrew Jeffery <andrew@codeconstruct.com.au>
To: Leo Wang <leo.jt.wang@gmail.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Kees Cook <kees@kernel.org>, Tony Luck <tony.luck@intel.com>,
"Guilherme G. Piccoli" <gpiccoli@igalia.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>
Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-aspeed@lists.ozlabs.org, linux-kernel@vger.kernel.org,
linux-hardening@vger.kernel.org,
linux-renesas-soc@vger.kernel.org,
bruce.jy.hung@fii-foxconn.com, george.kw.lee@fii-foxconn.com,
Leo Wang <leo.jt.wang@fii-foxconn.com>
Subject: Re: [PATCH 2/2] ARM: dts: aspeed: clemente: add Meta Clemente BMC
Date: Fri, 20 Jun 2025 16:09:11 +0930 [thread overview]
Message-ID: <751915792f5df84a4f8d4452ff08a784da3873e2.camel@codeconstruct.com.au> (raw)
In-Reply-To: <20250618-add-support-for-meta-clemente-bmc-v1-2-e5ca669ee47b@fii-foxconn.com>
Hi Leo,
On Wed, 2025-06-18 at 17:40 +0800, Leo Wang wrote:
> Add linux device tree entry for Meta Clemente compute-tray
> BMC using AST2600 SoC.
>
> Signed-off-by: Leo Wang <leo.jt.wang@fii-foxconn.com>
> ---
> arch/arm/boot/dts/aspeed/Makefile | 1 +
> .../dts/aspeed/aspeed-bmc-facebook-clemente.dts | 1254 ++++++++++++++++++++
> 2 files changed, 1255 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed/Makefile b/arch/arm/boot/dts/aspeed/Makefile
> index 2e5f4833a073b6c25190fd4b6e89a11f9636fc84..904503f78f960d7bc14cad7cb455bb8bb3138ccd 100644
> --- a/arch/arm/boot/dts/aspeed/Makefile
> +++ b/arch/arm/boot/dts/aspeed/Makefile
> @@ -19,6 +19,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
> aspeed-bmc-delta-ahe50dc.dtb \
> aspeed-bmc-facebook-bletchley.dtb \
> aspeed-bmc-facebook-catalina.dtb \
> + aspeed-bmc-facebook-clemente.dtb \
> aspeed-bmc-facebook-cmm.dtb \
> aspeed-bmc-facebook-elbert.dtb \
> aspeed-bmc-facebook-fuji.dtb \
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..ab5b37369d19a1e31fe74201fc5dc0011da2722f
> --- /dev/null
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-clemente.dts
> @@ -0,0 +1,1254 @@
>
*snip*
> + // Interposer
> + i2c-mux@70 {
> + compatible = "nxp,pca9548";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x70>;
> + i2c-mux-idle-disconnect;
> +
> + i2c1mux0ch0: i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x0>;
> + };
> + i2c1mux0ch1: i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x1>;
> + };
> + i2c1mux0ch2: i2c@2 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x2>;
> + };
> + i2c1mux0ch3: i2c@3 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x3>;
> + };
> + i2c1mux0ch4: i2c@4 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x4>;
> + };
> + i2c1mux0ch5: i2c@5 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x5>;
> +
> + // Interposer FRU EEPROM
> + eeprom@54 {
> + compatible = "atmel,24c64";
> + reg = <0x54>;
> + };
> +
> + // Interposer TEMP SENSOR
> + temperature-sensor@4f {
> + compatible = "ti,tmp75";
> + reg = <0x4f>;
> + };
The nodes up to here have been ordered nicely, but these two are
backwards :)
See:
https://docs.kernel.org/devicetree/bindings/dts-coding-style.html#order-of-nodes
> + };
> + i2c1mux0ch6: i2c@6 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x6>;
> +
> + // Interposer IOEXP
> + io_expander5: gpio@27 {
> + compatible = "nxp,pca9554";
> + reg = <0x27>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> + };
> + i2c1mux0ch7: i2c@7 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x7>;
> +
> + // FIO FRU EEPROM
> + eeprom@51 {
> + compatible = "atmel,24c64";
> + reg = <0x51>;
> + };
> +
> + // FIO TEMP SENSOR
> + temperature-sensor@4b {
> + compatible = "ti,tmp75";
> + reg = <0x4b>;
> + };
Again here.
> + };
> + };
> +};
> +
> +&i2c2 {
> + status = "okay";
> + // Module 0, Expander @0x20
> + io_expander0: gpio@20 {
> + compatible = "nxp,pca9555";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // Module 1, Expander @0x21
> + io_expander1: gpio@21 {
> + compatible = "nxp,pca9555";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // HMC Expander @0x27
> + io_expander2: gpio@27 {
> + compatible = "nxp,pca9555";
> + reg = <0x27>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // Module 0 Aux EEPROM
> + eeprom@50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + };
> +
> + // Module 1 Aux EEPROM
> + eeprom@51 {
> + compatible = "atmel,24c64";
> + reg = <0x51>;
> + };
> +};
> +
> +&i2c3 {
> + status = "okay";
> +};
> +
> +&i2c4 {
> + status = "okay";
> +};
> +
> +&i2c5 {
> + status = "okay";
> +};
> +
> +&i2c6 {
> + status = "okay";
> + rtc@6f {
> + compatible = "nuvoton,nct3018y";
> + reg = <0x6f>;
> + };
> +
> + io_expander3: gpio@21 {
> + compatible = "nxp,pca9555";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
Node ordering again.
> +};
> +
> +&i2c7 {
> + status = "okay";
> +};
> +
> +&i2c8 {
> + status = "okay";
> +};
> +
> +&i2c9 {
> + status = "okay";
> + // SCM CPLD IOEXP
> + io_expander4: gpio@4f {
> + compatible = "nxp,pca9555";
> + reg = <0x4f>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // SCM TEMP SENSOR BOARD
> + temperature-sensor@4b {
> + compatible = "national,lm75b";
> + reg = <0x4b>;
> + };
Node order
> +
> + // SCM FRU EEPROM
> + eeprom@50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + };
> +
> + // BSM FRU EEPROM
> + eeprom@56 {
> + compatible = "atmel,24c64";
> + reg = <0x56>;
> + };
> +};
> +
> +&i2c10 {
> + status = "okay";
> + // OCP NIC0 TEMP
> + temperature-sensor@1f {
> + compatible = "ti,tmp421";
> + reg = <0x1f>;
> + };
> +
> + // OCP NIC0 FRU EEPROM
> + eeprom@50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + };
> +};
> +
> +&i2c11 {
> + status = "okay";
> + ssif-bmc@10 {
> + compatible = "ssif-bmc";
> + reg = <0x10>;
> + };
> +};
> +
> +&i2c12 {
> + status = "okay";
> + multi-master;
> +};
> +
> +&i2c13 {
> + status = "okay";
> + multi-master;
> +
> + // HPM FRU EEPROM
> + eeprom@50 {
> + compatible = "atmel,24c64";
> + reg = <0x50>;
> + };
> + // CBC 0 FRU
> + eeprom@54 {
> + compatible = "atmel,24c02";
> + reg = <0x54>;
> + };
> + // CBC 1 FRU
> + eeprom@55 {
> + compatible = "atmel,24c02";
> + reg = <0x55>;
> + };
> + // CBC 2 FRU
> + eeprom@56 {
> + compatible = "atmel,24c02";
> + reg = <0x56>;
> + };
> + // CBC 3 FRU
> + eeprom@58 {
> + compatible = "atmel,24c02";
> + reg = <0x58>;
> + };
> + // HMC FRU EEPROM
> + eeprom@57 {
> + compatible = "atmel,24c02";
> + reg = <0x57>;
> + };
Hah, here too.
> +};
> +
> +&i2c14 {
> + status = "okay";
> +
> + // PDB CPLD IOEXP 0x10
> + io_expander9: gpio@10 {
> + compatible = "nxp,pca9555";
> + interrupt-parent = <&gpio0>;
> + interrupts = <ASPEED_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
> + reg = <0x10>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // PDB CPLD IOEXP 0x11
> + io_expander10: gpio@11 {
> + compatible = "nxp,pca9555";
> + interrupt-parent = <&gpio0>;
> + interrupts = <ASPEED_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
> + reg = <0x11>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // PDB CPLD IOEXP 0x12
> + io_expander11: gpio@12 {
> + compatible = "nxp,pca9555";
> + interrupt-parent = <&gpio0>;
> + interrupts = <ASPEED_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
> + reg = <0x12>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // PDB CPLD IOEXP 0x13
> + io_expander12: gpio@13 {
> + compatible = "nxp,pca9555";
> + interrupt-parent = <&gpio0>;
> + interrupts = <ASPEED_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
> + reg = <0x13>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + // PDB CPLD IOEXP 0x14
> + io_expander13: gpio@14 {
> + compatible = "nxp,pca9555";
> + reg = <0x14>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> +&i2c15 {
> + status = "okay";
> +
> + // OCP NIC1 TEMP
> + temperature-sensor@1f {
> + compatible = "ti,tmp421";
> + reg = <0x1f>;
> + };
> +
> + // OCP NIC1 FRU EEPROM
> + eeprom@52 {
> + compatible = "atmel,24c64";
> + reg = <0x52>;
> + };
> +};
> +
Can you order these top-level references alphabetically as per the dts
coding style (e.g. the i2c nodes above should be ordered (well) after
the adc nodes below)?
> +&adc0 {
> + vref-supply = <&p1v8_bmc_aux>;
> + status = "okay";
> +
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
> + &pinctrl_adc2_default &pinctrl_adc3_default
> + &pinctrl_adc4_default &pinctrl_adc5_default
> + &pinctrl_adc6_default &pinctrl_adc7_default>;
> +};
> +
*snip*
Andrew
next prev parent reply other threads:[~2025-06-20 6:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-18 9:40 [PATCH 0/2] ARM: dts: Add support for Meta Clemente BMC Leo Wang
2025-06-18 9:40 ` [PATCH 1/2] Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml Leo Wang
2025-06-20 6:25 ` Andrew Jeffery
2025-06-20 6:37 ` Krzysztof Kozlowski
2025-06-20 6:51 ` Geert Uytterhoeven
2025-06-18 9:40 ` [PATCH 2/2] ARM: dts: aspeed: clemente: add Meta Clemente BMC Leo Wang
2025-06-20 6:39 ` Andrew Jeffery [this message]
2025-06-18 13:36 ` [PATCH 0/2] ARM: dts: Add support for " Rob Herring (Arm)
[not found] <20250513031010.267994-1-LeoWang>
2025-05-13 3:10 ` [PATCH 2/2] ARM: dts: aspeed: clemente: add " leo.jt.wang
2025-05-13 7:44 ` Krzysztof Kozlowski
2025-05-13 12:38 ` Andrew Lunn
2025-05-14 13:11 ` Rob Herring (Arm)
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