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Thu, 06 Aug 2026 03:52:44 -0700 (PDT) X-Received: by 2002:a05:6a00:240d:b0:847:7a61:e68e with SMTP id d2e1a72fcca58-84f4febe965mr490026b3a.31.1786013563745; Thu, 06 Aug 2026 03:52:43 -0700 (PDT) Received: from [10.217.217.28] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84f45bc9b32sm1179448b3a.58.2026.08.06.03.52.36 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Aug 2026 03:52:43 -0700 (PDT) Message-ID: <752aaae3-10bf-4714-bfef-e075ce30604c@oss.qualcomm.com> Date: Thu, 6 Aug 2026 16:22:35 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/7] thermal: qcom: qcom-spmi-adc-tm5-gen3: Add support for QCOM PMIC5 Gen4 ADC To: Jonathan Cameron Cc: David Lechner , =?UTF-8?Q?Nuno_S=C3=A1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Bjorn Andersson , Konrad Dybcio , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, Kamal Wadhwa , Anjelique Melendez , Manaf Meethalavalappu Pallikunhi , Priyansh Jain References: <20260731-pmic5_gen4_adc-v1-0-9c49b2eea6f9@oss.qualcomm.com> <20260731-pmic5_gen4_adc-v1-3-9c49b2eea6f9@oss.qualcomm.com> <20260803011709.31cf83f2@jic23-huawei> Content-Language: en-US From: Jishnu Prakash In-Reply-To: <20260803011709.31cf83f2@jic23-huawei> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Info: AW1haW4tMjYwODA2MDA4NSBTYWx0ZWRfX6iX98oWV+jQk TorcZWi0gUrphRbpfeeQ0/AHaMr/Wn13nf4HWjm+vSQLbnPSpkPNbKBCeODwjjB2DGnhWw0r14A HS/pHob4Tr3yFGiBQ1LM3354oZtS2jk= X-Proofpoint-GUID: ZAxERBusA0_frKV0D57Flo8b0SoGbk2k X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODA2MDA4NSBTYWx0ZWRfX9ZvV7yWOWOZV YHgLXEPQjYA2fjONbuY3hmVoB6N6G31AZ2uAj+7FOip4arrxUztw0VIpfNFkpYlPPbBhNRXuGlf Y8bKMC7Lii1deTWaCegTHsQaLyB5h2hwyNQp74JCjLvz0d/mMRdDNMheM78uI4ZZ6d6h2J7nyrd osNy2/JVhE//zIUgXyz9nmEcVATutsDrPSKm5CghGJdTiCbLGkAJWIeM0nAZFZA6LvcShnsMlXR jGNHT/ymZH5mEqEb89QHs+KYKONn74AbANbMBLvlET2wXxkPb1e2Hc6ZWP4rTLlbKfSCgXwnBNu kFKmcfHqsRwiwLokV4Hj7YDHlM2bC5xFe/GNAn2M0EuKdRjihhzqNrZf58+AFFkUzdqq20Fw7wg 59mE8oSl8miDmafq6NsqXKiilWnN429N4D0xVS9MwnPdLnQBsbWrQqMAxkJV0ImVpQRHQAe1aOy ustfAKjiUmvzEqHnh4w== X-Authority-Analysis: v=2.4 cv=Mo1iLWae c=1 sm=1 tr=0 ts=6a74677d cx=c_pps a=WW5sKcV1LcKqjgzy2JUPuA==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=VLISa07izfuZ2-VxH8gA:9 a=QEXdDO2ut3YA:10 a=OpyuDcXvxspvyRM73sMx:22 X-Proofpoint-ORIG-GUID: ZAxERBusA0_frKV0D57Flo8b0SoGbk2k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-05_06,2026-08-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 adultscore=0 malwarescore=0 bulkscore=0 clxscore=1015 suspectscore=0 spamscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608060085 Hi Jonathan, On 8/3/2026 5:47 AM, Jonathan Cameron wrote: > On Fri, 31 Jul 2026 23:36:16 +0530 > Jishnu Prakash wrote: > >> PMIC5 Gen4 ADC is similar to PMIC5 Gen3 ADC, with several changes made >> for improved performance, mostly at the hardware level. >> >> One significant software change is that ratiometric conversion resolution >> has been increased from 14 bits to 16 bits. Add a reverse scaling function >> for Gen4 ADC thermistor channels. >> >> In the latest PMIC arbiter version (v8), there can be up to 4 buses >> under the PMIC arbiter and 32 PMICs under each bus. In order to >> support communication between ADC on the master PMIC and ADCs on any >> of the other PMICs, a field of width 2 bits is added for bus index >> and the bits for SID are extended from 4 to 5 bits, in the SID >> register. Add support for this. >> >> Co-developed-by: Anjelique Melendez >> Signed-off-by: Anjelique Melendez >> Signed-off-by: Jishnu Prakash > Hi Jishnu, Anjelique > > Code looks fine, but I just wanted to check. What happens if > for some reason the patch before ends up in a tree and this one doesn't > Do we read the wrong temperatures given 'bus' isn't specified? > Actually from what I see, patches 2 and 3 need to go in together, else there would be a compilation error in one driver. This is because patch 2 replaces two macros, which are used in both the IIO and thermal drivers: ADC5_GEN3_SID_MASK -> ADC5_GEN4_SID_MASK ADC5_GEN3_V_CHAN -> ADC5_GEN4_V_CHAN It looks like I missed checking for bisectability, sorry about that. To avoid this, I'll add the new macros in patch 2 and remove the old ones in a separate new patch after patch 3. To answer your question once bisectability is fixed: The changes in this TM file affect the flow in the .set_trips() call, which is used for setting high/low temperature thresholds. The .get_temp() is not affected, as it directly calls into the main ADC driver using the exported function adc5_gen3_get_scaled_reading(). For the specific situation you mentioned - temperature reading for Gen4 channels using get_temp() would work correctly with patch 2 in place, but setting high/low thresholds would go wrong for all Gen4 channels as the conversion formula is different. Bus index not being specified would also cause errors for configuring channels on bus numbers other than 0. Thanks, Jishnu > Jonathan >