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[82.131.98.15]) by smtp.gmail.com with ESMTPSA id i4-20020a198c44000000b00492c5ec6f84sm970215lfj.249.2022.08.28.08.14.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 28 Aug 2022 08:14:48 -0700 (PDT) Message-ID: <755e203f-d02c-16ca-254a-f9b1d751f1f5@linaro.org> Date: Sun, 28 Aug 2022 18:14:46 +0300 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [PATCH 09/11] dt-bindings: PCI: qcom-ep: Define clocks per platform Content-Language: en-US To: Manivannan Sadhasivam , lpieralisi@kernel.org, robh@kernel.org, andersson@kernel.org Cc: kw@linux.com, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, dmitry.baryshkov@linaro.org References: <20220826181923.251564-1-manivannan.sadhasivam@linaro.org> <20220826181923.251564-10-manivannan.sadhasivam@linaro.org> From: Krzysztof Kozlowski In-Reply-To: <20220826181923.251564-10-manivannan.sadhasivam@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 26/08/2022 21:19, Manivannan Sadhasivam wrote: > In preparation of adding the bindings for future SoCs, let's define the > clocks per platform. > > Signed-off-by: Manivannan Sadhasivam > --- > .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 46 +++++++++++-------- > 1 file changed, 27 insertions(+), 19 deletions(-) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > index b728ede3f09f..83a2cfc63bc1 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > @@ -9,9 +9,6 @@ title: Qualcomm PCIe Endpoint Controller binding > maintainers: > - Manivannan Sadhasivam > > -allOf: > - - $ref: "pci-ep.yaml#" > - > properties: > compatible: > const: qcom,sdx55-pcie-ep > @@ -35,24 +32,12 @@ properties: > - const: mmio > > clocks: > - items: > - - description: PCIe Auxiliary clock > - - description: PCIe CFG AHB clock > - - description: PCIe Master AXI clock > - - description: PCIe Slave AXI clock > - - description: PCIe Slave Q2A AXI clock > - - description: PCIe Sleep clock > - - description: PCIe Reference clock > + minItems: 7 MinItems is not needed. They should be added in your next patch. > + maxItems: 7 > > clock-names: > - items: > - - const: aux > - - const: cfg > - - const: bus_master > - - const: bus_slave > - - const: slave_q2a > - - const: sleep > - - const: ref > + minItems: 7 MinItems is not needed. They should be added in your next patch. > + maxItems: 7 > > qcom,perst-regs: > description: Reference to a syscon representing TCSR followed by the two > @@ -112,6 +97,29 @@ required: > - reset-names > - power-domains > > +allOf: > + - $ref: "pci-ep.yaml#" While moving this line around, drop the quotes. > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,sdx55-pcie-ep > + then: > + properties: > + clocks: > + minItems: 7 minItems is not needed > + maxItems: 7 Best regards, Krzysztof