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[78.88.45.245]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-aec6c7c77c0sm1045393666b.35.2025.07.23.06.09.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 23 Jul 2025 06:09:31 -0700 (PDT) Message-ID: <75a1935a-b6c1-4339-8b4d-12af9ead51e6@oss.qualcomm.com> Date: Wed, 23 Jul 2025 15:09:29 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/4] clk: qcom: apss-ipq5424: Add ipq5424 apss clock controller To: Varadarajan Narayanan , andersson@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, ilia.lin@kernel.org, djakov@kernel.org, quic_srichara@quicinc.com, quic_mdalam@quicinc.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org References: <20250723110815.2865403-1-quic_varada@quicinc.com> <20250723110815.2865403-3-quic_varada@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20250723110815.2865403-3-quic_varada@quicinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=G8UcE8k5 c=1 sm=1 tr=0 ts=6880df0e cx=c_pps a=HLyN3IcIa5EE8TELMZ618Q==:117 a=FpWmc02/iXfjRdCD7H54yg==:17 a=IkcTkHD0fZMA:10 a=Wb1JkmetP80A:10 a=COk6AnOGAAAA:8 a=osBE9IlwIbL1kcFus-gA:9 a=QEXdDO2ut3YA:10 a=bTQJ7kPSJx9SKPbeHEYW:22 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNzIzMDExMiBTYWx0ZWRfX9wbypKtHEqWj DqwNA87iTobLG7HEAHtCVjTJxO3ozBfYlfutN67cLKlaQdK2hYsCrT7YLr6a4Gk8Je4tI6P+kzn 3i/MFTGvgWJSiWjSG5Vf2vblIqsUXGY+6nw6gLwk+/aelQxSiwGQcfOayH/XCjjJasELyTvZBeC hFjOskCe9XhCjP9q7WhgObiu4CU/ALlIpTm38Hnp8OyLfqtkC3eK1ipkUEqihp7O3iptGlZf1Ff pLr/ITzEX3+vlGGzBjHSFaxJEuTz6zSdn01oiyvmzDobPctrvavd4gjeQfG657OE//CoXNHpy7Y 6GkDtFPRQ0XIMx0JpttZo8sCenpP1ir0LVJKXrb9luYcccNYFy9DPYLW1D9/MAYmIrR3jJL1dJ+ KBj5ifl8WfKu0Q0Yjcchp2ZWadVnV2HTx2mN0AMb4yCUzoyClnav8o5tV49/VywPBBWktfwu X-Proofpoint-GUID: 8sUw1yQJOSmAf-g15NDfBjIXufVFN1zN X-Proofpoint-ORIG-GUID: 8sUw1yQJOSmAf-g15NDfBjIXufVFN1zN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-07-23_02,2025-07-22_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 mlxscore=0 suspectscore=0 priorityscore=1501 clxscore=1015 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505280000 definitions=main-2507230112 On 7/23/25 1:08 PM, Varadarajan Narayanan wrote: > From: Sricharan Ramabadhran > > CPU on Qualcomm ipq5424 is clocked by huayra PLL with RCG support. > Add support for the APSS PLL, RCG and clock enable for ipq5424. > The PLL, RCG register space are clubbed. Hence adding new APSS driver > for both PLL and RCG/CBC control. Also the L3 cache has a separate pll > and needs to be scaled along with the CPU and is modeled as an ICC clock. > > Co-developed-by: Md Sadre Alam > Signed-off-by: Md Sadre Alam > Signed-off-by: Sricharan Ramabadhran > [ Removed clock notifier, moved L3 pll to icc-clk, used existing > alpha pll structure ] > Signed-off-by: Varadarajan Narayanan > --- > v2: Model L3 pll as ICC clock and add relevant structures > Use CLK_ALPHA_PLL_TYPE_HUAYRA_2290 register offsets instead > of duplicate ipq5424_pll_offsets definition. > Inline clock rates. > Fix MODULE_LICENSE > --- [...] Since the last time this was posted, we got some additional infra code.. > +static int apss_ipq5424_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct regmap *regmap; > + void __iomem *base; > + int ret; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + regmap = devm_regmap_init_mmio(dev, base, &apss_ipq5424_regmap_config); > + if (!regmap) > + return PTR_ERR(regmap); > + > + clk_alpha_pll_configure(&ipq5424_l3_pll, regmap, &l3_pll_config); > + > + clk_alpha_pll_configure(&ipq5424_apss_pll, regmap, &apss_pll_config); > + > + ret = qcom_cc_really_probe(dev, &apss_ipq5424_desc, regmap); > + if (!ret) > + dev_dbg(&pdev->dev, "Registered APSS & L3 clock provider\n"); > + > + return ret; You can now replace the entirety of this function with qcom_cc_driver_data Konrad