From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christo Radev Subject: Re: [PATCH 1/1] ARM: dts: sunxi: Add a olinuxino-lime2-emmc Date: Wed, 4 May 2016 10:24:42 -0700 (PDT) Message-ID: <75debca7-554e-4e15-9675-73a9bc92cc6f@googlegroups.com> References: <1461827998-12192-1-git-send-email-oliver@schinagl.nl> <57285162.2000704@schinagl.nl> <5729F07C.3080308@schinagl.nl> <948be370-4401-43cb-862e-d4376755a75d@googlegroups.com> <5729F6D6.8030100@schinagl.nl> <4704fa35-9a2a-4e6e-8fd4-f4778405c598@googlegroups.com> <572A0052.9060202@schinagl.nl> <2e745ef7-ddc0-40fc-b867-414543690276@googlegroups.com> <572A10B3.2020803@schinagl.nl> Reply-To: christo.radev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_4177_881679067.1462382682466" Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <572A10B3.2020803-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org> List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: linux-sunxi Cc: christo.radev-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, radoslav.kolev-1W28NRE8jL9DPfheJLI6IQ@public.gmane.org, wens-jdAy2FN1RRM@public.gmane.org, maxime.ripard-wi1+55ScJUtKEb57/3fJTNBPR1lH4CV8@public.gmane.org, tsvetan-kyXcfZUBQGPQT0dZR+AlfA@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org, pawel.moll-5wv7dgnIgG8@public.gmane.org, mark.rutland-5wv7dgnIgG8@public.gmane.org, ijc+devicetree-KcIKpvwj1kUDXYZnReoRVg@public.gmane.org, galak-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org, hdegoede-H+wXaHxf7aLQT0dZR+AlfA@public.gmane.org, dev-3kdeTeqwOZ9EV1b7eY7vFQ@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, oliver-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org List-Id: devicetree@vger.kernel.org ------=_Part_4177_881679067.1462382682466 Content-Type: multipart/alternative; boundary="----=_Part_4178_839273576.1462382682470" ------=_Part_4178_839273576.1462382682470 Content-Type: text/plain; charset=UTF-8 Hi Oliver, I have just tested your patch and the access to eMMC is working. There you are complete patch I have applied against kernel 4.5.2: index d5c796c..1f5339d 100644 --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts +++ b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts @@ -188,6 +188,15 @@ status = "okay"; }; +&mmc2 { + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins_a>; + vmmc-supply = <®_vcc3v3>; + bus-width = <8>; + non-removable; + status = "okay"; +}; + &ohci0 { status = "okay"; }; diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c index 3d5087b..78668aa 100644 --- a/drivers/mmc/core/mmc.c +++ b/drivers/mmc/core/mmc.c @@ -504,7 +504,7 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd) pr_info("%s: MAN_BKOPS_EN bit is not set\n", mmc_hostname(card->host)); } - +#if 0 /* check whether the eMMC card supports HPI */ if (!broken_hpi && (ext_csd[EXT_CSD_HPI_FEATURES] & 0x1)) { card->ext_csd.hpi = 1; @@ -519,7 +519,7 @@ static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd) card->ext_csd.out_of_int_time = ext_csd[EXT_CSD_OUT_OF_INTERRUPT_TIME] * 10; } - +#endif card->ext_csd.rel_param = ext_csd[EXT_CSD_WR_REL_PARAM]; card->ext_csd.rst_n_function = ext_csd[EXT_CSD_RST_N_FUNCTION]; diff --git a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c b/drivers/pinctrl/ sunxi/pinctrl-sun7i-a20.c index cf1ce0c..9fc12d2 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c +++ b/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c @@ -314,19 +314,23 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = { SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */ SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 16), SUNXI_FUNCTION(0x0, "gpio_in"), SUNXI_FUNCTION(0x1, "gpio_out"), And the boot messages: [ 3.598495] sunxi-mmc 1c0f000.mmc: Got CD GPIO [ 3.631826] sunxi-mmc 1c0f000.mmc: base:0xf08da000 irq:26 [ 3.668943] mmc0: host does not support reading read-only switch, assuming write-enable [ 3.671887] sunxi-mmc 1c11000.mmc: base:0xf08de000 irq:27 [ 3.671935] mmc0: new high speed SDHC card at address 0007 [ 3.672939] mmcblk0: mmc0:0007 SD04G 3.71 GiB [ 3.674799] mmcblk0: p1 [ 3.682634] sunxi-mmc 1c11000.mmc: smc 1 err, cmd 8, RTO !! [ 3.687921] sunxi-mmc 1c11000.mmc: smc 1 err, cmd 55, RTO !! [ 3.688785] sunxi-mmc 1c11000.mmc: smc 1 err, cmd 55, RTO !! [ 3.689643] sunxi-mmc 1c11000.mmc: smc 1 err, cmd 55, RTO !! [ 3.690477] sunxi-mmc 1c11000.mmc: smc 1 err, cmd 55, RTO !! [ 3.725492] mmc1: MAN_BKOPS_EN bit is not set [ 3.729187] sunxi-mmc 1c11000.mmc: smc 1 err, cmd 8, RD EBE !! [ 3.729228] sunxi-mmc 1c11000.mmc: data error, sending stop command [ 3.729247] sunxi-mmc 1c11000.mmc: send stop command failed [ 3.729270] mmc1: switch to bus width 2 failed [ 3.733592] mmc1: new high speed MMC card at address 0001 [ 3.734478] mmcblk1: mmc1:0001 P1XXXX 3.60 GiB [ 3.734889] mmcblk1boot0: mmc1:0001 P1XXXX partition 1 16.0 MiB [ 3.735305] mmcblk1boot1: mmc1:0001 P1XXXX partition 2 16.0 MiB [ 3.736551] mmcblk1: p1 [ 4.155620] EXT4-fs (mmcblk0p1): mounted filesystem with writeback data mode. Opts: (null) [ 8.163191] EXT4-fs (mmcblk0p1): re-mounted. Opts: commit=600,errors= remount-ro where mmc0 is SD/MMC card and mmc1 is eMMC on my A20-Olinuxino-Lime2-eMMC board. Fortunately or not the same error and fail messages can be observed in my board log. How can I verify how wide is the eMMC bus used in real? Best regards Chris On Wednesday, May 4, 2016 at 6:09:44 PM UTC+3, Olliver Schinagl wrote: > > Christo, > > On 04-05-16 16:31, Christo Radev wrote: > > Tanks Oliver, > > It could be the problem to get 8-bit access working. > > Unfortunately, I do not see where to make this changes because original > dts files > > are used in Armbian build. > I also see '*SUNXI_PINCTRL_PIN*' and '*SUNXI_FUNCTION*' may require some > patches in addition. > > check out drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c > > my patch should still work aginst that. > > > I am ready to make 8-bit eMMC access tests again so could you help me with > the needed staff it has to be used. > > I don't mind, but lets take it off list for that :) > > Olliver > > > Best regards > Chris > > On Wednesday, May 4, 2016 at 4:59:52 PM UTC+3, Olliver Schinagl wrote: >> >> Hey Christo, >> >> On 04-05-16 15:32, Christo Radev wrote: >> >> Hi Oliver, >> >> I do: that >> http://forum.armbian.com/index.php/topic/853-armbian-customization/page-2#entry7359 >> The syntax error seen there was fixed and the result is: >> http://forum.armbian.com/index.php/topic/853-armbian-customization/page-2#entry7361 >> >> Nope, you are still forgetting and seeing an 'unsupported function' error >> because of it. >> >> You forgot to add: >> >> >>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12), >> *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), >> *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), >> *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ4 */ >> *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ4 */ >> *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D4 */ >> *>>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13), >> *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), >> *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), >> *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ5 */ >> *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ5 */ >> *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D5 */ >> *>>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14), >> *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), >> *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), >> *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ6 */ >> *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ6 */ >> *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D6 */ >> *>>>* SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15), >> *>>>* SUNXI_FUNCTION(0x0, "gpio_in"), >> *>>>* SUNXI_FUNCTION(0x1, "gpio_out"), >> *>>>* - SUNXI_FUNCTION(0x2, "nand0")), /* NDQ7 */ >> *>>>* + SUNXI_FUNCTION(0x2, "nand0"), /* NDQ7 */ >> *>>>* + SUNXI_FUNCTION(0x3, "mmc2")), /* D7 */* >> >> >> to actually get the pin functions. >> >> >> The same tests was done on legacy kernel 3.4.111 modifying fex file and >> the result is the same: >> http://forum.armbian.com/index.php/topic/853-armbian-customization/page-2#entry7265 >> >> >> Best regards >> Chris >> >> >> On Wednesday, May 4, 2016 at 4:19:20 PM UTC+3, Olliver Schinagl wrote: >>> >>> Hey Christo, >>> >>> On 04-05-16 15:07, Christo Radev wrote: >>> >>> Hi Olliver, >>> >>> I have already test it a few weeks ago and definitely can say that 8-bit >>> bus did not work on A20-Olinuxino-Lime2-eMMC with mainline kernel. >>> See may post here >>> >>> . >>> >>> I saw, but you forgot to define the pins for 4.x :) >>> >>> See my patch from earlier: >>> >>> http://lists.infradead.org/ >>> pipermail/linux-arm-kernel/2015-September/368887.html >>> >>> Olliver >>> >>> >>> Best regards >>> >>> Chris >>> >>> On Wednesday, May 4, 2016 at 3:52:17 PM UTC+3, Olliver Schinagl wrote: >>>> >>>> Hey Radoslav, >>>> >>>> On 04-05-16 14:30, Radoslav Kolev wrote: >>>> > 2016-05-03 10:25 GMT+03:00 Chen-Yu Tsai : >>>> >> On Tue, May 3, 2016 at 3:21 PM, Olliver Schinagl >>>> wrote: >>>> >>>>> + bus-width = <4>; >>>> >>>> Only 4 bits? We normally see eMMC with 8 bits. 4 bits are some >>>> kind of >>>> >>>> embedded SD card. >>>> >>> On A20 as well? Our investigations so far have concluded that the >>>> A10 and >>>> >>> A20 have those pins not mapped out to pads. The IP does support it >>>> however >>>> >>> we assume. >>>> >> You're right. My bad. First time A10/A20 sees eMMC support. >>>> > I can't say anything about A10/A20, but I have a board with A13 and >>>> > the same eMMC chip and it works fine in 8 bit mode. >>>> Yep, sun5i actually brings them all out to pads, the A20 however does >>>> not :( We first thought that the A20 would also be an 8bitter, because >>>> the mmc IP appears to be the same as sun5i, but initial tests show it >>>> is >>>> not. As for A10, it has older IP and it might not even support 8 bit >>>> mode, let alone bring out the pins. >>>> >>>> But with A20's + eMMC being available via the lime2, others may repeat >>>> my experiments! The lime2 is 8 bit connected. >>>> >>>> Olliver >>>> > >>>> > Regards, >>>> > Radoslav >>>> >>>> >>> >> > -- You received this message because you are subscribed to the Google Groups "linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. ------=_Part_4178_839273576.1462382682470 Content-Type: text/html; charset=UTF-8 Content-Transfer-Encoding: quoted-printable
Hi Oliver,

I have just tested your patch and the ac= cess to eMMC is working.
There you are complete patch I have applied aga= inst kernel 4.5.2:
index d5c796c..1f5339d 100644<= /span>
= --- a/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
= +++= b/arch/arm/boot/dts/sun7i-a20-olinuxino-lime2.dts
@@= -188,6 +188,= 15<= span style=3D"color: #000;" class=3D"styled-by-prettify"> @@
=C2=A0 =C2=A0 =C2=A0status =3D "okay";
=C2=A0};
=C2=A0
+&mmc2 {
+ =C2=A0 =C2=A0pinctrl-names =3D= "def= ault"= ;
+ =C2=A0 =C2=A0pinctrl-0 =3D <&mmc2_pins_a>;
+ = =C2=A0 =C2=A0vmmc-su= pply =3D <&reg_vcc3v3>;
+ =C2=A0 =C2=A0bus-width =3D <8>= ;
+ =C2=A0 =C2=A0non= -removable;
+ =C2=A0 =C2=A0status =3D "okay";
+};
+
=C2=A0&= ohci0 {
=C2=A0 =C2=A0 =C2=A0stat= us =3D "okay"= ;
=C2=A0};
diff --git a/drivers/mmc/= core/mmc.c b/drivers/mmc/= core/mmc.c
index 3d5087b..78668aa 100644
--- a/drivers/mmc/core/mmc.c
<= /span>+++<= span style=3D"color: #000;" class=3D"styled-by-prettify"> b/drivers/mmc/core/mmc= .c
@@ -504,7= +<= span style=3D"color: #066;" class=3D"styled-by-prettify">504,7 @@ static int mmc_decode_e= xt_csd(struct= mmc_card = *card, u8 *ext_csd)
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0pr= _info("%s: MAN_= BKOPS_EN bit is not set\n",
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0 =C2=A0mmc_hostname(card->h= ost));
=C2=A0 =C2= =A0 =C2=A0 =C2=A0 =C2=A0}
-=
+#if 0
=C2=A0 =C2=A0 =C2=A0 =C2= =A0 =C2=A0= /* check whether the eMMC card supports HPI */
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0<= /span>if (!broken_hpi && (ext_csd[EXT_CSD_HPI_FEATURES] & 0x1)) {
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 = =C2=A0 =C2=A0card->ext_csd.= hpi =3D 1;
@@ -519,7 +519,7= @@= static int mmc_decode_ext_csd(struct mmc_card *card, u8 *ext_csd)
=C2=A0 =C2=A0 =C2=A0= =C2=A0 =C2=A0 =C2=A0 =C2=A0card->ext_csd.out_of_int_time =3D
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0ext= _csd[EXT_CSD_OUT_OF_= INTERRUPT_TIME] * 10;
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0}
-
+#endif
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0card->ext_csd.rel_param =3D ext_csd[EXT_CSD_WR_REL_PARAM];
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0card->ext_csd.rst_n_function =3D ext_csd[EXT_CSD_RST_N_FUNCTION];
=C2=A0
diff --git a/drivers/p= inctrl/sunxi<= span style=3D"color: #660;" class=3D"styled-by-prettify">/pinctrl-sun7i-a20.c b/drivers<= /span>/pinctrl/sunxi/pinctrl-sun7i-a20.c
index cf= 1ce0c..9fc12d2 100644
--- a/drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
+++= b/= drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c
@@ -314,19= +<= span style=3D"color: #066;" class=3D"styled-by-prettify">314,23 @@ static const<= /span> struct sunxi_desc_pin sun7i_a2= 0_pins[] =3D {
=C2=A0 =C2=A0 =C2=A0SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12),<= br>=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION(0x0, "gpio_in"),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION= (0x1, "gpio_out"),
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION<= span style=3D"color: #660;" class=3D"styled-by-prettify">(0x2, "nand0")), =C2=A0 =C2=A0/* NDQ4 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION(0x2, "nand0"), =C2=A0 =C2=A0 =C2=A0 =C2=A0/* NDQ4 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTIO= N(<= span style=3D"color: #066;" class=3D"styled-by-prettify">0x3, "mmc2")), =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* D4 */
=C2=A0 =C2=A0 =C2=A0SUN= XI_PIN(SUNXI_PINCTRL= _PIN(C, 13),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTIO= N(<= span style=3D"color: #066;" class=3D"styled-by-prettify">0x0, "gpio_in"),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0SUNXI_FUNCTION(0x= 1,<= span style=3D"color: #000;" class=3D"styled-by-prettify"> "gpio_out"= ),
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI= _FUNCTION(= 0x2= , "nand0")), =C2=A0 =C2=A0/* NDQ5 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCT= ION(0x2, "nand0"), =C2=A0 =C2=A0/* NDQ5 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION(0x3, "mmc2")), =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* D5 */
=C2=A0 =C2=A0 =C2=A0SUNX= I_PIN(SUNXI_PINCTRL_= PIN(C, 14),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION= (0x0, "gpio_in"),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0SUNXI_FUNCTION(0x= 1,<= span style=3D"color: #000;" class=3D"styled-by-prettify"> "gpio_out"= ),
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI= _FUNCTION(= 0x2= , "nand0")), =C2=A0 =C2=A0/* NDQ6 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCT= ION(0x2, "nand0"), =C2=A0 =C2=A0/* NDQ6 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION(0x3, "mmc2")), =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* D6 */
=C2=A0 =C2=A0 =C2=A0SUNX= I_PIN(SUNXI_PINCTRL_= PIN(C, 15),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION= (0x0, "gpio_in"),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0SUNXI_FUNCTION(0x= 1,<= span style=3D"color: #000;" class=3D"styled-by-prettify"> "gpio_out"= ),
- =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI= _FUNCTION(= 0x2= , "nand0")), =C2=A0 =C2=A0/* NDQ7 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCT= ION(0x2, "nand0"), =C2=A0 =C2=A0/* NDQ7 */
+ =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION(0x3, "mmc2")), =C2=A0 =C2=A0 =C2=A0 =C2=A0 /* D7 */
=C2=A0 =C2=A0 =C2=A0SUNX= I_PIN(SUNXI_PINCTRL_= PIN(C, 16),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0SUNXI_FUNCTION= (0x0, "gpio_in"),
=C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2=A0 =C2= =A0SUNXI_FUNCTION(0x= 1,<= span style=3D"color: #000;" class=3D"styled-by-prettify"> "gpio_out"= ),
<= /div>
And the boot messages:
[ =C2=A0 =C2=A03.598495] sunxi-mmc <= /span>1c0f000.mmc= : Got CD GPIO
[ =C2=A0 =C2=A03.631826] sunxi-mmc 1c0f000.mmc: base:0xf08da000 irq:26
[ =C2=A0 =C2=A03.668943] mmc0: host = does not support rea= ding read-= only switch, assuming write-enable
[ =C2=A0 =C2=A03.671887] sunxi-mmc 1c11000.mmc: base:0xf08de000 irq:27
[ =C2=A0 =C2=A03.671935] mmc0: new high speed SDHC card = at address 0007
<= /span>[ =C2=A0 =C2=A03.672939<= span style=3D"color: #660;" class=3D"styled-by-prettify">] mmcblk0: mmc0:0007 SD04G 3.71 = GiB
[ =C2=A0 =C2=A0<= span style=3D"color: #066;" class=3D"styled-by-prettify">3.674799] =C2=A0mmcblk0: p1
[ =C2=A0 =C2=A03.682634] sunxi-mmc 1c11000.mmc: sm= c 1= err, cmd 8, RTO !!
[ =C2=A0 = =C2=A03.68= 7921] sunxi-mmc 1c11000.mmc: smc 1 err, cmd 5= 5,<= span style=3D"color: #000;" class=3D"styled-by-prettify"> RTO !!
[ =C2=A0 =C2=A03.688785] sunxi-mmc 1c11000.mmc: sm= c 1= err, cmd 55, RTO !!
[ =C2=A0= =C2=A03.6= 89643] sunxi<= span style=3D"color: #660;" class=3D"styled-by-prettify">-mmc 1c11000.mmc: smc 1 err, cmd = 55,= RTO !!
[ =C2=A0 =C2=A03.690477] sunxi-mmc 1c11000.mmc: s= mc 1 err, cmd 55, RTO !!
[ =C2= =A0 =C2=A0= 3.725492]<= /span> mmc1: MAN_BKOPS_EN bit = is not set
[ =C2=A0 =C2=A03.729187] sun= xi-= mmc 1c11000.mmc: smc 1 err, cmd 8, RD EBE = !!<= span style=3D"color: #000;" class=3D"styled-by-prettify">
[ =C2=A0 =C2=A03.729228] sunxi-mmc 1c11000.mmc: data error, sending stop command
[ =C2=A0 =C2=A03.729247] sunxi-<= /span>mmc = 1c11000.mmc: send stop command failed=
[ =C2=A0 =C2=A0<= /span>3.729270] mmc1: switch to bus width 2 failed
[ =C2=A0 =C2=A03.733592] mmc1: new high speed MMC card a= t address = 0001
[ =C2=A0 =C2=A0= 3.734478] mmcblk1: mmc1:0001 P1XXXX 3.60 GiB
[ =C2=A0 =C2=A0= 3.734889] mmcblk1boot0: mmc1:0001 P1XXXX partition 1 16.0 MiB<= /span>
= [ =C2=A0 =C2=A03.735305] mmcblk1boot1: mmc1:0001 P1XXXX partition 2 16.0 MiB
[ =C2=A0 =C2=A03.736551] =C2=A0mmcblk1: p1
[ =C2=A0 =C2=A04.155620] EXT4-fs (mmcblk0p1): mounted filesystem with<= span style=3D"color: #000;" class=3D"styled-by-prettify"> writeback data mo= de.= Opts: (null)
[ =C2=A0 =C2=A0= 8.163191] EXT4-fs (mmcblk0p1): re-= mounted. Opts: commit=3D600,errors=3Dremount-ro
where mmc0 is SD/MMC card and mmc1 is eMMC on my A2= 0-Olinuxino-Lime2-eMMC board.

Fortunately or not the same error and = fail messages can be observed in my board log.

How can I verify how = wide is the eMMC bus used in real?

Best regards
Chris


= On Wednesday, May 4, 2016 at 6:09:44 PM UTC+3, Olliver Schinagl wrote: =20 =20 =20
Christo,

On 04-05-16 16:31, Christo Radev wrote:
Tanks Oliver,

It could be the problem to get 8-bit access working.

Unfortunately, I do not see where to make this changes because original dts files are used in Armbian build.
I also see 'SUNXI_PINCTRL_PIN' and 'SUNXI_FUN= CTION' may require some patches in addition.
check out drivers/pinctrl/sunxi/pinctrl-sun7i-a20.c

my patch should still work aginst that.

I am ready to make 8-bit eMMC access tests again so could you help me with the needed staff it has to be used.
I don't mind, but lets take it off list for that :)

Olliver

Best regards
Chris

On Wednesday, May 4, 2016 at 4:59:52 PM UTC+3, Olliver Schinagl wrote:
Hey Christo,

On 04-05-16 15:32, Christo Radev wrote:
Nope, you are still forgetting and seeing an 'unsupported function' error because of it.

You forgot to add:

>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 12=
),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ4 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ4 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D4 */
>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 13),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ5 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ5 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D5 */
>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 14),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ6 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ6 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D6 */
>>>          SUNXI_PIN(SUNXI_PINCTRL_PIN(C, 15),
>>>                    SUNXI_FUNCTION(0x0, "gpio_in&qu=
ot;),
>>>                    SUNXI_FUNCTION(0x1, "gpio_out&q=
uot;),
>>> -                 SUNXI_FUNCTION(0x2, "nand0"=
)),        /* NDQ7 */
>>> +                 SUNXI_FUNCTION(0x2, "nand0"=
),         /* NDQ7 */
>>> +                 SUNXI_FUNCTION(0x3, "mmc2")=
),         /* D7 */

to actually get the pin functions.

The same tests was done on legacy kernel 3.4.111 modifying fex file and the result is the same: http://forum.armbian.com/= index.php/topic/853-armbian-customization/page-2#entry7265


Best regards
Chris


On Wednesday, May 4, 2016 at 4:19:20 PM UTC+3, Olliver Schinagl wrote:
Hey Christo,
On 04-05-16 15:07, Christo Radev wrote:
Hi Olliver,

I have already test it a few weeks ago and definitely can say that 8-bit bus did not work on A20-Olinuxino-Lime2-eMMC with mainline kernel.
See may post here.=
I saw, but you forgot to define the pins for 4.x :)

See my patch from earlier: http://lists= .infradead.org/pipermail/linux-arm-kernel/2015-September/3688= 87.html

Olliver


Best regards

Chris

On Wednesday, May 4, 2016 at 3:52:17 PM UTC+3, Olliver Schinagl wrote:
Hey Radosla= v,

On 04-05-16 14:30, Radoslav Kolev wrote:
> 2016-05-03 10:25 GMT+03:00 Chen-Yu Tsai <we...-jdAy2FN1RRM@public.gmane.org>:
>> On Tue, May 3, 2016 at 3:21 PM, Olliver Schinagl <oli...-dxLnbx3+1qmEVqv0pETR8A@public.gmane.org>= ; wrote:
>>>>> + =C2=A0 =C2=A0 =C2=A0 bus-w= idth =3D <4>;
>>>> Only 4 bits? We normally see eMMC with 8 bits. 4 bits are some kind of
>>>> embedded SD card.
>>> On A20 as well? Our investigations so far have concluded that the A10 and
>>> A20 have those pins not mapped out to pads. The IP does support it however
>>> we assume.
>> You're right. My bad. First time A10/A20 sees eMMC support.
> I can't say anything about A10/A20, but = I have a board with A13 and
> the same eMMC chip and it works fine in 8 bit mode.
Yep, sun5i actually brings them all out to pads, the A20 however does
not :( We first thought that the A20 would also be an 8bitter, because
the mmc IP appears to be the same as sun5i, but initial tests show it is
not. As for A10, it has older IP and it might not even support 8 bit
mode, let alone bring out the pins.

But with A20's + eMMC being available via the lime2, others may repeat
my experiments! The lime2 is 8 bit connected.

Olliver
>
> Regards,
> Radoslav




--
You received this message because you are subscribed to the Google Groups &= quot;linux-sunxi" group.
To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-s= unxi+unsubscribe-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org.
For more options, visit http= s://groups.google.com/d/optout.
------=_Part_4178_839273576.1462382682470-- ------=_Part_4177_881679067.1462382682466--