Re: [PATCH 3/5] PCI: mediatek-gen3: Disable ASPM L0s

Manivannan Sadhasivam
2025-01-06T16:10:07Z

On Fri, Jan 03, 2025 at 02:00:13PM +0800, Jianjun Wang wrote:
> Disable ASPM L0s support because it does not significantly save power
> but impacts performance.
>

You should disable ASPM only if it is causing any functional issues to the SoC
itself. For other reasons, users will use the existing sysfs/cmdline params to
disable ASPM based on usecase if required.

- Mani

> Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> ---
> drivers/pci/controller/pcie-mediatek-gen3.c | 11 +++++++++++
> 1 file changed, 11 insertions(+)
>
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index ed3c0614486c..4bd3b39eebe2 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -84,6 +84,9 @@
> #define PCIE_MSI_SET_ENABLE_REG 0x190
> #define PCIE_MSI_SET_ENABLE GENMASK(PCIE_MSI_SET_NUM - 1, 0)
>
> +#define PCIE_LOW_POWER_CTRL_REG 0x194
> +#define PCIE_FORCE_DIS_L0S BIT(8)
> +
> #define PCIE_PIPE4_PIE8_REG 0x338
> #define PCIE_K_FINETUNE_MAX GENMASK(5, 0)
> #define PCIE_K_FINETUNE_ERR GENMASK(7, 6)
> @@ -458,6 +461,14 @@ static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)
> val &= ~PCIE_INTX_ENABLE;
> writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);
>
> + /*
> + * Disable L0s support because it does not significantly save power
> + * but impacts performance.
> + */
> + val = readl_relaxed(pcie->base + PCIE_LOW_POWER_CTRL_REG);
> + val |= PCIE_FORCE_DIS_L0S;
> + writel_relaxed(val, pcie->base + PCIE_LOW_POWER_CTRL_REG);
> +
> /* Disable DVFSRC voltage request */
> val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);
> val |= PCIE_DISABLE_DVFSRC_VLT_REQ;
> --
> 2.46.0
>

--
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