From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,MENTIONS_GIT_HOSTING,NICE_REPLY_A, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5769C433E2 for ; Wed, 2 Sep 2020 17:45:17 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 68AF12071B for ; Wed, 2 Sep 2020 17:45:17 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Gf1h3sAq" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726493AbgIBRpQ (ORCPT ); Wed, 2 Sep 2020 13:45:16 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:52892 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726355AbgIBRpQ (ORCPT ); Wed, 2 Sep 2020 13:45:16 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 082HjBPq063683; Wed, 2 Sep 2020 12:45:11 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1599068711; bh=YR8+4Y2NaPDsev1k+nCcCTn0vlAW0kNUzsYCCQAXhlk=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=Gf1h3sAqJ2PWr5aP2bT/dg/9TPdh8SmlBpL9XD03XXW+WctBoW12ftNorVeIkZbpq RVTZSqGi+rEyuqpPRjmBpn33Sevocx2X+dA4eNp4gOeENOGc12YDOUBQBzLd6v2C7o uxjlzUh9f2zP4CLmBMGWmL0IoRo8ZPhjxhGbFGM0= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTP id 082HjBxW005373; Wed, 2 Sep 2020 12:45:11 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Wed, 2 Sep 2020 12:45:11 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Wed, 2 Sep 2020 12:45:11 -0500 Received: from [10.250.34.112] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 082HjACV020018; Wed, 2 Sep 2020 12:45:11 -0500 Subject: Re: [PATCH 2/7] arm64: dts: ti: k3-am65*: Use generic clock for serdes clock name To: Nishanth Menon , Rob Herring , Tero Kristo CC: , , , Vignesh Raghavendra , , , References: <20200901223059.14801-1-nm@ti.com> <20200901223059.14801-3-nm@ti.com> From: Suman Anna Message-ID: <762671ff-d78a-95aa-2817-62d3ebed104e@ti.com> Date: Wed, 2 Sep 2020 12:45:05 -0500 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20200901223059.14801-3-nm@ti.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 9/1/20 5:30 PM, Nishanth Menon wrote: > Use clock@ naming for nodes following standard conventions of device > tree (section 2.2.2 Generic Names recommendation in [1]). > > [1] https://github.com/devicetree-org/devicetree-specification/tree/v0.3 > > Suggested-by: Suman Anna > Signed-off-by: Nishanth Menon Acked-by: Suman Anna > --- > arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > index 336d09d6fec7..03e28fc256de 100644 > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi > @@ -327,12 +327,12 @@ > reg = <0x00000210 0x4>; > }; > > - serdes0_clk: serdes_clk@4080 { > + serdes0_clk: clock@4080 { > compatible = "syscon"; > reg = <0x00004080 0x4>; > }; > > - serdes1_clk: serdes_clk@4090 { > + serdes1_clk: clock@4090 { > compatible = "syscon"; > reg = <0x00004090 0x4>; > }; > Btw, there is also ehrpwm_tbclk alongside these nodes which is currently defined as a syscon, but is actually a clock. regards Suman