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Mon, 20 Jul 2026 22:26:26 -0700 (PDT) X-Received: by 2002:a05:6a00:3e26:b0:848:2f74:d8da with SMTP id d2e1a72fcca58-84c294c870bmr15377086b3a.75.1784611586174; Mon, 20 Jul 2026 22:26:26 -0700 (PDT) Received: from [10.218.35.45] ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-84c2af6e401sm6649207b3a.48.2026.07.20.22.26.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 20 Jul 2026 22:26:25 -0700 (PDT) Message-ID: <76288f31-57ea-4a42-ad50-8504d8eccfa0@oss.qualcomm.com> Date: Tue, 21 Jul 2026 10:56:20 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/2] arm64: dts: qcom: eliza-evk: Add PCIe1 with TC9563 PCIe switch To: Manivannan Sadhasivam Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-pm@vger.kernel.org References: <20260708-eliza_evk-v2-0-c599246ceba1@oss.qualcomm.com> <20260708-eliza_evk-v2-2-c599246ceba1@oss.qualcomm.com> Content-Language: en-US From: Krishna Chaitanya Chundru In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: hYSKsu11DUvy23I36_GySSoz3903_2Jr X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIxMDA1MyBTYWx0ZWRfX4N38eG3iqivV FxVFEhNXVjDeWwWP374hyco5iGyxgk9Vr5478E2xovdf4YKzOCAutrvBY1UCP5MlG7cpO27jbET NeUYYYIugYdqCrLpdwrCpaZDoVzw9Aw= X-Proofpoint-GUID: hYSKsu11DUvy23I36_GySSoz3903_2Jr X-Authority-Analysis: v=2.4 cv=Sb7HsPRu c=1 sm=1 tr=0 ts=6a5f0303 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=WptVsyCosi7Mub_EgEwA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIxMDA1MyBTYWx0ZWRfX9pXBQmG0FHY/ Bo8XsRoCYXinU7axiKJ9ksgJRzcRT8rCbYyaqQVIFT/niLrnyxVT0E9fJ1xmXfAbhKIeVYTXHYM kOxEPfV5iRyjb1o5SNvHmPy0cZ9VsWg5JJHUcYPWNqSnNA5N5cQ8wxPfaA7HbhlaQGDMSn/wpbA 0/XGDdZGIshXZYbIFeUOZN17LAsQ3GeZpWNj4r2oDVUAlEWIJ5tYrlk0jsaFH/2cnnxK6SV9Jfx ndrKCnnj91XAhj2heyXNu5KhSZWctLAbynkV6lhfh7nzhq1HyWUk127M1yC2ua1qvEDnOzT3qhP S6tFdAoCFNPJy33zg1e6WqtpsE/ZdT4qmVCffv/5Mn+xnu6ugmOxNr5jddenOc1oty3qkZOttGn gq5tnI9URPRhKKm70cyJE8Ncy9Uu/1TvixEyAsFSBE7QPicC/5cnXXDxlfbWAyTUcoZQnSuL3bq cD1F3dLGgbE+UQcA8Fw== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-20_06,2026-07-20_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 phishscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607210053 On 7/9/2026 6:37 PM, Manivannan Sadhasivam wrote: > On Wed, Jul 08, 2026 at 11:47:17AM +0530, Krishna Chaitanya Chundru wrote: >> The Eliza EVK board connects PCIe1 (8GT/s x2) to a Toshiba TC9563 >> PCIe switch. Enable PCIe1 and its QMP PHY nodes. >> >> TC9563 uses I2C (at address 0x77 on I2C4) for its management interface. >> >> Override the base iommu-map with the expanded set covering all the >> switch's downstream ports (0x1400-0x1408 SID range). >> >> The TC9563 RESX# and PERST# are OR-ed internally to assert reset on the >> switch. Use TC9563 RESX# pin via a TLMM GPIO and skip wiring PERST# >> from the PCIe controller. >> >> Signed-off-by: Krishna Chaitanya Chundru >> --- >> arch/arm64/boot/dts/qcom/eliza-evk.dtsi | 112 ++++++++++++++++++++++++++++++++ >> arch/arm64/boot/dts/qcom/eliza.dtsi | 1 + >> 2 files changed, 113 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi >> index 6d76715ccffb..e099b7c8c371 100644 >> --- a/arch/arm64/boot/dts/qcom/eliza-evk.dtsi >> +++ b/arch/arm64/boot/dts/qcom/eliza-evk.dtsi >> @@ -12,6 +12,26 @@ chosen { >> stdout-path = "serial0:115200n8"; >> }; >> >> + vreg_0p9: regulator-0v9 { >> + compatible = "regulator-fixed"; >> + regulator-name = "VREG_0P9"; >> + >> + regulator-min-microvolt = <900000>; >> + regulator-max-microvolt = <900000>; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> + vreg_1p8: regulator-1v8 { >> + compatible = "regulator-fixed"; >> + regulator-name = "VREG_1P8"; >> + >> + regulator-min-microvolt = <1800000>; >> + regulator-max-microvolt = <1800000>; >> + regulator-always-on; >> + regulator-boot-on; >> + }; >> + >> vreg_pcie_m_3p3: regulator-3p3 { >> compatible = "regulator-fixed"; >> >> @@ -99,6 +119,98 @@ pcieport0_ep: endpoint { >> }; >> }; >> >> +&pcie1 { >> + iommu-map = <0x0 &apps_smmu 0x1400 0x1>, >> + <0x100 &apps_smmu 0x1401 0x1>, >> + <0x208 &apps_smmu 0x1402 0x1>, >> + <0x210 &apps_smmu 0x1403 0x1>, >> + <0x218 &apps_smmu 0x1404 0x1>, >> + <0x300 &apps_smmu 0x1405 0x1>, >> + <0x400 &apps_smmu 0x1406 0x1>, >> + <0x500 &apps_smmu 0x1407 0x1>, >> + <0x501 &apps_smmu 0x1408 0x1>; >> + >> + status = "okay"; >> +}; >> + >> +&pcie1_phy { >> + vdda-phy-supply = <&vreg_l1k>; >> + vdda-pll-supply = <&vreg_l3k>; >> + >> + status = "okay"; >> +}; >> + >> +&pcie1port0 { >> + wake-gpios = <&tlmm 53 GPIO_ACTIVE_LOW>; > No reset-gpios? RESX & PERST are ORed in this platform, as we can declare at only one place we declared it in the tc9563 node as resx-gpios - Krishna Chaitanya. > - Mani > >> + >> + tc9563: pcie@0,0 { >> + compatible = "pci1179,0623"; >> + reg = <0x10000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + device_type = "pci"; >> + ranges; >> + bus-range = <0x2 0xff>; >> + >> + vddc-supply = <&vreg_0p9>; >> + vdd18-supply = <&vreg_1p8>; >> + vdd09-supply = <&vreg_0p9>; >> + vddio1-supply = <&vreg_1p8>; >> + vddio2-supply = <&vreg_1p8>; >> + vddio18-supply = <&vreg_1p8>; >> + >> + i2c-parent = <&i2c4 0x77>; >> + >> + resx-gpios = <&tlmm 54 GPIO_ACTIVE_LOW>; >> + >> + pcie@1,0 { >> + reg = <0x20800 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + device_type = "pci"; >> + ranges; >> + bus-range = <0x3 0xff>; >> + }; >> + >> + pcie@2,0 { >> + reg = <0x21000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + >> + device_type = "pci"; >> + ranges; >> + bus-range = <0x4 0xff>; >> + }; >> + >> + pcie@3,0 { >> + reg = <0x21800 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + bus-range = <0x5 0xff>; >> + >> + pci@0,0 { >> + reg = <0x50000 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + }; >> + >> + pci@0,1 { >> + reg = <0x50100 0x0 0x0 0x0 0x0>; >> + #address-cells = <3>; >> + #size-cells = <2>; >> + device_type = "pci"; >> + ranges; >> + }; >> + }; >> + }; >> +}; >> + >> &uart13 { >> compatible = "qcom,geni-debug-uart"; >> >> diff --git a/arch/arm64/boot/dts/qcom/eliza.dtsi b/arch/arm64/boot/dts/qcom/eliza.dtsi >> index cce65e18f979..363cabc5f55c 100644 >> --- a/arch/arm64/boot/dts/qcom/eliza.dtsi >> +++ b/arch/arm64/boot/dts/qcom/eliza.dtsi >> @@ -2102,6 +2102,7 @@ opp-16000000-3 { >> >> }; >> pcie1port0: pcie@0 { >> + compatible = "pciclass,0604"; >> device_type = "pci"; >> reg = <0x0 0x0 0x0 0x0 0x0>; >> bus-range = <0x01 0xff>; >> >> -- >> 2.34.1 >>