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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4391dc9ff64sm44791635e9.9.2025.02.06.23.57.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 06 Feb 2025 23:57:50 -0800 (PST) Message-ID: <76865725-35ce-48c6-822f-ea6cf817cee3@rivosinc.com> Date: Fri, 7 Feb 2025 08:57:48 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 02/21] RISC-V: Add Sxcsrind ISA extension CSR definitions To: Atish Patra , Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, Kaiwen Xue References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> <20250205-counter_delegation-v4-2-835cfa88e3b1@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <20250205-counter_delegation-v4-2-835cfa88e3b1@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06/02/2025 08:23, Atish Patra wrote: > From: Kaiwen Xue > > This adds definitions of new CSRs and bits defined in Sxcsrind ISA > extension. These CSR enables indirect accesses mechanism to access > any CSRs in M-, S-, and VS-mode. The range of the select values > and ireg will be define by the ISA extension using Sxcsrind extension. > > Signed-off-by: Kaiwen Xue > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/csr.h | 30 ++++++++++++++++++++++++++++++ > 1 file changed, 30 insertions(+) > > diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h > index 37bdea65bbd8..2ad2d492e6b4 100644 > --- a/arch/riscv/include/asm/csr.h > +++ b/arch/riscv/include/asm/csr.h > @@ -318,6 +318,12 @@ > /* Supervisor-Level Window to Indirectly Accessed Registers (AIA) */ > #define CSR_SISELECT 0x150 > #define CSR_SIREG 0x151 > +/* Supervisor-Level Window to Indirectly Accessed Registers (Sxcsrind) */ > +#define CSR_SIREG2 0x152 > +#define CSR_SIREG3 0x153 > +#define CSR_SIREG4 0x155 > +#define CSR_SIREG5 0x156 > +#define CSR_SIREG6 0x157 > > /* Supervisor-Level Interrupts (AIA) */ > #define CSR_STOPEI 0x15c > @@ -365,6 +371,14 @@ > /* VS-Level Window to Indirectly Accessed Registers (H-extension with AIA) */ > #define CSR_VSISELECT 0x250 > #define CSR_VSIREG 0x251 > +/* > + * VS-Level Window to Indirectly Accessed Registers (H-extension with Sxcsrind) > + */ > +#define CSR_VSIREG2 0x252 > +#define CSR_VSIREG3 0x253 > +#define CSR_VSIREG4 0x255 > +#define CSR_VSIREG5 0x256 > +#define CSR_VISREG6 0x257 > > /* VS-Level Interrupts (H-extension with AIA) */ > #define CSR_VSTOPEI 0x25c > @@ -407,6 +421,12 @@ > /* Machine-Level Window to Indirectly Accessed Registers (AIA) */ > #define CSR_MISELECT 0x350 > #define CSR_MIREG 0x351 > +/* Machine-Level Window to Indrecitly Accessed Registers (Sxcsrind) */ Typo: s/Indrecitly/Indirectly > +#define CSR_MIREG2 0x352 > +#define CSR_MIREG3 0x353 > +#define CSR_MIREG4 0x355 > +#define CSR_MIREG5 0x356 > +#define CSR_MIREG6 0x357 > > /* Machine-Level Interrupts (AIA) */ > #define CSR_MTOPEI 0x35c > @@ -452,6 +472,11 @@ > # define CSR_IEH CSR_MIEH > # define CSR_ISELECT CSR_MISELECT > # define CSR_IREG CSR_MIREG > +# define CSR_IREG2 CSR_MIREG2 > +# define CSR_IREG3 CSR_MIREG3 > +# define CSR_IREG4 CSR_MIREG4 > +# define CSR_IREG5 CSR_MIREG5 > +# define CSR_IREG6 CSR_MIREG6 > # define CSR_IPH CSR_MIPH > # define CSR_TOPEI CSR_MTOPEI > # define CSR_TOPI CSR_MTOPI > @@ -477,6 +502,11 @@ > # define CSR_IEH CSR_SIEH > # define CSR_ISELECT CSR_SISELECT > # define CSR_IREG CSR_SIREG > +# define CSR_IREG2 CSR_SIREG2 > +# define CSR_IREG3 CSR_SIREG3 > +# define CSR_IREG4 CSR_SIREG4 > +# define CSR_IREG5 CSR_SIREG5 > +# define CSR_IREG6 CSR_SIREG6 > # define CSR_IPH CSR_SIPH > # define CSR_TOPEI CSR_STOPEI > # define CSR_TOPI CSR_STOPI > With that typo fixed: Reviewed-by: Clément Léger Thanks, Clément