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From: Dmitry Osipenko <digetx@gmail.com>
To: "Michał Mirosław" <mirq-linux@rere.qmqm.pl>
Cc: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>,
	Prashant Gaikwad <pgaikwad@nvidia.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	linux-tegra@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v5 2/7] clk: tegra: Fix refcounting of gate clocks
Date: Thu, 18 Mar 2021 13:44:49 +0300	[thread overview]
Message-ID: <768dcbd3-a29b-33c1-2147-e59e3847e75c@gmail.com> (raw)
In-Reply-To: <20210318091219.GA18038@qmqm.qmqm.pl>

18.03.2021 12:12, Michał Mirosław пишет:
> On Wed, Mar 17, 2021 at 10:30:01PM +0300, Dmitry Osipenko wrote:
>> The refcounting of the gate clocks has a bug causing the enable_refcnt
>> to underflow when unused clocks are disabled. This happens because clk
>> provider erroneously bumps the refcount if clock is enabled at a boot
>> time, which it shouldn't be doing, and it does this only for the gate
>> clocks, while peripheral clocks are using the same gate ops and the
>> peripheral clocks are missing the initial bump. Hence the refcount of
>> the peripheral clocks is 0 when unused clocks are disabled and then the
>> counter is decremented further by the gate ops, causing the integer
>> underflow.
> [...]
>> diff --git a/drivers/clk/tegra/clk-periph-gate.c b/drivers/clk/tegra/clk-periph-gate.c
>> index 4b31beefc9fc..3c4259fec82e 100644
>> --- a/drivers/clk/tegra/clk-periph-gate.c
>> +++ b/drivers/clk/tegra/clk-periph-gate.c
> [...]
>> @@ -91,21 +108,28 @@ static void clk_periph_disable(struct clk_hw *hw)
>>  
>>  	spin_lock_irqsave(&periph_ref_lock, flags);
>>  
>> -	gate->enable_refcnt[gate->clk_num]--;
>> -	if (gate->enable_refcnt[gate->clk_num] > 0) {
>> -		spin_unlock_irqrestore(&periph_ref_lock, flags);
>> -		return;
>> -	}
>> +	WARN_ON(!gate->enable_refcnt[gate->clk_num]);
>> +
>> +	if (gate->enable_refcnt[gate->clk_num]-- == 1)
>> +		clk_periph_disable_locked(hw);
> 
> Nit: "if (--n == 0)" seems more natural, as you want to call
> clk_periph_disable_locked() when the refcount goes down to 0.
> 
> [...]
>>  	/*
>> -	 * If peripheral is in the APB bus then read the APB bus to
>> -	 * flush the write operation in apb bus. This will avoid the
>> -	 * peripheral access after disabling clock
>> +	 * Some clocks are duplicated and some of them are marked as critical,
>> +	 * like fuse and fuse_burn for example, thus the enable_refcnt will
>> +	 * be non-zero here id the "unused" duplicate is disabled by CCF.
> 
> s/id/if/ ?

I'll update this patch over the weekend, thanks!

  reply	other threads:[~2021-03-18 10:45 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-17 19:29 [PATCH v5 0/7] Couple improvements for Tegra clk driver Dmitry Osipenko
2021-03-17 19:30 ` [PATCH v5 1/7] clk: tegra30: Use 300MHz for video decoder by default Dmitry Osipenko
2021-03-17 19:30 ` [PATCH v5 2/7] clk: tegra: Fix refcounting of gate clocks Dmitry Osipenko
2021-03-18  9:12   ` Michał Mirosław
2021-03-18 10:44     ` Dmitry Osipenko [this message]
2021-03-17 19:30 ` [PATCH v5 3/7] clk: tegra: Ensure that PLLU configuration is applied properly Dmitry Osipenko
2021-03-17 19:30 ` [PATCH v5 4/7] clk: tegra: Halve SCLK rate on Tegra20 Dmitry Osipenko
2021-03-17 19:30 ` [PATCH v5 5/7] MAINTAINERS: Hand Tegra clk driver to Jon and Thierry Dmitry Osipenko
2021-03-17 19:30 ` [PATCH v5 6/7] clk: tegra: Don't allow zero clock rate for PLLs Dmitry Osipenko
2021-03-17 19:30 ` [PATCH v5 7/7] dt-bindings: clock: tegra: Convert to schema Dmitry Osipenko

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