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([2a00:f41:900a:a4b1:c71b:4253:8a9f:c478]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-52ca282ee85sm114279e87.111.2024.06.13.00.42.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 13 Jun 2024 00:42:02 -0700 (PDT) Message-ID: <76f5e3c7-a90b-42d2-8169-e5e2211a14a1@linaro.org> Date: Thu, 13 Jun 2024 09:41:59 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V4 8/8] arm64: dts: qcom: sm4450: add camera, display and gpu clock controller To: Ajit Pandey , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Vinod Koul , Vladimir Zapolskiy Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Taniya Das , Jagadeesh Kona , Imran Shaik , Satya Priya Kakitapalli References: <20240611133752.2192401-1-quic_ajipan@quicinc.com> <20240611133752.2192401-9-quic_ajipan@quicinc.com> Content-Language: en-US From: Konrad Dybcio In-Reply-To: <20240611133752.2192401-9-quic_ajipan@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/11/24 15:37, Ajit Pandey wrote: > Add device node for camera, display and graphics clock controller on > Qualcomm SM4450 platform. > > Signed-off-by: Ajit Pandey > --- None of these nodes reference a power domain (which would usually be CX/MX/MMCX). This way, the RPMhPDs will never be scaled. The current upstream implementation only allows one power domain to be scaled, but that's better than none (see other DTs for recent SoCs). Konrad