* [PATCH v5 1/5] dt-bindings: display: msm: dp-controller: document SM8450 compatible
2023-03-17 9:12 [PATCH v5 0/5] arm64: dts: qcom: add DP Controller to SM8350 & SM8450 DTS Neil Armstrong
@ 2023-03-17 9:12 ` Neil Armstrong
2023-03-17 9:12 ` [PATCH v5 2/5] arm64: dts: qcom: sm8350: switch to combo usb3/dp phy Neil Armstrong
` (3 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Neil Armstrong @ 2023-03-17 9:12 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Kuogee Hsieh, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong, Krzysztof Kozlowski
The SM8450 & SM350 shares the same DT TX IP version, use the
SM8350 compatible as fallback for SM8450.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
.../bindings/display/msm/dp-controller.yaml | 25 +++++++++++++---------
1 file changed, 15 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
index 0e8d8df686dc..f0c2237d5f82 100644
--- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
+++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml
@@ -15,16 +15,21 @@ description: |
properties:
compatible:
- enum:
- - qcom,sc7180-dp
- - qcom,sc7280-dp
- - qcom,sc7280-edp
- - qcom,sc8180x-dp
- - qcom,sc8180x-edp
- - qcom,sc8280xp-dp
- - qcom,sc8280xp-edp
- - qcom,sdm845-dp
- - qcom,sm8350-dp
+ oneOf:
+ - enum:
+ - qcom,sc7180-dp
+ - qcom,sc7280-dp
+ - qcom,sc7280-edp
+ - qcom,sc8180x-dp
+ - qcom,sc8180x-edp
+ - qcom,sc8280xp-dp
+ - qcom,sc8280xp-edp
+ - qcom,sdm845-dp
+ - qcom,sm8350-dp
+ - items:
+ - enum:
+ - qcom,sm8450-dp
+ - const: qcom,sm8350-dp
reg:
minItems: 4
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 2/5] arm64: dts: qcom: sm8350: switch to combo usb3/dp phy
2023-03-17 9:12 [PATCH v5 0/5] arm64: dts: qcom: add DP Controller to SM8350 & SM8450 DTS Neil Armstrong
2023-03-17 9:12 ` [PATCH v5 1/5] dt-bindings: display: msm: dp-controller: document SM8450 compatible Neil Armstrong
@ 2023-03-17 9:12 ` Neil Armstrong
2023-03-17 9:12 ` [PATCH v5 3/5] arm64: dts: qcom: sm8350: add dp controller Neil Armstrong
` (2 subsequent siblings)
4 siblings, 0 replies; 11+ messages in thread
From: Neil Armstrong @ 2023-03-17 9:12 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Kuogee Hsieh, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
The first QMP PHY is an USB3/DP combo phy, switch to the newly
documented bindings and register the clocks to the GCC
and DISPCC controllers.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #SM8350-HDK
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 42 +++++++++++++-----------------------
1 file changed, 15 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 1afc4311796e..975ab4cbe57e 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -13,6 +13,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interconnect/qcom,sm8350.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/thermal/thermal.h>
@@ -661,7 +662,7 @@ gcc: clock-controller@100000 {
<&ufs_mem_phy_lanes 0>,
<&ufs_mem_phy_lanes 1>,
<&ufs_mem_phy_lanes 2>,
- <0>,
+ <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<0>;
};
@@ -2135,37 +2136,24 @@ usb_2_hsphy: phy@88e4000 {
resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
};
- usb_1_qmpphy: phy-wrapper@88e9000 {
- compatible = "qcom,sm8350-qmp-usb3-phy";
- reg = <0 0x088e9000 0 0x200>,
- <0 0x088e8000 0 0x20>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ usb_1_qmpphy: phy@88e9000 {
+ compatible = "qcom,sm8350-qmp-usb3-dp-phy";
+ reg = <0 0x088e8000 0 0x3000>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux", "ref", "com_aux", "usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x400>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
};
usb_2_qmpphy: phy-wrapper@88eb000 {
@@ -2268,7 +2256,7 @@ usb_1_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
};
};
@@ -2633,8 +2621,8 @@ dispcc: clock-controller@af00000 {
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>,
- <0>,
- <0>;
+ <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v5 3/5] arm64: dts: qcom: sm8350: add dp controller
2023-03-17 9:12 [PATCH v5 0/5] arm64: dts: qcom: add DP Controller to SM8350 & SM8450 DTS Neil Armstrong
2023-03-17 9:12 ` [PATCH v5 1/5] dt-bindings: display: msm: dp-controller: document SM8450 compatible Neil Armstrong
2023-03-17 9:12 ` [PATCH v5 2/5] arm64: dts: qcom: sm8350: switch to combo usb3/dp phy Neil Armstrong
@ 2023-03-17 9:12 ` Neil Armstrong
2023-03-17 12:16 ` Dmitry Baryshkov
2023-03-17 9:12 ` [PATCH v5 4/5] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy Neil Armstrong
2023-03-17 9:12 ` [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller Neil Armstrong
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2023-03-17 9:12 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Kuogee Hsieh, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
Add the Display Port controller subnode to the MDSS node.
Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #SM8350-HDK
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8350.dtsi | 74 ++++++++++++++++++++++++++++++++++++
1 file changed, 74 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 975ab4cbe57e..37ae4a948be1 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2415,6 +2415,80 @@ dpu_intf2_out: endpoint {
remote-endpoint = <&mdss_dsi1_in>;
};
};
+
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp_in>;
+ };
+ };
+ };
+ };
+
+ mdss_dp: displayport-controller@ae90000 {
+ compatible = "qcom,sm8350-dp";
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SM8350_MMCX>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 3/5] arm64: dts: qcom: sm8350: add dp controller
2023-03-17 9:12 ` [PATCH v5 3/5] arm64: dts: qcom: sm8350: add dp controller Neil Armstrong
@ 2023-03-17 12:16 ` Dmitry Baryshkov
0 siblings, 0 replies; 11+ messages in thread
From: Dmitry Baryshkov @ 2023-03-17 12:16 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Kuogee Hsieh,
Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 17/03/2023 11:12, Neil Armstrong wrote:
> Add the Display Port controller subnode to the MDSS node.
>
> Tested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> #SM8350-HDK
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8350.dtsi | 74 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 74 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> index 975ab4cbe57e..37ae4a948be1 100644
> --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
> @@ -2415,6 +2415,80 @@ dpu_intf2_out: endpoint {
> remote-endpoint = <&mdss_dsi1_in>;
> };
> };
> +
> + port@2 {
> + reg = <2>;
> + dpu_intf0_out: endpoint {
> + remote-endpoint = <&mdss_dp_in>;
> + };
> + };
> + };
> + };
> +
> + mdss_dp: displayport-controller@ae90000 {
> + compatible = "qcom,sm8350-dp";
> + reg = <0 0xae90000 0 0x200>,
> + <0 0xae90200 0 0x200>,
> + <0 0xae90400 0 0x600>,
> + <0 0xae91000 0 0x400>,
> + <0 0xae91400 0 0x400>;
> + interrupt-parent = <&mdss>;
> + interrupts = <12>;
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
> + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + operating-points-v2 = <&dp_opp_table>;
> + power-domains = <&rpmhpd SM8350_MMCX>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dp_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> + };
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
I think we still need an OPP entry for RBR rate (160000000). Downstream
would resort to low_svs in such case, the min voltage for MMCX domain.
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> };
> };
>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 4/5] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy
2023-03-17 9:12 [PATCH v5 0/5] arm64: dts: qcom: add DP Controller to SM8350 & SM8450 DTS Neil Armstrong
` (2 preceding siblings ...)
2023-03-17 9:12 ` [PATCH v5 3/5] arm64: dts: qcom: sm8350: add dp controller Neil Armstrong
@ 2023-03-17 9:12 ` Neil Armstrong
2023-03-17 12:09 ` Dmitry Baryshkov
2023-03-17 9:12 ` [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller Neil Armstrong
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2023-03-17 9:12 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Kuogee Hsieh, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
The QMP PHY is a USB3/DP combo phy, switch to the newly
documented bindings and register the clocks to the GCC
and DISPCC controllers.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 +++++++++++++-----------------------
1 file changed, 15 insertions(+), 27 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 69695eb83897..0b5a151ce138 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -11,6 +11,7 @@
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/interconnect/qcom,sm8450.h>
#include <dt-bindings/soc/qcom,gpr.h>
@@ -748,7 +749,7 @@ gcc: clock-controller@100000 {
<&ufs_mem_phy_lanes 0>,
<&ufs_mem_phy_lanes 1>,
<&ufs_mem_phy_lanes 2>,
- <0>;
+ <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
clock-names = "bi_tcxo",
"sleep_clk",
"pcie_0_pipe_clk",
@@ -2034,37 +2035,24 @@ usb_1_hsphy: phy@88e3000 {
resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
};
- usb_1_qmpphy: phy-wrapper@88e9000 {
- compatible = "qcom,sm8450-qmp-usb3-phy";
- reg = <0 0x088e9000 0 0x200>,
- <0 0x088e8000 0 0x20>;
- status = "disabled";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
+ usb_1_qmpphy: phy@88e8000 {
+ compatible = "qcom,sm8450-qmp-usb3-dp-phy";
+ reg = <0 0x088e8000 0 0x4000>;
clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
- clock-names = "aux", "ref_clk_src", "com_aux";
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux", "ref", "com_aux", "usb3_pipe";
resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
<&gcc GCC_USB3_PHY_PRIM_BCR>;
reset-names = "phy", "common";
- usb_1_ssphy: phy@88e9200 {
- reg = <0 0x088e9200 0 0x200>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x400>,
- <0 0x088e9600 0 0x200>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
- #phy-cells = <0>;
- #clock-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
- };
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
};
remoteproc_slpi: remoteproc@2400000 {
@@ -2972,8 +2960,8 @@ dispcc: clock-controller@af00000 {
<&mdss_dsi0_phy 1>,
<&mdss_dsi1_phy 0>,
<&mdss_dsi1_phy 1>,
- <0>, /* dp0 */
- <0>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
<0>, /* dp1 */
<0>,
<0>, /* dp2 */
@@ -4168,7 +4156,7 @@ usb_1_dwc3: usb@a600000 {
iommus = <&apps_smmu 0x0 0x0>;
snps,dis_u2_susphy_quirk;
snps,dis_enblslpm_quirk;
- phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
+ phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
phy-names = "usb2-phy", "usb3-phy";
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 4/5] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy
2023-03-17 9:12 ` [PATCH v5 4/5] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy Neil Armstrong
@ 2023-03-17 12:09 ` Dmitry Baryshkov
2023-03-17 14:28 ` Neil Armstrong
0 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2023-03-17 12:09 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Kuogee Hsieh,
Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 17/03/2023 11:12, Neil Armstrong wrote:
> The QMP PHY is a USB3/DP combo phy, switch to the newly
> documented bindings and register the clocks to the GCC
> and DISPCC controllers.
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 +++++++++++++-----------------------
> 1 file changed, 15 insertions(+), 27 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 69695eb83897..0b5a151ce138 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -11,6 +11,7 @@
> #include <dt-bindings/dma/qcom-gpi.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/interconnect/qcom,sm8450.h>
> #include <dt-bindings/soc/qcom,gpr.h>
> @@ -748,7 +749,7 @@ gcc: clock-controller@100000 {
> <&ufs_mem_phy_lanes 0>,
> <&ufs_mem_phy_lanes 1>,
> <&ufs_mem_phy_lanes 2>,
> - <0>;
> + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> clock-names = "bi_tcxo",
> "sleep_clk",
> "pcie_0_pipe_clk",
> @@ -2034,37 +2035,24 @@ usb_1_hsphy: phy@88e3000 {
> resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> };
>
> - usb_1_qmpphy: phy-wrapper@88e9000 {
> - compatible = "qcom,sm8450-qmp-usb3-phy";
> - reg = <0 0x088e9000 0 0x200>,
> - <0 0x088e8000 0 0x20>;
> - status = "disabled";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> + usb_1_qmpphy: phy@88e8000 {
> + compatible = "qcom,sm8450-qmp-usb3-dp-phy";
> + reg = <0 0x088e8000 0 0x4000>;
This should be 0x3000 too, like 8350
>
> clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> <&rpmhcc RPMH_CXO_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> - clock-names = "aux", "ref_clk_src", "com_aux";
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux", "ref", "com_aux", "usb3_pipe";
>
> resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> <&gcc GCC_USB3_PHY_PRIM_BCR>;
> reset-names = "phy", "common";
>
> - usb_1_ssphy: phy@88e9200 {
> - reg = <0 0x088e9200 0 0x200>,
> - <0 0x088e9400 0 0x200>,
> - <0 0x088e9c00 0 0x400>,
> - <0 0x088e9600 0 0x200>,
> - <0 0x088e9800 0 0x200>,
> - <0 0x088e9a00 0 0x100>;
> - #phy-cells = <0>;
> - #clock-cells = <0>;
> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> - clock-names = "pipe0";
> - clock-output-names = "usb3_phy_pipe_clk_src";
> - };
> + #clock-cells = <1>;
> + #phy-cells = <1>;
> +
> + status = "disabled";
> };
>
> remoteproc_slpi: remoteproc@2400000 {
> @@ -2972,8 +2960,8 @@ dispcc: clock-controller@af00000 {
> <&mdss_dsi0_phy 1>,
> <&mdss_dsi1_phy 0>,
> <&mdss_dsi1_phy 1>,
> - <0>, /* dp0 */
> - <0>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
> <0>, /* dp1 */
> <0>,
> <0>, /* dp2 */
> @@ -4168,7 +4156,7 @@ usb_1_dwc3: usb@a600000 {
> iommus = <&apps_smmu 0x0 0x0>;
> snps,dis_u2_susphy_quirk;
> snps,dis_enblslpm_quirk;
> - phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
> phy-names = "usb2-phy", "usb3-phy";
> };
> };
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v5 4/5] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy
2023-03-17 12:09 ` Dmitry Baryshkov
@ 2023-03-17 14:28 ` Neil Armstrong
0 siblings, 0 replies; 11+ messages in thread
From: Neil Armstrong @ 2023-03-17 14:28 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Kuogee Hsieh, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 17/03/2023 13:09, Dmitry Baryshkov wrote:
> On 17/03/2023 11:12, Neil Armstrong wrote:
>> The QMP PHY is a USB3/DP combo phy, switch to the newly
>> documented bindings and register the clocks to the GCC
>> and DISPCC controllers.
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 +++++++++++++-----------------------
>> 1 file changed, 15 insertions(+), 27 deletions(-)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 69695eb83897..0b5a151ce138 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -11,6 +11,7 @@
>> #include <dt-bindings/dma/qcom-gpi.h>
>> #include <dt-bindings/gpio/gpio.h>
>> #include <dt-bindings/mailbox/qcom-ipcc.h>
>> +#include <dt-bindings/phy/phy-qcom-qmp.h>
>> #include <dt-bindings/power/qcom-rpmpd.h>
>> #include <dt-bindings/interconnect/qcom,sm8450.h>
>> #include <dt-bindings/soc/qcom,gpr.h>
>> @@ -748,7 +749,7 @@ gcc: clock-controller@100000 {
>> <&ufs_mem_phy_lanes 0>,
>> <&ufs_mem_phy_lanes 1>,
>> <&ufs_mem_phy_lanes 2>,
>> - <0>;
>> + <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
>> clock-names = "bi_tcxo",
>> "sleep_clk",
>> "pcie_0_pipe_clk",
>> @@ -2034,37 +2035,24 @@ usb_1_hsphy: phy@88e3000 {
>> resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
>> };
>> - usb_1_qmpphy: phy-wrapper@88e9000 {
>> - compatible = "qcom,sm8450-qmp-usb3-phy";
>> - reg = <0 0x088e9000 0 0x200>,
>> - <0 0x088e8000 0 0x20>;
>> - status = "disabled";
>> - #address-cells = <2>;
>> - #size-cells = <2>;
>> - ranges;
>> + usb_1_qmpphy: phy@88e8000 {
>> + compatible = "qcom,sm8450-qmp-usb3-dp-phy";
>> + reg = <0 0x088e8000 0 0x4000>;
>
> This should be 0x3000 too, like 8350
Ack thx for noticing
>
>> clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
>> <&rpmhcc RPMH_CXO_CLK>,
>> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
>> - clock-names = "aux", "ref_clk_src", "com_aux";
>> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
>> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> + clock-names = "aux", "ref", "com_aux", "usb3_pipe";
>> resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
>> <&gcc GCC_USB3_PHY_PRIM_BCR>;
>> reset-names = "phy", "common";
>> - usb_1_ssphy: phy@88e9200 {
>> - reg = <0 0x088e9200 0 0x200>,
>> - <0 0x088e9400 0 0x200>,
>> - <0 0x088e9c00 0 0x400>,
>> - <0 0x088e9600 0 0x200>,
>> - <0 0x088e9800 0 0x200>,
>> - <0 0x088e9a00 0 0x100>;
>> - #phy-cells = <0>;
>> - #clock-cells = <0>;
>> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
>> - clock-names = "pipe0";
>> - clock-output-names = "usb3_phy_pipe_clk_src";
>> - };
>> + #clock-cells = <1>;
>> + #phy-cells = <1>;
>> +
>> + status = "disabled";
>> };
>> remoteproc_slpi: remoteproc@2400000 {
>> @@ -2972,8 +2960,8 @@ dispcc: clock-controller@af00000 {
>> <&mdss_dsi0_phy 1>,
>> <&mdss_dsi1_phy 0>,
>> <&mdss_dsi1_phy 1>,
>> - <0>, /* dp0 */
>> - <0>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
>> <0>, /* dp1 */
>> <0>,
>> <0>, /* dp2 */
>> @@ -4168,7 +4156,7 @@ usb_1_dwc3: usb@a600000 {
>> iommus = <&apps_smmu 0x0 0x0>;
>> snps,dis_u2_susphy_quirk;
>> snps,dis_enblslpm_quirk;
>> - phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
>> + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
>> phy-names = "usb2-phy", "usb3-phy";
>> };
>> };
>>
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller
2023-03-17 9:12 [PATCH v5 0/5] arm64: dts: qcom: add DP Controller to SM8350 & SM8450 DTS Neil Armstrong
` (3 preceding siblings ...)
2023-03-17 9:12 ` [PATCH v5 4/5] arm64: dts: qcom: sm8450: switch to usb3/dp combo phy Neil Armstrong
@ 2023-03-17 9:12 ` Neil Armstrong
2023-03-17 12:19 ` Dmitry Baryshkov
4 siblings, 1 reply; 11+ messages in thread
From: Neil Armstrong @ 2023-03-17 9:12 UTC (permalink / raw)
To: Rob Clark, Abhinav Kumar, Dmitry Baryshkov, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Kuogee Hsieh, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel,
Neil Armstrong
Add the Display Port controller subnode to the MDSS node.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8450.dtsi | 79 ++++++++++++++++++++++++++++++++++++
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 0b5a151ce138..41f5015e615b 100644
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint {
};
};
+ port@2 {
+ reg = <2>;
+ dpu_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+
};
mdp_opp_table: opp-table {
@@ -2783,6 +2790,78 @@ opp-500000000 {
};
};
+ mdss_dp0: displayport-controller@ae90000 {
+ compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0xc00>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+ interrupt-parent = <&mdss>;
+ interrupts = <12>;
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ operating-points-v2 = <&dp_opp_table>;
+ power-domains = <&rpmhpd SM8450_MMCX>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&dpu_intf0_out>;
+ };
+ };
+ };
+
+ dp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-19200000 {
+ opp-hz = /bits/ 64 <19200000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
mdss_dsi0: dsi@ae94000 {
compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
reg = <0 0x0ae94000 0 0x400>;
--
2.34.1
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller
2023-03-17 9:12 ` [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller Neil Armstrong
@ 2023-03-17 12:19 ` Dmitry Baryshkov
2023-03-17 13:39 ` Neil Armstrong
0 siblings, 1 reply; 11+ messages in thread
From: Dmitry Baryshkov @ 2023-03-17 12:19 UTC (permalink / raw)
To: Neil Armstrong, Rob Clark, Abhinav Kumar, Sean Paul, David Airlie,
Daniel Vetter, Rob Herring, Krzysztof Kozlowski, Kuogee Hsieh,
Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 17/03/2023 11:12, Neil Armstrong wrote:
> Add the Display Port controller subnode to the MDSS node.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/sm8450.dtsi | 79 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 79 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> index 0b5a151ce138..41f5015e615b 100644
> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
> @@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint {
> };
> };
>
> + port@2 {
> + reg = <2>;
> + dpu_intf0_out: endpoint {
> + remote-endpoint = <&mdss_dp0_in>;
> + };
> + };
> +
> };
>
> mdp_opp_table: opp-table {
> @@ -2783,6 +2790,78 @@ opp-500000000 {
> };
> };
>
> + mdss_dp0: displayport-controller@ae90000 {
> + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
> + reg = <0 0xae90000 0 0x200>,
> + <0 0xae90200 0 0x200>,
> + <0 0xae90400 0 0xc00>,
> + <0 0xae91000 0 0x400>,
> + <0 0xae91400 0 0x400>;
> + interrupt-parent = <&mdss>;
> + interrupts = <12>;
> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
> + clock-names = "core_iface",
> + "core_aux",
> + "ctrl_link",
> + "ctrl_link_iface",
> + "stream_pixel";
> +
> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
> + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
> +
> + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
> + phy-names = "dp";
> +
> + #sound-dai-cells = <0>;
> +
> + operating-points-v2 = <&dp_opp_table>;
> + power-domains = <&rpmhpd SM8450_MMCX>;
> +
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@0 {
> + reg = <0>;
> + mdss_dp0_in: endpoint {
> + remote-endpoint = <&dpu_intf0_out>;
> + };
> + };
> + };
> +
> + dp_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-19200000 {
> + opp-hz = /bits/ 64 <19200000>;
> + required-opps = <&rpmhpd_opp_low_svs>;
> + };
Yes, the vendor kernel has 19.2 MHz as a frequency for the low_svs.
However I don't think we should do it this way, we list DP rates here,
so the lowest entry should be RBR, 160000000.
> +
> + opp-270000000 {
> + opp-hz = /bits/ 64 <270000000>;
> + required-opps = <&rpmhpd_opp_svs>;
> + };
> +
> + opp-540000000 {
> + opp-hz = /bits/ 64 <540000000>;
> + required-opps = <&rpmhpd_opp_svs_l1>;
> + };
> +
> + opp-810000000 {
> + opp-hz = /bits/ 64 <810000000>;
> + required-opps = <&rpmhpd_opp_nom>;
> + };
> + };
> + };
> +
> mdss_dsi0: dsi@ae94000 {
> compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
> reg = <0 0x0ae94000 0 0x400>;
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v5 5/5] arm64: dts: qcom: sm8450: add dp controller
2023-03-17 12:19 ` Dmitry Baryshkov
@ 2023-03-17 13:39 ` Neil Armstrong
0 siblings, 0 replies; 11+ messages in thread
From: Neil Armstrong @ 2023-03-17 13:39 UTC (permalink / raw)
To: Dmitry Baryshkov, Rob Clark, Abhinav Kumar, Sean Paul,
David Airlie, Daniel Vetter, Rob Herring, Krzysztof Kozlowski,
Kuogee Hsieh, Andy Gross, Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dri-devel, freedreno, devicetree, linux-kernel
On 17/03/2023 13:19, Dmitry Baryshkov wrote:
> On 17/03/2023 11:12, Neil Armstrong wrote:
>> Add the Display Port controller subnode to the MDSS node.
>>
>> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
>> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
>> ---
>> arch/arm64/boot/dts/qcom/sm8450.dtsi | 79 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 79 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> index 0b5a151ce138..41f5015e615b 100644
>> --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
>> @@ -2751,6 +2751,13 @@ dpu_intf2_out: endpoint {
>> };
>> };
>> + port@2 {
>> + reg = <2>;
>> + dpu_intf0_out: endpoint {
>> + remote-endpoint = <&mdss_dp0_in>;
>> + };
>> + };
>> +
>> };
>> mdp_opp_table: opp-table {
>> @@ -2783,6 +2790,78 @@ opp-500000000 {
>> };
>> };
>> + mdss_dp0: displayport-controller@ae90000 {
>> + compatible = "qcom,sm8450-dp", "qcom,sm8350-dp";
>> + reg = <0 0xae90000 0 0x200>,
>> + <0 0xae90200 0 0x200>,
>> + <0 0xae90400 0 0xc00>,
>> + <0 0xae91000 0 0x400>,
>> + <0 0xae91400 0 0x400>;
>> + interrupt-parent = <&mdss>;
>> + interrupts = <12>;
>> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
>> + clock-names = "core_iface",
>> + "core_aux",
>> + "ctrl_link",
>> + "ctrl_link_iface",
>> + "stream_pixel";
>> +
>> + assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
>> + <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
>> + assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
>> + <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
>> +
>> + phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>;
>> + phy-names = "dp";
>> +
>> + #sound-dai-cells = <0>;
>> +
>> + operating-points-v2 = <&dp_opp_table>;
>> + power-domains = <&rpmhpd SM8450_MMCX>;
>> +
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@0 {
>> + reg = <0>;
>> + mdss_dp0_in: endpoint {
>> + remote-endpoint = <&dpu_intf0_out>;
>> + };
>> + };
>> + };
>> +
>> + dp_opp_table: opp-table {
>> + compatible = "operating-points-v2";
>> +
>> + opp-19200000 {
>> + opp-hz = /bits/ 64 <19200000>;
>> + required-opps = <&rpmhpd_opp_low_svs>;
>> + };
>
> Yes, the vendor kernel has 19.2 MHz as a frequency for the low_svs. However I don't think we should do it this way, we list DP rates here, so the lowest entry should be RBR, 160000000.
Ok so v4 for ok for both patches 3 & 5
Will send v6 with those reverted
Neil
>
>> +
>> + opp-270000000 {
>> + opp-hz = /bits/ 64 <270000000>;
>> + required-opps = <&rpmhpd_opp_svs>;
>> + };
>> +
>> + opp-540000000 {
>> + opp-hz = /bits/ 64 <540000000>;
>> + required-opps = <&rpmhpd_opp_svs_l1>;
>> + };
>> +
>> + opp-810000000 {
>> + opp-hz = /bits/ 64 <810000000>;
>> + required-opps = <&rpmhpd_opp_nom>;
>> + };
>> + };
>> + };
>> +
>> mdss_dsi0: dsi@ae94000 {
>> compatible = "qcom,sm8450-dsi-ctrl", "qcom,mdss-dsi-ctrl";
>> reg = <0 0x0ae94000 0 0x400>;
>>
>
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