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Fri, 08 Aug 2025 22:09:33 -0700 (PDT) Message-ID: <7737de72-701a-43ce-88a4-90d2d17c48f8@tuxon.dev> Date: Sat, 9 Aug 2025 08:09:32 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 3/4] arm64: dts: renesas: rzg3s-smarc-som: Enable I3C To: Wolfram Sang , linux-renesas-soc@vger.kernel.org Cc: Geert Uytterhoeven , Magnus Damm , Rob Herring , Krzysztof Kozlowski , Conor Dooley , devicetree@vger.kernel.org References: <20250807151434.5241-6-wsa+renesas@sang-engineering.com> <20250807151434.5241-9-wsa+renesas@sang-engineering.com> From: Claudiu Beznea Content-Language: en-US In-Reply-To: <20250807151434.5241-9-wsa+renesas@sang-engineering.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Hi, Wolfram, On 07.08.2025 18:14, Wolfram Sang wrote: > Enable I3C on the dedicated connector of the RZ/G3S module. Provide > safe defaults allowing to connect even to slow I2C devices. > > Signed-off-by: Wolfram Sang > --- > arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi > index 39845faec894..17fd30df3432 100644 > --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi > +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi > @@ -7,6 +7,7 @@ > > #include > #include > +#include > #include > > #include "rzg3s-smarc-switches.h" > @@ -172,6 +173,12 @@ a0 80 30 30 9c > }; > }; > > +&i3c { > + i2c-scl-hz = <100000>; > + i3c-scl-hz = <12500000>; I'm not familiar with I3C but from the HW manual it seems there is some level of control for I3C in pin controller: - on Input Enable Control Register (IEN_m) there is this note: Note 1. 1b: applies to terminals of TMS_SWDIO, I3C_SCL, I3C_SDA, P1_0, P7_0 - there is I3C_SET register (bit POC) which controls the I3C voltage, so, I presume, depending on the SW_I3C_VIO_SEL switch on the board (which selects the output of VDD_I3C regulator) the pins would have to be configured with proper power-source = <1800> or power-source = <1200> Thank you, Claudiu > + status = "okay"; > +}; > + > #if SW_CONFIG2 == SW_ON > /* SD0 slot */ > &sdhi0 {