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[98.183.112.25]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5eb4eee7f3csm263487eaf.47.2024.10.15.07.40.29 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 15 Oct 2024 07:40:30 -0700 (PDT) Message-ID: <776ed45e-7ca8-42e8-9050-86928f223965@baylibre.com> Date: Tue, 15 Oct 2024 09:40:28 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 2/8] dt-bindings: iio: dac: adi-axi-dac: add ad3552r axi variant To: Angelo Dureghello Cc: =?UTF-8?Q?Nuno_S=C3=A1?= , Lars-Peter Clausen , Michael Hennerich , Jonathan Cameron , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Olivier Moysan , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Mark Brown References: <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-0-eeef0c1e0e56@baylibre.com> <20241014-wip-bl-ad3552r-axi-v0-iio-testing-v6-2-eeef0c1e0e56@baylibre.com> Content-Language: en-US From: David Lechner In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/15/24 2:44 AM, Angelo Dureghello wrote: > On 14.10.2024 16:13, David Lechner wrote: >> On 10/14/24 5:08 AM, Angelo Dureghello wrote: >>> From: Angelo Dureghello >>> >>> Add a new compatible and related bindigns for the fpga-based >>> "ad3552r" AXI IP core, a variant of the generic AXI DAC IP. >>> >>> The AXI "ad3552r" IP is a very similar HDL (fpga) variant of the >>> generic AXI "DAC" IP, intended to control ad3552r and similar chips, >>> mainly to reach high speed transfer rates using a QSPI DDR >>> (dobule-data-rate) interface. >>> >>> The ad3552r device is defined as a child of the AXI DAC, that in >>> this case is acting as an SPI controller. >>> >>> Note, #io-backend is present because it is possible (in theory anyway) >>> to use a separate controller for the control path than that used >>> for the datapath. >>> >>> Signed-off-by: Angelo Dureghello >>> --- >>> .../devicetree/bindings/iio/dac/adi,axi-dac.yaml | 56 ++++++++++++++++++++-- >>> 1 file changed, 53 insertions(+), 3 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>> index a55e9bfc66d7..2b7e16717219 100644 >>> --- a/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>> +++ b/Documentation/devicetree/bindings/iio/dac/adi,axi-dac.yaml >>> @@ -19,11 +19,13 @@ description: | >>> memory via DMA into the DAC. >>> >>> https://wiki.analog.com/resources/fpga/docs/axi_dac_ip >>> + https://analogdevicesinc.github.io/hdl/library/axi_ad3552r/index.html >>> >>> properties: >>> compatible: >>> enum: >>> - adi,axi-dac-9.1.b >>> + - adi,axi-ad3552r >>> >>> reg: >>> maxItems: 1 >>> @@ -36,7 +38,14 @@ properties: >>> - const: tx >>> >>> clocks: >>> - maxItems: 1 >>> + minItems: 1 >>> + maxItems: 2 >>> + >>> + clock-names: >>> + minItems: 1 >>> + items: >>> + - const: s_axi_aclk >>> + - const: dac_clk >>> >>> '#io-backend-cells': >>> const: 0 >>> @@ -47,7 +56,16 @@ required: >>> - reg >>> - clocks >>> >>> -additionalProperties: false >>> +allOf: >>> + - if: >>> + properties: >>> + compatible: >>> + contains: >>> + const: adi,axi-ad3552r >>> + then: >>> + $ref: /schemas/spi/spi-controller.yaml# >> + properties: >> + clocks: >> + minItems: 2 >> + clock-names: >> + minItems: 2 >> + required: >> + clock-names >> + else: >> + properties: >> + clocks: >> + maxItems: 1 >> + clock-names: >> + maxItems: 1 >> >> We could make the checking of clocks more strict to show >> the intent: >> >> adi,axi-dac-9.1.b only has 1 clock and clock-names is optional. >> >> adi,axi-ad3552r always has 2 clocks and clock-names is required. >> > is this really necessary ? At v.6 would not fix things > not reallyh necessary. > It is just a suggestion from me. I will leave it to the maintainers to say if it is necessary or not. (If they don't say anything, then we'll take it to mean it isn't necessary.)