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[109.252.193.186]) by smtp.googlemail.com with ESMTPSA id x19sm265377lff.189.2020.10.27.12.18.35 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Oct 2020 12:18:36 -0700 (PDT) Subject: Re: [PATCH v6 09/52] dt-bindings: memory: tegra30: mc: Document new interconnect property To: Krzysztof Kozlowski Cc: Thierry Reding , Jonathan Hunter , Georgi Djakov , Rob Herring , Michael Turquette , Stephen Boyd , Peter De Schrijver , MyungJoo Ham , Kyungmin Park , Chanwoo Choi , Mikko Perttunen , Viresh Kumar , Peter Geis , Nicolas Chauvet , linux-tegra@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org References: <20201025221735.3062-1-digetx@gmail.com> <20201025221735.3062-10-digetx@gmail.com> <20201027090550.GI4244@kozik-lap> From: Dmitry Osipenko Message-ID: <7770b89e-f30b-3bfd-1e21-8ebbe905efcd@gmail.com> Date: Tue, 27 Oct 2020 22:18:35 +0300 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201027090550.GI4244@kozik-lap> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org 27.10.2020 12:05, Krzysztof Kozlowski пишет: > On Mon, Oct 26, 2020 at 01:16:52AM +0300, Dmitry Osipenko wrote: >> Memory controller is interconnected with memory clients and with the >> External Memory Controller. Document new interconnect property which >> turns memory controller into interconnect provider. >> >> Acked-by: Rob Herring >> Signed-off-by: Dmitry Osipenko >> --- >> .../bindings/memory-controllers/nvidia,tegra30-mc.yaml | 5 +++++ >> 1 file changed, 5 insertions(+) >> >> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml >> index 84fd57bcf0dc..5436e6d420bc 100644 >> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml >> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml >> @@ -57,6 +57,9 @@ properties: >> "#iommu-cells": >> const: 1 >> >> + "#interconnect-cells": >> + const: 1 >> + >> patternProperties: >> "^emc-timings-[0-9]+$": >> type: object >> @@ -120,6 +123,7 @@ required: >> - clock-names >> - "#reset-cells" >> - "#iommu-cells" >> + - "#interconnect-cells" > > Rob, > > You were fine with adding a new required property which breaks all > existing DTBs? This is a required property for the new bindings and optional for the older. Does it really need to be made optional in the binding? > Were these bindings marked as unstable? The patchset does not even > say/scream that it breaks the ABI, so this might be quite a surprise for > someone... Please see tegra_mc_interconnect_setup() in "memory: tegra-mc: Add interconnect framework" patch, which check presence of the new ICC DT property.