From: "Yu-Chun Lin [林祐君]" <eleanor.lin@realtek.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: "mturquette@baylibre.com" <mturquette@baylibre.com>,
"sboyd@kernel.org" <sboyd@kernel.org>,
"robh@kernel.org" <robh@kernel.org>,
"krzk+dt@kernel.org" <krzk+dt@kernel.org>,
"conor+dt@kernel.org" <conor+dt@kernel.org>,
"p.zabel@pengutronix.de" <p.zabel@pengutronix.de>,
"Edgar Lee [李承諭]" <cylee12@realtek.com>,
"afaerber@suse.com" <afaerber@suse.com>,
"Jyan Chou [周芷安]" <jyanchou@realtek.com>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-clk@vger.kernel.org" <linux-clk@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"linux-realtek-soc@lists.infradead.org"
<linux-realtek-soc@lists.infradead.org>,
"James Tai [戴志峰]" <james.tai@realtek.com>,
"CY_Huang[黃鉦晏]" <cy.huang@realtek.com>,
"Stanley Chang[昌育德]" <stanley_chang@realtek.com>
Subject: RE: [PATCH v4 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller
Date: Tue, 17 Mar 2026 01:57:24 +0000 [thread overview]
Message-ID: <77e88b72f99c4a709f6fbae57162b090@realtek.com> (raw)
In-Reply-To: <20260314-orange-foxhound-of-felicity-997667@quoll>
> On Fri, Mar 13, 2026 at 04:10:51PM +0800, Yu-Chun Lin wrote:
>> +#endif /* __DT_BINDINGS_RTK_CLOCK_RTD1625_H */
>> diff --git a/include/dt-bindings/reset/realtek,rtd1625.h
>> b/include/dt-bindings/reset/realtek,rtd1625.h
>> new file mode 100644
>> index 000000000000..e69b5ee14cc6
>> --- /dev/null
>> +++ b/include/dt-bindings/reset/realtek,rtd1625.h
>> @@ -0,0 +1,195 @@
>> +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
>> +/*
>> + * Copyright (C) 2025 Realtek Semiconductor Corp.
>> + */
>> +#ifndef __DT_BINDINGS_RTK_RESET_RTD1625_H #define
>> +__DT_BINDINGS_RTK_RESET_RTD1625_H
>> +
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET1 0
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET2 1
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET3 2
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET4 3
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET7 4
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET9 5
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET_BIST 6
>> +#define RTD1625_RSTN_REG_ID_DUMMY0 7
>> +#define RTD1625_RSTN_REG_ID_DUMMY1 8
>> +#define RTD1625_RSTN_REG_ID_DUMMY4 9
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET11 10
>> +#define RTD1625_RSTN_REG_ID_SOFT_RESET12 11
>> +
>> +#define _REG_ID(n) ((RTD1625_RSTN_REG_ID_ ## n) << 5)
>> +
>
> Not a binding.
>
>> +#define RTD1625_CRT_RSTN_MISC (_REG_ID(SOFT_RESET1) | 0)
>> +#define RTD1625_CRT_RSTN_DIP (_REG_ID(SOFT_RESET1) | 2)
>> +#define RTD1625_CRT_RSTN_GSPI (_REG_ID(SOFT_RESET1) | 4)
>
> None of these are really bindings. Register offsets is hardware data, not a
> binding.
>
> Drop all of this above and further - actually nothing in this header look like a
> binding, since you called these "REG".
>
> Best regards,
> Krzysztof
The defines in this header are NOT register offsets. They encode "Bank ID+ Bit
Position" for use in Device Tree.
Agreed, The naming with "REG_ID" is misleading. I will improve naming all reset
IDs in v5.
Best regards,
Yu-Chun
next prev parent reply other threads:[~2026-03-17 2:00 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-13 8:10 [PATCH v4 00/10] clk: realtek: Add RTD1625 Clock Support Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 01/10] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin
2026-03-14 9:16 ` Krzysztof Kozlowski
2026-03-17 1:57 ` Yu-Chun Lin [林祐君] [this message]
2026-03-17 7:14 ` Krzysztof Kozlowski
2026-03-17 14:13 ` Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 02/10] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 03/10] clk: realtek: Add basic reset support Yu-Chun Lin
2026-03-14 9:19 ` Krzysztof Kozlowski
2026-03-17 2:12 ` Yu-Chun Lin [林祐君]
2026-03-17 7:14 ` Krzysztof Kozlowski
2026-03-18 13:02 ` Philipp Zabel
2026-03-13 8:10 ` [PATCH v4 04/10] clk: realtek: Introduce a common probe() Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 05/10] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 06/10] clk: realtek: Add support for gate clock Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 07/10] clk: realtek: Add support for mux clock Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 08/10] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin
2026-03-13 8:10 ` [PATCH v4 09/10] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin
2026-03-13 8:11 ` [PATCH v4 10/10] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin
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