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Fri, 12 Jun 2026 00:52:50 -0700 (PDT) X-Received: by 2002:a05:6a00:35cc:b0:842:5634:3c1d with SMTP id d2e1a72fcca58-8434cdac1dbmr2028614b3a.19.1781250769717; Fri, 12 Jun 2026 00:52:49 -0700 (PDT) Received: from [192.168.1.8] ([122.164.81.0]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8434ac9df57sm1393519b3a.7.2026.06.12.00.52.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Jun 2026 00:52:49 -0700 (PDT) Message-ID: <787c6ee5-e7e0-4884-9efc-b7b4692f1877@oss.qualcomm.com> Date: Fri, 12 Jun 2026 13:22:44 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/2] phy: qcom: qmp-pcie: Add IPQ9650 PCIe PHY support To: Dmitry Baryshkov Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260602-ipq9650_pcie_phy-v1-0-d8c32a36dbd9@oss.qualcomm.com> <20260602-ipq9650_pcie_phy-v1-2-d8c32a36dbd9@oss.qualcomm.com> <56zkq7bwrt5smmmum6jckzrekkkqrych2gntx3obnrmamwumtv@espahwe6pc3v> <7def2ccd-0319-4f85-8275-73fd254d887d@oss.qualcomm.com> <602e893c-d346-486d-86b3-50d0f01990bf@oss.qualcomm.com> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Proofpoint-GUID: kF4IlFRAN6UfcTSeCmgkhUi-kWlCl20t X-Authority-Analysis: v=2.4 cv=c4abhx9l c=1 sm=1 tr=0 ts=6a2bbad2 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=DVNErGSwdtF8OHn2hLoakQ==:17 a=IkcTkHD0fZMA:10 a=FelO9ux0wxsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=EUspDBNiAAAA:8 a=xnaJPCCZ8mv5B4GoDGgA:9 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNjEyMDA2OSBTYWx0ZWRfX/ipCEf0DKjOr A83GXNeizejaNk9osQyRTIwTmvwTqOue0hHWdmjX+gfQitKtoJzs6FXRt0x8qwe+mya0biNxohm bHa5VrTWMKE87Gv1qudD2evePP68HjqZPtHBADxFW68b1yI9ZFg+ohgEGPfiYdt+KinsmQL+uGE Ho38du88ZBrx1ysdw3ziOOcdI3h1kN8tjLfZN9MV94gsBQbk13Epl5ARIdYsKTrQ2eU78tTE5H4 6gu3oZ7Oxc2C9paB2XBAjZLT2X3UsGgBIWvcFGAepleCJItvIigMgdbzxtt4/Hb1kCwONF66xvR bYvSdd+gglsWJ8g6NZWN+2C32+qgc9KXg799fpbRgEZWi2mSYRZ0iFyaaMEybXLMQrzTIa5VSBO rmaqaZv8MeqVDLmygmDYeTx9PUffZCEr1PMege5TW+e3rj11hz4Haq71Konk6Qo6pYAN77GYn5+ kRRWQFE+NjLPOW66VRA== X-Proofpoint-ORIG-GUID: kF4IlFRAN6UfcTSeCmgkhUi-kWlCl20t X-Proofpoint-Spam-Info: AW1haW4tMjYwNjEyMDA2OSBTYWx0ZWRfXzVpBb0sumW/z XzlLGxb8I7CAhWM7e8Gq6gfdosIPwBW95ITXSZ/IM4nAHAuTo2szKLe7gOUv3p/gOp4kScb/Y/F LuoC7MU5MOS4F6ocYU0h8DHXcn3Ix0s= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.125,FMLib:17.12.100.49 definitions=2026-06-12_01,2026-06-11_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 clxscore=1015 phishscore=0 priorityscore=1501 malwarescore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606040000 definitions=main-2606120069 On 6/12/2026 12:54 PM, Dmitry Baryshkov wrote: > On Fri, Jun 12, 2026 at 12:13:04PM +0530, Kathiravan Thirumoorthy wrote: >> On 6/12/2026 11:44 AM, Dmitry Baryshkov wrote: >>> On Fri, Jun 12, 2026 at 08:22:02AM +0530, Kathiravan Thirumoorthy wrote: >>>> On 6/12/2026 1:52 AM, Dmitry Baryshkov wrote: >>>>> On Tue, Jun 09, 2026 at 03:46:56PM +0530, Kathiravan Thirumoorthy wrote: >>>>>> On 6/8/2026 12:26 PM, Dmitry Baryshkov wrote: >>>>>>> On Tue, Jun 02, 2026 at 02:40:18PM +0530, Kathiravan Thirumoorthy wrote: >>>>>>>> The IPQ9650 platform has three Gen3 2-lane PCIe controllers and two Gen3 >>>>>>>> 1-lane PCIe controllers. The PHY instances also require the on-chip refgen >>>>>>>> supply. >>>>>>>> >>>>>>>> Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations, including the >>>>>>>> refgen regulator supply. >>>>>>>> >>>>>>>> Signed-off-by: Kathiravan Thirumoorthy >>>>>>>> --- >>>>>>>> drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 220 +++++++++++++++++++++++++++++++ >>>>>>>> 1 file changed, 220 insertions(+) >>>>>>>> >>>>>>>> @@ -3378,6 +3524,10 @@ static const char * const qmp_phy_vreg_l[] = { >>>>>>>> "vdda-phy", "vdda-pll", >>>>>>>> }; >>>>>>>> +static const char * const ipq9650_qmp_phy_vreg_l[] = { >>>>>>>> + "refgen", >>>>>>>> +}; >>>>>>> Now vdda-phy / vdda-pll supplies? >>>>>> Cross checked with HW team again. Along with refgen, there is a on-chip LDO >>>>>> which supplies fixed voltage to the PHYs. It is enabled upon system power on >>>>>> and no SW intervention is required. >>>>> What is it being powered by? MX? CX? >>>> It is driven by CX. >>> I assume that there is no CX collapse on IPQ9650? Is CX not scaling on >>> this chip. Please provide some details on the commit message. >> That's right. No CX collapse on IPQ9650. Let me rewrite the commit message >> as below. Hope its okay. >> >> -- >> >> Add support for the IPQ9650 platform, which includes three Gen3 x2 PCIe >> controllers and two Gen3 x1 PCIe controllers. The PHY instances require the >> on-chip refgen supply. >> >> Add the IPQ9650 Gen3 x1 and x2 QMP PCIe PHY configurations along with the >> refgen regulator supply. Note that an on-chip LDO, driven by the SoC CX, >> supplies the PHY voltages without requiring software control. Note that CX >> power collapse is not supported on IPQ9650. > ...neither CX power collapse nor rail scaling... > > LGTM. Thanks much. Have sent V2. Please have a look. > >