* [PATCH v4 0/6] media: qcom: camss: Add sc7280 support
@ 2024-10-30 10:53 Vikram Sharma
2024-10-30 10:53 ` [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma
` (6 more replies)
0 siblings, 7 replies; 16+ messages in thread
From: Vikram Sharma @ 2024-10-30 10:53 UTC (permalink / raw)
To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt,
conor+dt, akapatra, hariramp, andersson, konradybcio,
hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will
Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm,
devicetree, linux-kernel, kernel
SC7280 is a Qualcomm SoC. This series adds support to bring up the CSIPHY,
CSID, VFE/RDI interfaces in SC7280.
SC7280 provides
- 3 x VFE, 3 RDI per VFE
- 2 x VFE Lite, 4 RDI per VFE
- 3 x CSID
- 2 x CSID Lite
- 5 x CSI PHY
The changes are verified on SC7280 qcs6490-rb3gen2 board, with attached vision mezzanine
the base dts for qcs6490-rb3gen2 is:
https://lore.kernel.org/all/20231103184655.23555-1-quic_kbajaj@quicinc.com/
Changes in V4:
- V3 had 8 patches and V4 is reduced to 6.
- Removed [Patch v3 2/8] as binding change is not required for dtso.
- Removed [Patch v3 3/8] as the fix is already taken care in latest
kernel tip.
- Updated alignment for dtsi and dt-bindings.
- Adding qcs6490-rb3gen2-vision-mezzanine as overlay.
- Link to v3: https://lore.kernel.org/linux-arm-msm/20241011140932.1744124-1-quic_vikramsa@quicinc.com/
Changes in V3:
- Added missed subject line for cover letter of V2.
- Updated Alignment, indentation and properties order.
- edit commit text for [PATCH 02/10] and [PATCH 03/10].
- Refactor camss_link_entities.
- Removed camcc enablement changes as it already done.
- Link to v2: https://lore.kernel.org/linux-arm-msm/20240904-camss_on_sc7280_rb3gen2_vision_v2_patches-v1-0-b18ddcd7d9df@quicinc.com/
Changes in V2:
- Improved indentation/formatting.
- Removed _src clocks and misleading code comments.
- Added name fields for power domains and csid register offset in DTSI.
- Dropped minItems field from YAML file.
- Listed changes in alphabetical order.
- Updated description and commit text to reflect changes
- Changed the compatible string from imx412 to imx577.
- Added board-specific enablement changes in the newly created vision
board DTSI file.
- Fixed bug encountered during testing.
- Moved logically independent changes to a new/seprate patch.
- Removed cci0 as no sensor is on this port and MCLK2, which was a
copy-paste error from the RB5 board reference.
- Added power rails, referencing the RB5 board.
- Discarded Patch 5/6 completely (not required).
- Removed unused enums.
- Link to v1: https://lore.kernel.org/linux-arm-msm/20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com/
Suresh Vankadara (1):
media: qcom: camss: Add support for camss driver on SC7280
Vikram Sharma (5):
media: dt-bindings: media: camss: Add qcom,sc7280-camss binding
media: qcom: camss: Sort CAMSS version enums and compatible strings
media: qcom: camss: Restructure camss_link_entities
arm64: dts: qcom: sc7280: Add support for camss
arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision
mezzanine
.../bindings/media/qcom,sc7280-camss.yaml | 439 +++++++++++++++
arch/arm64/boot/dts/qcom/Makefile | 4 +
.../qcs6490-rb3gen2-vision-mezzanine.dtso | 73 +++
arch/arm64/boot/dts/qcom/sc7280.dtsi | 208 ++++++++
.../media/platform/qcom/camss/camss-csid.c | 1 -
.../qcom/camss/camss-csiphy-3ph-1-0.c | 13 +-
.../media/platform/qcom/camss/camss-csiphy.c | 5 +
.../media/platform/qcom/camss/camss-csiphy.h | 1 +
drivers/media/platform/qcom/camss/camss-vfe.c | 8 +-
drivers/media/platform/qcom/camss/camss.c | 500 ++++++++++++++++--
drivers/media/platform/qcom/camss/camss.h | 1 +
11 files changed, 1190 insertions(+), 63 deletions(-)
create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml
create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso
--
2.25.1
^ permalink raw reply [flat|nested] 16+ messages in thread* [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding 2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma @ 2024-10-30 10:53 ` Vikram Sharma 2024-10-30 11:10 ` Vladimir Zapolskiy 2024-11-01 10:09 ` Krzysztof Kozlowski 2024-10-30 10:53 ` [PATCH v4 2/6] media: qcom: camss: Sort CAMSS version enums and compatible strings Vikram Sharma ` (5 subsequent siblings) 6 siblings, 2 replies; 16+ messages in thread From: Vikram Sharma @ 2024-10-30 10:53 UTC (permalink / raw) To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel Add bindings for qcom,sc7280-camss to support the camera subsystem on the SC7280 platform. Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> --- .../bindings/media/qcom,sc7280-camss.yaml | 439 ++++++++++++++++++ 1 file changed, 439 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml new file mode 100644 index 000000000000..783a5366e32b --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml @@ -0,0 +1,439 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC7280 CAMSS ISP + +maintainers: + - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com> + - Hariram Purushothaman <hariramp@quicinc.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sc7280-camss + + clocks: + maxItems: 32 + + clock-names: + items: + - const: camnoc_axi + - const: csi0 + - const: csi1 + - const: csi2 + - const: csi3 + - const: csi4 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy4 + - const: csiphy4_timer + - const: gcc_camera_ahb + - const: gcc_camera_axi + - const: soc_ahb + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe2_axi + - const: vfe2 + - const: vfe2_cphy_rx + - const: vfe0_lite + - const: vfe0_lite_cphy_rx + - const: vfe1_lite + - const: vfe1_lite_cphy_rx + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0 + + interrupts: + maxItems: 15 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domains-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@2: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@3: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@4: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + port@5: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + + reg: + maxItems: 15 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite0 + - const: csid_lite1 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: csiphy4 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite0 + - const: vfe_lite1 + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + +required: + - clock-names + - clocks + - compatible + - interconnects + - interconnect-names + - interrupts + - interrupt-names + - iommus + - power-domains + - power-domains-names + - reg + - reg-names + - vdda-phy-supply + - vdda-pll-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,camcc-sc7280.h> + #include <dt-bindings/clock/qcom,gcc-sc7280.h> + #include <dt-bindings/interconnect/qcom,sc7280.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@acaf000 { + compatible = "qcom,sc7280-camss"; + + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_2_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + <&clock_camcc CAM_CC_CSIPHY0_CLK>, + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY1_CLK>, + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY2_CLK>, + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY3_CLK>, + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&clock_camcc CAM_CC_CSIPHY4_CLK>, + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_0_CLK>, + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_1_CLK>, + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>, + <&clock_camcc CAM_CC_IFE_2_CLK>, + <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_0_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_1_CLK>, + <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>; + + clock-names = "camnoc_axi", + "csi0", + "csi1", + "csi2", + "csi3", + "csi4", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe0_lite", + "vfe0_lite_cphy_rx", + "vfe1_lite", + "vfe1_lite_cphy_rx"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; + + interconnect-names = "ahb", "hf_0"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + iommus = <&apps_smmu 0x800 0x4e0>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domains-names = "ife0", "ife1", "ife2", "top"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0accf000 0x0 0x1000>, + <0x0 0x0ace0000 0x0 0x2000>, + <0x0 0x0ace2000 0x0 0x2000>, + <0x0 0x0ace4000 0x0 0x2000>, + <0x0 0x0ace6000 0x0 0x2000>, + <0x0 0x0ace8000 0x0 0x2000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0accb000 0x0 0x4000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding 2024-10-30 10:53 ` [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma @ 2024-10-30 11:10 ` Vladimir Zapolskiy 2024-11-01 10:09 ` Krzysztof Kozlowski 1 sibling, 0 replies; 16+ messages in thread From: Vladimir Zapolskiy @ 2024-10-30 11:10 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel Hi Vikram, On 10/30/24 12:53, Vikram Sharma wrote: > Add bindings for qcom,sc7280-camss to support the camera subsystem > on the SC7280 platform. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- <snip> > +required: > + - clock-names > + - clocks > + - compatible > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - power-domains-names > + - reg > + - reg-names > + - vdda-phy-supply > + - vdda-pll-supply These supplies shall be split into pad specific ones. > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,camcc-sc7280.h> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/interconnect/qcom,sc7280.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: camss@acaf000 { Unit address is not the first one from the list of addresses from, reg values nor it even in the list. I kindly suggest to sort the list of reg values in address increase order, this will immediately make visible problems of this type. > + compatible = "qcom,sc7280-camss"; > + > + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, > + <&clock_camcc CAM_CC_IFE_0_CSID_CLK>, > + <&clock_camcc CAM_CC_IFE_1_CSID_CLK>, > + <&clock_camcc CAM_CC_IFE_2_CSID_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_0_CSID_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_1_CSID_CLK>, > + <&clock_camcc CAM_CC_CSIPHY0_CLK>, > + <&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>, > + <&clock_camcc CAM_CC_CSIPHY1_CLK>, > + <&clock_camcc CAM_CC_CSI1PHYTIMER_CLK>, > + <&clock_camcc CAM_CC_CSIPHY2_CLK>, > + <&clock_camcc CAM_CC_CSI2PHYTIMER_CLK>, > + <&clock_camcc CAM_CC_CSIPHY3_CLK>, > + <&clock_camcc CAM_CC_CSI3PHYTIMER_CLK>, > + <&clock_camcc CAM_CC_CSIPHY4_CLK>, > + <&clock_camcc CAM_CC_CSI4PHYTIMER_CLK>, > + <&gcc GCC_CAMERA_AHB_CLK>, > + <&gcc GCC_CAMERA_HF_AXI_CLK>, > + <&clock_camcc CAM_CC_CPAS_AHB_CLK>, > + <&clock_camcc CAM_CC_IFE_0_AXI_CLK>, > + <&clock_camcc CAM_CC_IFE_0_CLK>, > + <&clock_camcc CAM_CC_IFE_0_CPHY_RX_CLK>, > + <&clock_camcc CAM_CC_IFE_1_AXI_CLK>, > + <&clock_camcc CAM_CC_IFE_1_CLK>, > + <&clock_camcc CAM_CC_IFE_1_CPHY_RX_CLK>, > + <&clock_camcc CAM_CC_IFE_2_AXI_CLK>, > + <&clock_camcc CAM_CC_IFE_2_CLK>, > + <&clock_camcc CAM_CC_IFE_2_CPHY_RX_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_0_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_1_CLK>, > + <&clock_camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>; > + > + clock-names = "camnoc_axi", > + "csi0", > + "csi1", > + "csi2", > + "csi3", > + "csi4", > + "csiphy0", > + "csiphy0_timer", > + "csiphy1", > + "csiphy1_timer", > + "csiphy2", > + "csiphy2_timer", > + "csiphy3", > + "csiphy3_timer", > + "csiphy4", > + "csiphy4_timer", > + "gcc_camera_ahb", > + "gcc_camera_axi", > + "soc_ahb", > + "vfe0_axi", > + "vfe0", > + "vfe0_cphy_rx", > + "vfe1_axi", > + "vfe1", > + "vfe1_cphy_rx", > + "vfe2_axi", > + "vfe2", > + "vfe2_cphy_rx", > + "vfe0_lite", > + "vfe0_lite_cphy_rx", > + "vfe1_lite", > + "vfe1_lite_cphy_rx"; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>, > + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; > + > + interconnect-names = "ahb", "hf_0"; > + > + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, > + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; > + > + interrupt-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; > + > + iommus = <&apps_smmu 0x800 0x4e0>; > + > + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, > + <&camcc CAM_CC_IFE_1_GDSC>, > + <&camcc CAM_CC_IFE_2_GDSC>, > + <&camcc CAM_CC_TITAN_TOP_GDSC>; > + > + power-domains-names = "ife0", "ife1", "ife2", "top"; > + > + reg = <0x0 0x0acb3000 0x0 0x1000>, > + <0x0 0x0acba000 0x0 0x1000>, > + <0x0 0x0acc1000 0x0 0x1000>, > + <0x0 0x0acc8000 0x0 0x1000>, > + <0x0 0x0accf000 0x0 0x1000>, > + <0x0 0x0ace0000 0x0 0x2000>, > + <0x0 0x0ace2000 0x0 0x2000>, > + <0x0 0x0ace4000 0x0 0x2000>, > + <0x0 0x0ace6000 0x0 0x2000>, > + <0x0 0x0ace8000 0x0 0x2000>, > + <0x0 0x0acaf000 0x0 0x4000>, > + <0x0 0x0acb6000 0x0 0x4000>, > + <0x0 0x0acbd000 0x0 0x4000>, > + <0x0 0x0acc4000 0x0 0x4000>, > + <0x0 0x0accb000 0x0 0x4000>; > + > + reg-names = "csid0", > + "csid1", > + "csid2", > + "csid_lite0", > + "csid_lite1", > + "csiphy0", > + "csiphy1", > + "csiphy2", > + "csiphy3", > + "csiphy4", > + "vfe0", > + "vfe1", > + "vfe2", > + "vfe_lite0", > + "vfe_lite1"; reg and reg-names properties come right after the compatible property. > + > + vdda-phy-supply = <&vreg_l10c_0p88>; > + vdda-pll-supply = <&vreg_l6b_1p2>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; -- Best wishes, Vladimir ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding 2024-10-30 10:53 ` [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma 2024-10-30 11:10 ` Vladimir Zapolskiy @ 2024-11-01 10:09 ` Krzysztof Kozlowski 1 sibling, 0 replies; 16+ messages in thread From: Krzysztof Kozlowski @ 2024-11-01 10:09 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel On 30/10/2024 11:53, Vikram Sharma wrote: > Add bindings for qcom,sc7280-camss to support the camera subsystem > on the SC7280 platform. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> Feedback given to one patch, applies to everything. Respond or implement the feedback from 2 months ago: https://lore.kernel.org/linux-arm-msm/b17ad6e0-a99b-46c9-89e6-df72773a0bd4@kernel.org/ > --- > .../bindings/media/qcom,sc7280-camss.yaml | 439 ++++++++++++++++++ > 1 file changed, 439 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > > diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > new file mode 100644 > index 000000000000..783a5366e32b > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > @@ -0,0 +1,439 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/qcom,sc7280-camss.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Qualcomm SC7280 CAMSS ISP > + > +maintainers: > + - Azam Sadiq Pasha Kapatrala Syed <akapatra@quicinc.com> > + - Hariram Purushothaman <hariramp@quicinc.com> > + > +description: > + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. > + > +properties: > + compatible: > + const: qcom,sc7280-camss > + > + clocks: > + maxItems: 32 > + > + clock-names: > + items: > + - const: camnoc_axi > + - const: csi0 > + - const: csi1 > + - const: csi2 > + - const: csi3 > + - const: csi4 > + - const: csiphy0 > + - const: csiphy0_timer > + - const: csiphy1 > + - const: csiphy1_timer > + - const: csiphy2 > + - const: csiphy2_timer > + - const: csiphy3 > + - const: csiphy3_timer > + - const: csiphy4 > + - const: csiphy4_timer > + - const: gcc_camera_ahb > + - const: gcc_camera_axi > + - const: soc_ahb > + - const: vfe0_axi > + - const: vfe0 > + - const: vfe0_cphy_rx > + - const: vfe1_axi > + - const: vfe1 > + - const: vfe1_cphy_rx > + - const: vfe2_axi > + - const: vfe2 > + - const: vfe2_cphy_rx > + - const: vfe0_lite > + - const: vfe0_lite_cphy_rx > + - const: vfe1_lite > + - const: vfe1_lite_cphy_rx > + > + interconnects: > + maxItems: 2 > + > + interconnect-names: > + items: > + - const: ahb > + - const: hf_0 > + > + interrupts: > + maxItems: 15 > + > + interrupt-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + iommus: > + maxItems: 1 > + > + power-domains: > + items: > + - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller. > + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. > + > + power-domains-names: > + items: > + - const: ife0 > + - const: ife1 > + - const: ife2 > + - const: top > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + description: > + CSI input ports. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@1: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@2: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@3: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@4: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + port@5: > + $ref: /schemas/graph.yaml#/$defs/port-base > + unevaluatedProperties: false > + description: > + Input port for receiving CSI data. > + > + properties: > + endpoint: > + $ref: video-interfaces.yaml# > + unevaluatedProperties: false > + > + properties: > + data-lanes: > + minItems: 1 > + maxItems: 4 > + > + required: > + - data-lanes > + > + reg: > + maxItems: 15 > + > + reg-names: > + items: > + - const: csid0 > + - const: csid1 > + - const: csid2 > + - const: csid_lite0 > + - const: csid_lite1 > + - const: csiphy0 > + - const: csiphy1 > + - const: csiphy2 > + - const: csiphy3 > + - const: csiphy4 > + - const: vfe0 > + - const: vfe1 > + - const: vfe2 > + - const: vfe_lite0 > + - const: vfe_lite1 > + > + vdda-phy-supply: > + description: > + Phandle to a regulator supply to PHY core block. > + > + vdda-pll-supply: > + description: > + Phandle to 1.8V regulator supply to PHY refclk pll block. > + > +required: > + - clock-names > + - clocks > + - compatible > + - interconnects > + - interconnect-names > + - interrupts > + - interrupt-names > + - iommus > + - power-domains > + - power-domains-names > + - reg > + - reg-names > + - vdda-phy-supply > + - vdda-pll-supply > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,camcc-sc7280.h> > + #include <dt-bindings/clock/qcom,gcc-sc7280.h> > + #include <dt-bindings/interconnect/qcom,sc7280.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/power/qcom-rpmpd.h> > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + camss: camss@acaf000 { Drop unused label. > + compatible = "qcom,sc7280-camss"; > + > + clocks = <&clock_camcc CAM_CC_CAMNOC_AXI_CLK>, Last time feedback was: "Please carefully read DTS coding style." Before that, I asked to fix the order: https://lore.kernel.org/all/2m4dmdsivqwo45bxvuhashrlfki3akzzc3qp2vp32nrhvairyq@uibybei3fsco/ I don't think this improved. I think you just skimmed through DTS coding style without really double-checking your code. Sorry, repeating both feedbacks two or three times is not acceptable to me. NAK Best regards, Krzysztof ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 2/6] media: qcom: camss: Sort CAMSS version enums and compatible strings 2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma 2024-10-30 10:53 ` [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma @ 2024-10-30 10:53 ` Vikram Sharma 2024-10-30 10:53 ` [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma ` (4 subsequent siblings) 6 siblings, 0 replies; 16+ messages in thread From: Vikram Sharma @ 2024-10-30 10:53 UTC (permalink / raw) To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel Sort CAMSS version enums and compatible strings alphanumerically. Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> --- .../media/platform/qcom/camss/camss-csiphy-3ph-1-0.c | 10 +++++----- drivers/media/platform/qcom/camss/camss-vfe.c | 6 +++--- drivers/media/platform/qcom/camss/camss.c | 2 +- 3 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index df7e93a5a4f6..7d2490c9de01 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -505,10 +505,6 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u32 val; switch (csiphy->camss->res->version) { - case CAMSS_845: - r = &lane_regs_sdm845[0][0]; - array_size = ARRAY_SIZE(lane_regs_sdm845[0]); - break; case CAMSS_8250: r = &lane_regs_sm8250[0][0]; array_size = ARRAY_SIZE(lane_regs_sm8250[0]); @@ -517,6 +513,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, r = &lane_regs_sc8280xp[0][0]; array_size = ARRAY_SIZE(lane_regs_sc8280xp[0]); break; + case CAMSS_845: + r = &lane_regs_sdm845[0][0]; + array_size = ARRAY_SIZE(lane_regs_sdm845[0]); + break; default: WARN(1, "unknown cspi version\n"); return; @@ -557,9 +557,9 @@ static bool csiphy_is_gen2(u32 version) bool ret = false; switch (version) { - case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_845: ret = true; break; } diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index 83c5a36d071f..ffcb1e2ec417 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -333,11 +333,11 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, return sink_code; } break; - case CAMSS_8x96: case CAMSS_660: - case CAMSS_845: + case CAMSS_8x96: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_845: switch (sink_code) { case MEDIA_BUS_FMT_YUYV8_1X16: { @@ -1692,9 +1692,9 @@ static int vfe_bpl_align(struct vfe_device *vfe) int ret = 8; switch (vfe->camss->res->version) { - case CAMSS_845: case CAMSS_8250: case CAMSS_8280XP: + case CAMSS_845: ret = 16; break; default: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index fabe034081ed..e8cd8afe7bee 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2456,10 +2456,10 @@ static const struct camss_resources sc8280xp_resources = { static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, + { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, { .compatible = "qcom,sm8250-camss", .data = &sm8250_resources }, - { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { } }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma 2024-10-30 10:53 ` [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma 2024-10-30 10:53 ` [PATCH v4 2/6] media: qcom: camss: Sort CAMSS version enums and compatible strings Vikram Sharma @ 2024-10-30 10:53 ` Vikram Sharma 2024-10-30 11:15 ` Vladimir Zapolskiy 2024-10-31 17:58 ` Bryan O'Donoghue 2024-10-30 10:53 ` [PATCH v4 4/6] media: qcom: camss: Restructure camss_link_entities Vikram Sharma ` (3 subsequent siblings) 6 siblings, 2 replies; 16+ messages in thread From: Vikram Sharma @ 2024-10-30 10:53 UTC (permalink / raw) To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel From: Suresh Vankadara <quic_svankada@quicinc.com> Add support for the camss driver on the SC7280 SoC. Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> --- .../media/platform/qcom/camss/camss-csid.c | 1 - .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 + .../media/platform/qcom/camss/camss-csiphy.c | 5 + .../media/platform/qcom/camss/camss-csiphy.h | 1 + drivers/media/platform/qcom/camss/camss-vfe.c | 2 + drivers/media/platform/qcom/camss/camss.c | 339 ++++++++++++++++++ drivers/media/platform/qcom/camss/camss.h | 1 + 7 files changed, 353 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c index 858db5d4ca75..8d3dc26e2af4 100644 --- a/drivers/media/platform/qcom/camss/camss-csid.c +++ b/drivers/media/platform/qcom/camss/camss-csid.c @@ -1028,7 +1028,6 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, csid->res->hw_ops->subdev_init(csid); /* Memory */ - if (camss->res->version == CAMSS_8250) { /* for titan 480, CSID registers are inside the VFE region, * between the VFE "top" and "bus" registers. this requires diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c index 7d2490c9de01..f341f7b7fd8a 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, u32 val; switch (csiphy->camss->res->version) { + case CAMSS_7280: + r = &lane_regs_sm8250[0][0]; + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); + break; case CAMSS_8250: r = &lane_regs_sm8250[0][0]; array_size = ARRAY_SIZE(lane_regs_sm8250[0]); @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) bool ret = false; switch (version) { + case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: case CAMSS_845: diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c index 68a3ea1ba2a5..9722cee4143f 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.c +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c @@ -108,6 +108,11 @@ const struct csiphy_formats csiphy_formats_sdm845 = { .formats = formats_sdm845 }; +const struct csiphy_formats csiphy_formats_sc7280 = { + .nformats = ARRAY_SIZE(formats_sdm845), + .formats = formats_sdm845 +}; + /* * csiphy_get_bpp - map media bus format to bits per pixel * @formats: supported media bus formats array diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h index eebc1ff1cfab..67a96ef55bb6 100644 --- a/drivers/media/platform/qcom/camss/camss-csiphy.h +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h @@ -112,6 +112,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); extern const struct csiphy_formats csiphy_formats_8x16; extern const struct csiphy_formats csiphy_formats_8x96; extern const struct csiphy_formats csiphy_formats_sdm845; +extern const struct csiphy_formats csiphy_formats_sc7280; extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0; extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0; diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c index ffcb1e2ec417..61f6815a3756 100644 --- a/drivers/media/platform/qcom/camss/camss-vfe.c +++ b/drivers/media/platform/qcom/camss/camss-vfe.c @@ -334,6 +334,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, } break; case CAMSS_660: + case CAMSS_7280: case CAMSS_8x96: case CAMSS_8250: case CAMSS_8280XP: @@ -1692,6 +1693,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) int ret = 8; switch (vfe->camss->res->version) { + case CAMSS_7280: case CAMSS_8250: case CAMSS_8280XP: case CAMSS_845: diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index e8cd8afe7bee..addaed8f77cb 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1480,6 +1480,330 @@ static const struct resources_icc icc_res_sc8280xp[] = { }, }; +static const struct camss_subdev_resources csiphy_res_7280[] = { + /* CSIPHY0 */ + { + .regulators = {}, + .clock = { "csiphy0", "csiphy0_timer"}, + .clock_rate = { + { 300000000 }, + { 300000000 } + }, + .reg = { "csiphy0" }, + .interrupt = { "csiphy0" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sc7280 + } + }, + /* CSIPHY1 */ + { + .regulators = {}, + .clock = { "csiphy1", "csiphy1_timer"}, + .clock_rate = { + { 300000000 }, + { 300000000 } + }, + .reg = { "csiphy1" }, + .interrupt = { "csiphy1" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sc7280 + } + }, + /* CSIPHY2 */ + { + .regulators = {}, + .clock = { "csiphy2", "csiphy2_timer"}, + .clock_rate = { + { 300000000 }, + { 300000000 } + }, + .reg = { "csiphy2" }, + .interrupt = { "csiphy2" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sc7280 + } + }, + /* CSIPHY3 */ + { + .regulators = {}, + .clock = { "csiphy3", "csiphy3_timer"}, + .clock_rate = { + { 300000000 }, + { 300000000 } + }, + .reg = { "csiphy3" }, + .interrupt = { "csiphy3" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sc7280 + } + }, + /* CSIPHY4 */ + { + .regulators = {}, + .clock = { "csiphy4", "csiphy4_timer"}, + .clock_rate = { + { 300000000 }, + { 300000000 } + }, + .reg = { "csiphy4" }, + .interrupt = { "csiphy4" }, + .csiphy = { + .hw_ops = &csiphy_ops_3ph_1_0, + .formats = &csiphy_formats_sc7280 + } + }, +}; + +static const struct camss_subdev_resources csid_res_7280[] = { + /* CSID0 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + + .clock = { "csi0", "vfe0_cphy_rx", "vfe0", "soc_ahb"}, + .clock_rate = { + { 300000000, 0, 380000000, 0}, + { 400000000, 0, 510000000, 0}, + { 400000000, 0, 637000000, 0}, + { 400000000, 0, 760000000, 0} + }, + + .reg = { "csid0" }, + .interrupt = { "csid0" }, + .csid = { + .is_lite = false, + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + }, + /* CSID1 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + + .clock = { "csi1", "vfe1_cphy_rx", "vfe1", "soc_ahb"}, + .clock_rate = { + { 300000000, 0, 380000000, 0}, + { 400000000, 0, 510000000, 0}, + { 400000000, 0, 637000000, 0}, + { 400000000, 0, 760000000, 0} + }, + + .reg = { "csid1" }, + .interrupt = { "csid1" }, + .csid = { + .is_lite = false, + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + }, + /* CSID2 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + + .clock = { "csi2", "vfe2_cphy_rx", "vfe2", "soc_ahb"}, + .clock_rate = { + { 300000000, 0, 380000000, 0}, + { 400000000, 0, 510000000, 0}, + { 400000000, 0, 637000000, 0}, + { 400000000, 0, 760000000, 0} + }, + + .reg = { "csid2" }, + .interrupt = { "csid2" }, + .csid = { + .is_lite = false, + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + }, + /* CSID3 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + + .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, + .clock_rate = { + { 300000000, 0, 320000000, 0}, + { 400000000, 0, 400000000, 0}, + { 400000000, 0, 480000000, 0}, + { 400000000, 0, 600000000, 0} + }, + + .reg = { "csid_lite0" }, + .interrupt = { "csid_lite0" }, + .csid = { + .is_lite = true, + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + }, + /* CSID4 */ + { + .regulators = { "vdda-phy", "vdda-pll" }, + + .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, + .clock_rate = { + { 300000000, 0, 320000000, 0}, + { 400000000, 0, 400000000, 0}, + { 400000000, 0, 480000000, 0}, + { 400000000, 0, 600000000, 0} + }, + + .reg = { "csid_lite1" }, + .interrupt = { "csid_lite1" }, + .csid = { + .is_lite = true, + .hw_ops = &csid_ops_gen2, + .parent_dev_ops = &vfe_parent_dev_ops, + .formats = &csid_formats_gen2 + } + }, +}; + +static const struct camss_subdev_resources vfe_res_7280[] = { + /* VFE0 */ + { + .regulators = {}, + + .clock = { "vfe0", "vfe0_axi", "soc_ahb", + "camnoc_axi", "gcc_camera_axi"}, + .clock_rate = { + { 380000000, 0, 80000000, 150000000, 0}, + { 510000000, 0, 80000000, 240000000, 0}, + { 637000000, 0, 80000000, 320000000, 0}, + { 760000000, 0, 80000000, 400000000, 0}, + { 760000000, 0, 80000000, 480000000, 0}, + }, + + .reg = { "vfe0" }, + .interrupt = { "vfe0" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .has_pd = true, + .pd_name = "ife0", + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE1 */ + { + .regulators = {}, + + .clock = { "vfe1", "vfe1_axi", "soc_ahb", + "camnoc_axi", "gcc_camera_axi"}, + .clock_rate = { + { 380000000, 0, 80000000, 150000000, 0}, + { 510000000, 0, 80000000, 240000000, 0}, + { 637000000, 0, 80000000, 320000000, 0}, + { 760000000, 0, 80000000, 400000000, 0}, + { 760000000, 0, 80000000, 480000000, 0}, + }, + + .reg = { "vfe1" }, + .interrupt = { "vfe1" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .has_pd = true, + .pd_name = "ife1", + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE2 */ + { + .regulators = {}, + + .clock = { "vfe2", "vfe2_axi", "soc_ahb", + "camnoc_axi", "gcc_camera_axi"}, + .clock_rate = { + { 380000000, 0, 80000000, 150000000, 0}, + { 510000000, 0, 80000000, 240000000, 0}, + { 637000000, 0, 80000000, 320000000, 0}, + { 760000000, 0, 80000000, 400000000, 0}, + { 760000000, 0, 80000000, 480000000, 0}, + }, + + .reg = { "vfe2" }, + .interrupt = { "vfe2" }, + .vfe = { + .line_num = 3, + .is_lite = false, + .hw_ops = &vfe_ops_170, + .has_pd = true, + .pd_name = "ife2", + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE3 (lite) */ + { + .clock = { "vfe0_lite", "soc_ahb", + "camnoc_axi", "gcc_camera_axi"}, + .clock_rate = { + { 320000000, 80000000, 150000000, 0}, + { 400000000, 80000000, 240000000, 0}, + { 480000000, 80000000, 320000000, 0}, + { 600000000, 80000000, 400000000, 0}, + }, + + .regulators = {}, + .reg = { "vfe_lite0" }, + .interrupt = { "vfe_lite0" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, + /* VFE4 (lite) */ + { + .clock = { "vfe1_lite", "soc_ahb", + "camnoc_axi", "gcc_camera_axi"}, + .clock_rate = { + { 320000000, 80000000, 150000000, 0}, + { 400000000, 80000000, 240000000, 0}, + { 480000000, 80000000, 320000000, 0}, + { 600000000, 80000000, 400000000, 0}, + }, + + .regulators = {}, + .reg = { "vfe_lite1" }, + .interrupt = { "vfe_lite1" }, + .vfe = { + .line_num = 4, + .is_lite = true, + .hw_ops = &vfe_ops_170, + .formats_rdi = &vfe_formats_rdi_845, + .formats_pix = &vfe_formats_pix_845 + } + }, +}; + +static const struct resources_icc icc_res_sc7280[] = { + { + .name = "ahb", + .icc_bw_tbl.avg = 38400, + .icc_bw_tbl.peak = 76800, + }, + { + .name = "hf_0", + .icc_bw_tbl.avg = 2097152, + .icc_bw_tbl.peak = 2097152, + }, +}; + /* * camss_add_clock_margin - Add margin to clock frequency rate * @rate: Clock frequency rate @@ -2453,9 +2777,24 @@ static const struct camss_resources sc8280xp_resources = { .link_entities = camss_link_entities }; +static const struct camss_resources sc7280_resources = { + .version = CAMSS_7280, + .pd_name = "top", + .csiphy_res = csiphy_res_7280, + .csid_res = csid_res_7280, + .vfe_res = vfe_res_7280, + .icc_res = icc_res_sc7280, + .icc_path_num = ARRAY_SIZE(icc_res_sc7280), + .csiphy_num = ARRAY_SIZE(csiphy_res_7280), + .csid_num = ARRAY_SIZE(csid_res_7280), + .vfe_num = ARRAY_SIZE(vfe_res_7280), + .link_entities = camss_link_entities +}; + static const struct of_device_id camss_dt_match[] = { { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources }, { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h index 0ce84fcbbd25..bbdf9aa81c36 100644 --- a/drivers/media/platform/qcom/camss/camss.h +++ b/drivers/media/platform/qcom/camss/camss.h @@ -80,6 +80,7 @@ enum camss_version { CAMSS_8x16, CAMSS_8x96, CAMSS_660, + CAMSS_7280, CAMSS_845, CAMSS_8250, CAMSS_8280XP, -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 2024-10-30 10:53 ` [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma @ 2024-10-30 11:15 ` Vladimir Zapolskiy 2024-10-31 17:58 ` Bryan O'Donoghue 1 sibling, 0 replies; 16+ messages in thread From: Vladimir Zapolskiy @ 2024-10-30 11:15 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel On 10/30/24 12:53, Vikram Sharma wrote: > From: Suresh Vankadara <quic_svankada@quicinc.com> > > Add support for the camss driver on the SC7280 SoC. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > .../media/platform/qcom/camss/camss-csid.c | 1 - > .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.h | 1 + > drivers/media/platform/qcom/camss/camss-vfe.c | 2 + > drivers/media/platform/qcom/camss/camss.c | 339 ++++++++++++++++++ > drivers/media/platform/qcom/camss/camss.h | 1 + > 7 files changed, 353 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c > index 858db5d4ca75..8d3dc26e2af4 100644 > --- a/drivers/media/platform/qcom/camss/camss-csid.c > +++ b/drivers/media/platform/qcom/camss/camss-csid.c > @@ -1028,7 +1028,6 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, > csid->res->hw_ops->subdev_init(csid); > > /* Memory */ > - > if (camss->res->version == CAMSS_8250) { > /* for titan 480, CSID registers are inside the VFE region, > * between the VFE "top" and "bus" registers. this requires > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 7d2490c9de01..f341f7b7fd8a 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, > u32 val; > > switch (csiphy->camss->res->version) { > + case CAMSS_7280: > + r = &lane_regs_sm8250[0][0]; > + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > + break; > case CAMSS_8250: > r = &lane_regs_sm8250[0][0]; > array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) > bool ret = false; > > switch (version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c > index 68a3ea1ba2a5..9722cee4143f 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c > @@ -108,6 +108,11 @@ const struct csiphy_formats csiphy_formats_sdm845 = { > .formats = formats_sdm845 > }; > > +const struct csiphy_formats csiphy_formats_sc7280 = { > + .nformats = ARRAY_SIZE(formats_sdm845), > + .formats = formats_sdm845 > +}; > + Since you are picky about alphabetical sorting, you may need to keep it here as well. > /* > * csiphy_get_bpp - map media bus format to bits per pixel > * @formats: supported media bus formats array > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h > index eebc1ff1cfab..67a96ef55bb6 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.h > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h > @@ -112,6 +112,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); > extern const struct csiphy_formats csiphy_formats_8x16; > extern const struct csiphy_formats csiphy_formats_8x96; > extern const struct csiphy_formats csiphy_formats_sdm845; > +extern const struct csiphy_formats csiphy_formats_sc7280; Same comment as above. > > extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0; > extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0; > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c > index ffcb1e2ec417..61f6815a3756 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.c > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c > @@ -334,6 +334,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, > } > break; > case CAMSS_660: > + case CAMSS_7280: > case CAMSS_8x96: > case CAMSS_8250: > case CAMSS_8280XP: > @@ -1692,6 +1693,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) > int ret = 8; > > switch (vfe->camss->res->version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index e8cd8afe7bee..addaed8f77cb 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -1480,6 +1480,330 @@ static const struct resources_icc icc_res_sc8280xp[] = { > }, > }; > > +static const struct camss_subdev_resources csiphy_res_7280[] = { Same comment as above. > + /* CSIPHY0 */ > + { > + .regulators = {}, > + .clock = { "csiphy0", "csiphy0_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy0" }, > + .interrupt = { "csiphy0" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY1 */ > + { > + .regulators = {}, > + .clock = { "csiphy1", "csiphy1_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy1" }, > + .interrupt = { "csiphy1" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY2 */ > + { > + .regulators = {}, > + .clock = { "csiphy2", "csiphy2_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy2" }, > + .interrupt = { "csiphy2" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY3 */ > + { > + .regulators = {}, > + .clock = { "csiphy3", "csiphy3_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy3" }, > + .interrupt = { "csiphy3" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY4 */ > + { > + .regulators = {}, > + .clock = { "csiphy4", "csiphy4_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy4" }, > + .interrupt = { "csiphy4" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > +}; > + > +static const struct camss_subdev_resources csid_res_7280[] = { > + /* CSID0 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, Supply regulators shall be properties of CSIPHY IP and its representation in the driver. > + > + .clock = { "csi0", "vfe0_cphy_rx", "vfe0", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid0" }, > + .interrupt = { "csid0" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID1 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi1", "vfe1_cphy_rx", "vfe1", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid1" }, > + .interrupt = { "csid1" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID2 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi2", "vfe2_cphy_rx", "vfe2", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid2" }, > + .interrupt = { "csid2" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID3 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 320000000, 0}, > + { 400000000, 0, 400000000, 0}, > + { 400000000, 0, 480000000, 0}, > + { 400000000, 0, 600000000, 0} > + }, > + > + .reg = { "csid_lite0" }, > + .interrupt = { "csid_lite0" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID4 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 320000000, 0}, > + { 400000000, 0, 400000000, 0}, > + { 400000000, 0, 480000000, 0}, > + { 400000000, 0, 600000000, 0} > + }, > + > + .reg = { "csid_lite1" }, > + .interrupt = { "csid_lite1" }, > + .csid = { > + .is_lite = true, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > +}; > + > +static const struct camss_subdev_resources vfe_res_7280[] = { > + /* VFE0 */ > + { > + .regulators = {}, > + > + .clock = { "vfe0", "vfe0_axi", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 380000000, 0, 80000000, 150000000, 0}, > + { 510000000, 0, 80000000, 240000000, 0}, > + { 637000000, 0, 80000000, 320000000, 0}, > + { 760000000, 0, 80000000, 400000000, 0}, > + { 760000000, 0, 80000000, 480000000, 0}, > + }, > + > + .reg = { "vfe0" }, > + .interrupt = { "vfe0" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife0", > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE1 */ > + { > + .regulators = {}, > + > + .clock = { "vfe1", "vfe1_axi", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 380000000, 0, 80000000, 150000000, 0}, > + { 510000000, 0, 80000000, 240000000, 0}, > + { 637000000, 0, 80000000, 320000000, 0}, > + { 760000000, 0, 80000000, 400000000, 0}, > + { 760000000, 0, 80000000, 480000000, 0}, > + }, > + > + .reg = { "vfe1" }, > + .interrupt = { "vfe1" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .has_pd = true, > + .pd_name = "ife1", > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE2 */ > + { > + .regulators = {}, > + > + .clock = { "vfe2", "vfe2_axi", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 380000000, 0, 80000000, 150000000, 0}, > + { 510000000, 0, 80000000, 240000000, 0}, > + { 637000000, 0, 80000000, 320000000, 0}, > + { 760000000, 0, 80000000, 400000000, 0}, > + { 760000000, 0, 80000000, 480000000, 0}, > + }, > + > + .reg = { "vfe2" }, > + .interrupt = { "vfe2" }, > + .vfe = { > + .line_num = 3, > + .is_lite = false, > + .hw_ops = &vfe_ops_170, > + .has_pd = true, > + .pd_name = "ife2", > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE3 (lite) */ > + { > + .clock = { "vfe0_lite", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 320000000, 80000000, 150000000, 0}, > + { 400000000, 80000000, 240000000, 0}, > + { 480000000, 80000000, 320000000, 0}, > + { 600000000, 80000000, 400000000, 0}, > + }, > + > + .regulators = {}, > + .reg = { "vfe_lite0" }, > + .interrupt = { "vfe_lite0" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > + /* VFE4 (lite) */ > + { > + .clock = { "vfe1_lite", "soc_ahb", > + "camnoc_axi", "gcc_camera_axi"}, > + .clock_rate = { > + { 320000000, 80000000, 150000000, 0}, > + { 400000000, 80000000, 240000000, 0}, > + { 480000000, 80000000, 320000000, 0}, > + { 600000000, 80000000, 400000000, 0}, > + }, > + > + .regulators = {}, > + .reg = { "vfe_lite1" }, > + .interrupt = { "vfe_lite1" }, > + .vfe = { > + .line_num = 4, > + .is_lite = true, > + .hw_ops = &vfe_ops_170, > + .formats_rdi = &vfe_formats_rdi_845, > + .formats_pix = &vfe_formats_pix_845 > + } > + }, > +}; > + > +static const struct resources_icc icc_res_sc7280[] = { > + { > + .name = "ahb", > + .icc_bw_tbl.avg = 38400, > + .icc_bw_tbl.peak = 76800, > + }, > + { > + .name = "hf_0", > + .icc_bw_tbl.avg = 2097152, > + .icc_bw_tbl.peak = 2097152, > + }, > +}; > + > /* > * camss_add_clock_margin - Add margin to clock frequency rate > * @rate: Clock frequency rate > @@ -2453,9 +2777,24 @@ static const struct camss_resources sc8280xp_resources = { > .link_entities = camss_link_entities > }; > > +static const struct camss_resources sc7280_resources = { > + .version = CAMSS_7280, > + .pd_name = "top", > + .csiphy_res = csiphy_res_7280, > + .csid_res = csid_res_7280, > + .vfe_res = vfe_res_7280, > + .icc_res = icc_res_sc7280, > + .icc_path_num = ARRAY_SIZE(icc_res_sc7280), > + .csiphy_num = ARRAY_SIZE(csiphy_res_7280), > + .csid_num = ARRAY_SIZE(csid_res_7280), > + .vfe_num = ARRAY_SIZE(vfe_res_7280), > + .link_entities = camss_link_entities > +}; > + > static const struct of_device_id camss_dt_match[] = { > { .compatible = "qcom,msm8916-camss", .data = &msm8916_resources }, > { .compatible = "qcom,msm8996-camss", .data = &msm8996_resources }, > + { .compatible = "qcom,sc7280-camss", .data = &sc7280_resources }, > { .compatible = "qcom,sc8280xp-camss", .data = &sc8280xp_resources }, > { .compatible = "qcom,sdm660-camss", .data = &sdm660_resources }, > { .compatible = "qcom,sdm845-camss", .data = &sdm845_resources }, > diff --git a/drivers/media/platform/qcom/camss/camss.h b/drivers/media/platform/qcom/camss/camss.h > index 0ce84fcbbd25..bbdf9aa81c36 100644 > --- a/drivers/media/platform/qcom/camss/camss.h > +++ b/drivers/media/platform/qcom/camss/camss.h > @@ -80,6 +80,7 @@ enum camss_version { > CAMSS_8x16, > CAMSS_8x96, > CAMSS_660, > + CAMSS_7280, > CAMSS_845, > CAMSS_8250, > CAMSS_8280XP, -- Best wishes, Vladimir ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 2024-10-30 10:53 ` [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma 2024-10-30 11:15 ` Vladimir Zapolskiy @ 2024-10-31 17:58 ` Bryan O'Donoghue 1 sibling, 0 replies; 16+ messages in thread From: Bryan O'Donoghue @ 2024-10-31 17:58 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel On 30/10/2024 10:53, Vikram Sharma wrote: > From: Suresh Vankadara <quic_svankada@quicinc.com> > > Add support for the camss driver on the SC7280 SoC. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > .../media/platform/qcom/camss/camss-csid.c | 1 - > .../qcom/camss/camss-csiphy-3ph-1-0.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.h | 1 + > drivers/media/platform/qcom/camss/camss-vfe.c | 2 + > drivers/media/platform/qcom/camss/camss.c | 339 ++++++++++++++++++ > drivers/media/platform/qcom/camss/camss.h | 1 + > 7 files changed, 353 insertions(+), 1 deletion(-) > > diff --git a/drivers/media/platform/qcom/camss/camss-csid.c b/drivers/media/platform/qcom/camss/camss-csid.c > index 858db5d4ca75..8d3dc26e2af4 100644 > --- a/drivers/media/platform/qcom/camss/camss-csid.c > +++ b/drivers/media/platform/qcom/camss/camss-csid.c > @@ -1028,7 +1028,6 @@ int msm_csid_subdev_init(struct camss *camss, struct csid_device *csid, > csid->res->hw_ops->subdev_init(csid); > > /* Memory */ > - Extraneous deletion. > if (camss->res->version == CAMSS_8250) { > /* for titan 480, CSID registers are inside the VFE region, > * between the VFE "top" and "bus" registers. this requires > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > index 7d2490c9de01..f341f7b7fd8a 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c > @@ -505,6 +505,10 @@ static void csiphy_gen2_config_lanes(struct csiphy_device *csiphy, > u32 val; > > switch (csiphy->camss->res->version) { > + case CAMSS_7280: > + r = &lane_regs_sm8250[0][0]; > + array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > + break; > case CAMSS_8250: > r = &lane_regs_sm8250[0][0]; > array_size = ARRAY_SIZE(lane_regs_sm8250[0]); > @@ -557,6 +561,7 @@ static bool csiphy_is_gen2(u32 version) > bool ret = false; > > switch (version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.c b/drivers/media/platform/qcom/camss/camss-csiphy.c > index 68a3ea1ba2a5..9722cee4143f 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.c > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.c > @@ -108,6 +108,11 @@ const struct csiphy_formats csiphy_formats_sdm845 = { > .formats = formats_sdm845 > }; > > +const struct csiphy_formats csiphy_formats_sc7280 = { > + .nformats = ARRAY_SIZE(formats_sdm845), > + .formats = formats_sdm845 > +}; > + > /* > * csiphy_get_bpp - map media bus format to bits per pixel > * @formats: supported media bus formats array > diff --git a/drivers/media/platform/qcom/camss/camss-csiphy.h b/drivers/media/platform/qcom/camss/camss-csiphy.h > index eebc1ff1cfab..67a96ef55bb6 100644 > --- a/drivers/media/platform/qcom/camss/camss-csiphy.h > +++ b/drivers/media/platform/qcom/camss/camss-csiphy.h > @@ -112,6 +112,7 @@ void msm_csiphy_unregister_entity(struct csiphy_device *csiphy); > extern const struct csiphy_formats csiphy_formats_8x16; > extern const struct csiphy_formats csiphy_formats_8x96; > extern const struct csiphy_formats csiphy_formats_sdm845; > +extern const struct csiphy_formats csiphy_formats_sc7280; > > extern const struct csiphy_hw_ops csiphy_ops_2ph_1_0; > extern const struct csiphy_hw_ops csiphy_ops_3ph_1_0; > diff --git a/drivers/media/platform/qcom/camss/camss-vfe.c b/drivers/media/platform/qcom/camss/camss-vfe.c > index ffcb1e2ec417..61f6815a3756 100644 > --- a/drivers/media/platform/qcom/camss/camss-vfe.c > +++ b/drivers/media/platform/qcom/camss/camss-vfe.c > @@ -334,6 +334,7 @@ static u32 vfe_src_pad_code(struct vfe_line *line, u32 sink_code, > } > break; > case CAMSS_660: > + case CAMSS_7280: > case CAMSS_8x96: > case CAMSS_8250: > case CAMSS_8280XP: > @@ -1692,6 +1693,7 @@ static int vfe_bpl_align(struct vfe_device *vfe) > int ret = 8; > > switch (vfe->camss->res->version) { > + case CAMSS_7280: > case CAMSS_8250: > case CAMSS_8280XP: > case CAMSS_845: > diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c > index e8cd8afe7bee..addaed8f77cb 100644 > --- a/drivers/media/platform/qcom/camss/camss.c > +++ b/drivers/media/platform/qcom/camss/camss.c > @@ -1480,6 +1480,330 @@ static const struct resources_icc icc_res_sc8280xp[] = { > }, > }; > > +static const struct camss_subdev_resources csiphy_res_7280[] = { > + /* CSIPHY0 */ > + { > + .regulators = {}, > + .clock = { "csiphy0", "csiphy0_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy0" }, > + .interrupt = { "csiphy0" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY1 */ > + { > + .regulators = {}, > + .clock = { "csiphy1", "csiphy1_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy1" }, > + .interrupt = { "csiphy1" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY2 */ > + { > + .regulators = {}, > + .clock = { "csiphy2", "csiphy2_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy2" }, > + .interrupt = { "csiphy2" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY3 */ > + { > + .regulators = {}, > + .clock = { "csiphy3", "csiphy3_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy3" }, > + .interrupt = { "csiphy3" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > + /* CSIPHY4 */ > + { > + .regulators = {}, > + .clock = { "csiphy4", "csiphy4_timer"}, > + .clock_rate = { > + { 300000000 }, > + { 300000000 } > + }, > + .reg = { "csiphy4" }, > + .interrupt = { "csiphy4" }, > + .csiphy = { > + .hw_ops = &csiphy_ops_3ph_1_0, > + .formats = &csiphy_formats_sc7280 > + } > + }, > +}; > + > +static const struct camss_subdev_resources csid_res_7280[] = { > + /* CSID0 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi0", "vfe0_cphy_rx", "vfe0", "soc_ahb"}, csi0 should probably be named vfe0_csid, same with the other csiX clocks here. 7280 is similar/derived from 8250 so the naming convention should be followed. > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid0" }, > + .interrupt = { "csid0" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID1 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi1", "vfe1_cphy_rx", "vfe1", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid1" }, > + .interrupt = { "csid1" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID2 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi2", "vfe2_cphy_rx", "vfe2", "soc_ahb"}, > + .clock_rate = { > + { 300000000, 0, 380000000, 0}, > + { 400000000, 0, 510000000, 0}, > + { 400000000, 0, 637000000, 0}, > + { 400000000, 0, 760000000, 0} > + }, > + > + .reg = { "csid2" }, > + .interrupt = { "csid2" }, > + .csid = { > + .is_lite = false, > + .hw_ops = &csid_ops_gen2, > + .parent_dev_ops = &vfe_parent_dev_ops, > + .formats = &csid_formats_gen2 > + } > + }, > + /* CSID3 */ > + { > + .regulators = { "vdda-phy", "vdda-pll" }, > + > + .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, As with 8250 I'd expect "lite" to appear in the clock name When fixed please add. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> --- bod ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 4/6] media: qcom: camss: Restructure camss_link_entities 2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma ` (2 preceding siblings ...) 2024-10-30 10:53 ` [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma @ 2024-10-30 10:53 ` Vikram Sharma 2024-10-30 11:17 ` Vladimir Zapolskiy 2024-10-30 10:53 ` [PATCH v4 5/6] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma ` (2 subsequent siblings) 6 siblings, 1 reply; 16+ messages in thread From: Vikram Sharma @ 2024-10-30 10:53 UTC (permalink / raw) To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel Refactor the camss_link_entities function by breaking it down into three distinct functions. Each function will handle the linking of a specific entity separately, enhancing readability. Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> --- drivers/media/platform/qcom/camss/camss.c | 159 ++++++++++++++-------- 1 file changed, 105 insertions(+), 54 deletions(-) diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index addaed8f77cb..e4579ce80572 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -2164,14 +2164,66 @@ static int camss_init_subdevices(struct camss *camss) } /* - * camss_link_entities - Register subdev nodes and create links + * camss_link_entities_csid - Register subdev nodes and create links * @camss: CAMSS device * * Return 0 on success or a negative error code on failure */ -static int camss_link_entities(struct camss *camss) +static int camss_link_entities_csid(struct camss *camss) { - int i, j, k; + int i, j; + int ret, line_num; + u16 src_pad; + u16 sink_pad; + struct media_entity *src_entity; + struct media_entity *sink_entity; + + for (i = 0; i < camss->res->csid_num; i++) { + if (camss->ispif) + line_num = camss->ispif->line_num; + else + line_num = camss->vfe[i].res->line_num; + + src_entity = &camss->csid[i].subdev.entity; + for (j = 0; j < line_num; j++) { + if (camss->ispif) { + sink_entity = &camss->ispif->line[j].subdev.entity; + src_pad = MSM_CSID_PAD_SRC; + sink_pad = MSM_ISPIF_PAD_SINK; + } else { + sink_entity = &camss->vfe[i].line[j].subdev.entity; + src_pad = MSM_CSID_PAD_FIRST_SRC + j; + sink_pad = MSM_VFE_PAD_SINK; + } + + ret = media_create_pad_link(src_entity, + src_pad, + sink_entity, + sink_pad, + 0); + if (ret < 0) { + dev_err(camss->dev, + "Failed to link %s->%s entities: %d\n", + src_entity->name, + sink_entity->name, + ret); + return ret; + } + } + } + + return 0; +} + +/* + * camss_link_entities_csiphy - Register subdev nodes and create links + * @camss: CAMSS device + * + * Return 0 on success or a negative error code on failure + */ +static int camss_link_entities_csiphy(struct camss *camss) +{ + int i, j; int ret; for (i = 0; i < camss->res->csiphy_num; i++) { @@ -2192,71 +2244,70 @@ static int camss_link_entities(struct camss *camss) } } - if (camss->ispif) { - for (i = 0; i < camss->res->csid_num; i++) { - for (j = 0; j < camss->ispif->line_num; j++) { - ret = media_create_pad_link(&camss->csid[i].subdev.entity, - MSM_CSID_PAD_SRC, - &camss->ispif->line[j].subdev.entity, - MSM_ISPIF_PAD_SINK, + return 0; +} + +/* + * camss_link_entities_ispif - Register subdev nodes and create links + * @camss: CAMSS device + * + * Return 0 on success or a negative error code on failure + */ +static int camss_link_entities_ispif(struct camss *camss) +{ + int i, j, k; + int ret; + + for (i = 0; i < camss->ispif->line_num; i++) { + for (k = 0; k < camss->res->vfe_num; k++) { + for (j = 0; j < camss->vfe[k].res->line_num; j++) { + struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev; + struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; + + ret = media_create_pad_link(&ispif->entity, + MSM_ISPIF_PAD_SRC, + &vfe->entity, + MSM_VFE_PAD_SINK, 0); if (ret < 0) { dev_err(camss->dev, "Failed to link %s->%s entities: %d\n", - camss->csid[i].subdev.entity.name, - camss->ispif->line[j].subdev.entity.name, + ispif->entity.name, + vfe->entity.name, ret); return ret; } } } - - for (i = 0; i < camss->ispif->line_num; i++) - for (k = 0; k < camss->res->vfe_num; k++) - for (j = 0; j < camss->vfe[k].res->line_num; j++) { - struct v4l2_subdev *ispif = &camss->ispif->line[i].subdev; - struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; - - ret = media_create_pad_link(&ispif->entity, - MSM_ISPIF_PAD_SRC, - &vfe->entity, - MSM_VFE_PAD_SINK, - 0); - if (ret < 0) { - dev_err(camss->dev, - "Failed to link %s->%s entities: %d\n", - ispif->entity.name, - vfe->entity.name, - ret); - return ret; - } - } - } else { - for (i = 0; i < camss->res->csid_num; i++) - for (k = 0; k < camss->res->vfe_num; k++) - for (j = 0; j < camss->vfe[k].res->line_num; j++) { - struct v4l2_subdev *csid = &camss->csid[i].subdev; - struct v4l2_subdev *vfe = &camss->vfe[k].line[j].subdev; - - ret = media_create_pad_link(&csid->entity, - MSM_CSID_PAD_FIRST_SRC + j, - &vfe->entity, - MSM_VFE_PAD_SINK, - 0); - if (ret < 0) { - dev_err(camss->dev, - "Failed to link %s->%s entities: %d\n", - csid->entity.name, - vfe->entity.name, - ret); - return ret; - } - } } return 0; } +/* + * camss_link_entities - Register subdev nodes and create links + * @camss: CAMSS device + * + * Return 0 on success or a negative error code on failure + */ +static int camss_link_entities(struct camss *camss) +{ + int ret; + + ret = camss_link_entities_csiphy(camss); + if (ret < 0) + return ret; + + ret = camss_link_entities_csid(camss); + if (ret < 0) + return ret; + + if (camss->ispif) + ret = camss_link_entities_ispif(camss); + + return ret; +} + /* * camss_register_entities - Register subdev nodes and create links * @camss: CAMSS device -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4 4/6] media: qcom: camss: Restructure camss_link_entities 2024-10-30 10:53 ` [PATCH v4 4/6] media: qcom: camss: Restructure camss_link_entities Vikram Sharma @ 2024-10-30 11:17 ` Vladimir Zapolskiy 0 siblings, 0 replies; 16+ messages in thread From: Vladimir Zapolskiy @ 2024-10-30 11:17 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel On 10/30/24 12:53, Vikram Sharma wrote: > Refactor the camss_link_entities function by breaking it down into > three distinct functions. Each function will handle the linking of > a specific entity separately, enhancing readability. I kindly ask to exclude this change from the series, it is unrelated to the support of a new platform in CAMSS driver. Please send it separately and rebased on the current state of CAMSS source code. > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > drivers/media/platform/qcom/camss/camss.c | 159 ++++++++++++++-------- > 1 file changed, 105 insertions(+), 54 deletions(-) -- Best wishes, Vladimir ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 5/6] arm64: dts: qcom: sc7280: Add support for camss 2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma ` (3 preceding siblings ...) 2024-10-30 10:53 ` [PATCH v4 4/6] media: qcom: camss: Restructure camss_link_entities Vikram Sharma @ 2024-10-30 10:53 ` Vikram Sharma 2024-10-31 18:09 ` Bryan O'Donoghue 2024-10-30 10:53 ` [PATCH v4 6/6] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma 2024-11-01 15:27 ` [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Luca Weiss 6 siblings, 1 reply; 16+ messages in thread From: Vikram Sharma @ 2024-10-30 10:53 UTC (permalink / raw) To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel Add changes to support the camera subsystem on the SC7280. Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 175 +++++++++++++++++++++++++++ 1 file changed, 175 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 55db1c83ef55..690051708dec 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4426,6 +4426,181 @@ cci1_i2c1: i2c-bus@1 { }; }; + camss: camss@acaf000 { + compatible = "qcom,sc7280-camss"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY4_CLK>, + <&camcc CAM_CC_CSI4PHYTIMER_CLK>, + <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_IFE_0_AXI_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_AXI_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_AXI_CLK>, + <&camcc CAM_CC_IFE_2_CLK>, + <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>; + + clock-names = "camnoc_axi", + "csi0", + "csi1", + "csi2", + "csi3", + "csi4", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy4", + "csiphy4_timer", + "gcc_camera_ahb", + "gcc_camera_axi", + "soc_ahb", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe0_lite", + "vfe0_lite_cphy_rx", + "vfe1_lite", + "vfe1_lite_cphy_rx"; + + interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>, + <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; + + interconnect-names = "ahb", "hf_0"; + + interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; + + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + iommus = <&apps_smmu 0x800 0x4e0>; + + power-domains = <&camcc CAM_CC_IFE_0_GDSC>, + <&camcc CAM_CC_IFE_1_GDSC>, + <&camcc CAM_CC_IFE_2_GDSC>, + <&camcc CAM_CC_TITAN_TOP_GDSC>; + + power-domains-names = "ife0", "ife1", "ife2", "top"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0accf000 0x0 0x1000>, + <0x0 0x0ace0000 0x0 0x2000>, + <0x0 0x0ace2000 0x0 0x2000>, + <0x0 0x0ace4000 0x0 0x2000>, + <0x0 0x0ace6000 0x0 0x2000>, + <0x0 0x0ace8000 0x0 0x2000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0accb000 0x0 0x4000>; + + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite0", + "csid_lite1", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "csiphy4", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite0", + "vfe_lite1"; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + }; + + port@1 { + reg = <1>; + }; + + port@2 { + reg = <2>; + }; + + port@3 { + reg = <3>; + }; + + port@4 { + reg = <4>; + }; + }; + }; + camcc: clock-controller@ad00000 { compatible = "qcom,sc7280-camcc"; reg = <0 0x0ad00000 0 0x10000>; -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4 5/6] arm64: dts: qcom: sc7280: Add support for camss 2024-10-30 10:53 ` [PATCH v4 5/6] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma @ 2024-10-31 18:09 ` Bryan O'Donoghue 0 siblings, 0 replies; 16+ messages in thread From: Bryan O'Donoghue @ 2024-10-31 18:09 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel On 30/10/2024 10:53, Vikram Sharma wrote: > Add changes to support the camera subsystem on the SC7280. > > Signed-off-by: Suresh Vankadara <quic_svankada@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sc7280.dtsi | 175 +++++++++++++++++++++++++++ > 1 file changed, 175 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 55db1c83ef55..690051708dec 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -4426,6 +4426,181 @@ cci1_i2c1: i2c-bus@1 { > }; > }; > > + camss: camss@acaf000 { > + compatible = "qcom,sc7280-camss"; > + > + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, Order of declaration of the nodes needs to conform to Documentation/devicetree/bindings/dts-coding-style.rst i.e. reg should come first after compatible --- bod ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v4 6/6] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine 2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma ` (4 preceding siblings ...) 2024-10-30 10:53 ` [PATCH v4 5/6] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma @ 2024-10-30 10:53 ` Vikram Sharma 2024-10-30 11:29 ` Vladimir Zapolskiy 2024-11-01 15:27 ` [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Luca Weiss 6 siblings, 1 reply; 16+ messages in thread From: Vikram Sharma @ 2024-10-30 10:53 UTC (permalink / raw) To: rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, quic_vikramsa, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel The Vision Mezzanine for the RB3 ships with an imx577 camera sensor. Enable the IMX577 on the vision mezzanine. An example media-ctl pipeline for the imx577 is: media-ctl --reset media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]' media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]' media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com> Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> --- arch/arm64/boot/dts/qcom/Makefile | 4 + .../qcs6490-rb3gen2-vision-mezzanine.dtso | 73 +++++++++++++++++++ arch/arm64/boot/dts/qcom/sc7280.dtsi | 33 +++++++++ 3 files changed, 110 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index ac199f809b0d..186768f7c696 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -111,6 +111,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb + +qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo + +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso new file mode 100644 index 000000000000..cd3fe65fa971 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +/* + * Camera Sensor overlay on top of rb3gen2 core kit. + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/qcom,camcc-sc7280.h> + +/dts-v1/; +/plugin/; + +&camcc { + status = "okay"; +}; + +&camss { + vdda-phy-supply = <&vreg_l10c_0p88>; + vdda-pll-supply = <&vreg_l6b_1p2>; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* The port index denotes CSIPHY id i.e. csiphy3 */ + port@3 { + reg = <3>; + csiphy3_ep: endpoint { + clock-lanes = <7>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&imx577_ep>; + }; + }; + }; +}; + +&cci1 { + status = "okay"; +}; + +&cci1_i2c1 { + #address-cells = <1>; + #size-cells = <0>; + + camera@1a { + compatible = "sony,imx577"; + reg = <0x1a>; + + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; + pinctrl-names = "default", "suspend"; + pinctrl-0 = <&cam2_default>; + pinctrl-1 = <&cam2_suspend>; + + clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; + + dovdd-supply = <&vreg_l18b_1p8>; + + port { + imx577_ep: endpoint { + clock-lanes = <7>; + link-frequencies = /bits/ 64 <600000000>; + data-lanes = <0 1 2 3>; + remote-endpoint = <&csiphy3_ep>; + }; + }; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 690051708dec..8130c1374722 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -5115,6 +5115,39 @@ tlmm: pinctrl@f100000 { gpio-ranges = <&tlmm 0 0 175>; wakeup-parent = <&pdc>; + cam2_default: cam2-default-state { + rst-pins { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + mclk-pins { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-disable; + }; + }; + + cam2_suspend: cam2-suspend-state { + rst-pins { + pins = "gpio78"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + output-low; + }; + + mclk-pins { + pins = "gpio67"; + function = "cam_mclk"; + drive-strength = <2>; + bias-pull-down; + }; + }; + cci0_default: cci0-default-state { pins = "gpio69", "gpio70"; function = "cci_i2c"; -- 2.25.1 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH v4 6/6] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine 2024-10-30 10:53 ` [PATCH v4 6/6] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma @ 2024-10-30 11:29 ` Vladimir Zapolskiy 0 siblings, 0 replies; 16+ messages in thread From: Vladimir Zapolskiy @ 2024-10-30 11:29 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel On 10/30/24 12:53, Vikram Sharma wrote: > The Vision Mezzanine for the RB3 ships with an imx577 camera sensor. > Enable the IMX577 on the vision mezzanine. > > An example media-ctl pipeline for the imx577 is: > > media-ctl --reset > media-ctl -v -V '"imx577 '19-001a'":0[fmt:SRGGB10/4056x3040 field:none]' > media-ctl -V '"msm_csiphy3":0[fmt:SRGGB10/4056x3040]' > media-ctl -V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' > media-ctl -V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' > media-ctl -l '"msm_csiphy3":1->"msm_csid0":0[1]' > media-ctl -l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' > > yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 > > Signed-off-by: Hariram Purushothaman <quic_hariramp@quicinc.com> > Signed-off-by: Vikram Sharma <quic_vikramsa@quicinc.com> > Signed-off-by: Trishansh Bhardwaj <quic_tbhardwa@quicinc.com> > --- > arch/arm64/boot/dts/qcom/Makefile | 4 + > .../qcs6490-rb3gen2-vision-mezzanine.dtso | 73 +++++++++++++++++++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 33 +++++++++ > 3 files changed, 110 insertions(+) > create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso > > diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile > index ac199f809b0d..186768f7c696 100644 > --- a/arch/arm64/boot/dts/qcom/Makefile > +++ b/arch/arm64/boot/dts/qcom/Makefile > @@ -111,6 +111,10 @@ dtb-$(CONFIG_ARCH_QCOM) += qcm6490-shift-otter.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2.dtb > + > +qcs6490-rb3gen2-vision-mezzanine-dtbs := qcs6490-rb3gen2.dtb qcs6490-rb3gen2-vision-mezzanine.dtbo > + > +dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb > dtb-$(CONFIG_ARCH_QCOM) += qcs8550-aim300-aiot.dtb > dtb-$(CONFIG_ARCH_QCOM) += qdu1000-idp.dtb > dtb-$(CONFIG_ARCH_QCOM) += qrb2210-rb1.dtb > diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso > new file mode 100644 > index 000000000000..cd3fe65fa971 > --- /dev/null > +++ b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso > @@ -0,0 +1,73 @@ > +// SPDX-License-Identifier: BSD-3-Clause > +/* > + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. > + */ > + > +/* > + * Camera Sensor overlay on top of rb3gen2 core kit. > + */ > + > +#include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/clock/qcom,camcc-sc7280.h> > + > +/dts-v1/; > +/plugin/; > + > +&camcc { > + status = "okay"; > +}; > + > +&camss { > + vdda-phy-supply = <&vreg_l10c_0p88>; > + vdda-pll-supply = <&vreg_l6b_1p2>; > + status = "okay"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + /* The port index denotes CSIPHY id i.e. csiphy3 */ > + port@3 { > + reg = <3>; > + csiphy3_ep: endpoint { > + clock-lanes = <7>; > + data-lanes = <0 1 2 3>; > + remote-endpoint = <&imx577_ep>; > + }; > + }; > + }; > +}; > + > +&cci1 { > + status = "okay"; > +}; > + > +&cci1_i2c1 { > + #address-cells = <1>; > + #size-cells = <0>; > + > + camera@1a { > + compatible = "sony,imx577"; > + reg = <0x1a>; > + > + reset-gpios = <&tlmm 78 GPIO_ACTIVE_LOW>; > + pinctrl-names = "default", "suspend"; > + pinctrl-0 = <&cam2_default>; > + pinctrl-1 = <&cam2_suspend>; > + > + clocks = <&camcc CAM_CC_MCLK3_CLK>; > + assigned-clocks = <&camcc CAM_CC_MCLK3_CLK>; > + assigned-clock-rates = <24000000>; > + > + dovdd-supply = <&vreg_l18b_1p8>; > + > + port { > + imx577_ep: endpoint { > + clock-lanes = <7>; > + link-frequencies = /bits/ 64 <600000000>; > + data-lanes = <0 1 2 3>; > + remote-endpoint = <&csiphy3_ep>; > + }; > + }; > + }; > +}; > diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi > index 690051708dec..8130c1374722 100644 > --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi > +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi > @@ -5115,6 +5115,39 @@ tlmm: pinctrl@f100000 { > gpio-ranges = <&tlmm 0 0 175>; > wakeup-parent = <&pdc>; > > + cam2_default: cam2-default-state { > + rst-pins { > + pins = "gpio78"; > + function = "gpio"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + mclk-pins { > + pins = "gpio67"; > + function = "cam_mclk"; > + drive-strength = <2>; > + bias-disable; > + }; > + }; SoC-specific change of adding new pin functions into the platform dtsi file shall be separated from the rest of the mezzanine board change, send it as its own change, you may wish add all MCLK pins at once. And the camera sensor reset "gpio" pin goes into the mezzanine specific change. > + > + cam2_suspend: cam2-suspend-state { > + rst-pins { > + pins = "gpio78"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + output-low; > + }; > + > + mclk-pins { > + pins = "gpio67"; > + function = "cam_mclk"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + }; > + Same as above. > cci0_default: cci0-default-state { > pins = "gpio69", "gpio70"; > function = "cci_i2c"; -- Best wishes, Vladimir ^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH v4 0/6] media: qcom: camss: Add sc7280 support 2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma ` (5 preceding siblings ...) 2024-10-30 10:53 ` [PATCH v4 6/6] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma @ 2024-11-01 15:27 ` Luca Weiss [not found] ` <1f173036-279d-4802-bf04-cfa2d8066e68@quicinc.com> 6 siblings, 1 reply; 16+ messages in thread From: Luca Weiss @ 2024-11-01 15:27 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will Cc: linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel On Wed Oct 30, 2024 at 11:53 AM CET, Vikram Sharma wrote: > SC7280 is a Qualcomm SoC. This series adds support to bring up the CSIPHY, > CSID, VFE/RDI interfaces in SC7280. > > SC7280 provides > > - 3 x VFE, 3 RDI per VFE > - 2 x VFE Lite, 4 RDI per VFE > - 3 x CSID > - 2 x CSID Lite > - 5 x CSI PHY > > The changes are verified on SC7280 qcs6490-rb3gen2 board, with attached vision mezzanine > the base dts for qcs6490-rb3gen2 is: > https://lore.kernel.org/all/20231103184655.23555-1-quic_kbajaj@quicinc.com/ Hi Vikram! Two things: You use the property "power-domains-names" in both bindings and dtsi but this property is never parsed in the kernel. This should be "power-domain-names" Second, I still can't get the test pattern to work on my QCM6490-based phone (Fairphone 5). Could you please try if the commands as per [0] work on your board? [0] https://lore.kernel.org/linux-arm-msm/c912f2da-519c-4bdc-a5cb-e19c3aa63ea8@linaro.org/ Regards Luca > > Changes in V4: > - V3 had 8 patches and V4 is reduced to 6. > - Removed [Patch v3 2/8] as binding change is not required for dtso. > - Removed [Patch v3 3/8] as the fix is already taken care in latest > kernel tip. > - Updated alignment for dtsi and dt-bindings. > - Adding qcs6490-rb3gen2-vision-mezzanine as overlay. > - Link to v3: https://lore.kernel.org/linux-arm-msm/20241011140932.1744124-1-quic_vikramsa@quicinc.com/ > > Changes in V3: > - Added missed subject line for cover letter of V2. > - Updated Alignment, indentation and properties order. > - edit commit text for [PATCH 02/10] and [PATCH 03/10]. > - Refactor camss_link_entities. > - Removed camcc enablement changes as it already done. > - Link to v2: https://lore.kernel.org/linux-arm-msm/20240904-camss_on_sc7280_rb3gen2_vision_v2_patches-v1-0-b18ddcd7d9df@quicinc.com/ > > Changes in V2: > - Improved indentation/formatting. > - Removed _src clocks and misleading code comments. > - Added name fields for power domains and csid register offset in DTSI. > - Dropped minItems field from YAML file. > - Listed changes in alphabetical order. > - Updated description and commit text to reflect changes > - Changed the compatible string from imx412 to imx577. > - Added board-specific enablement changes in the newly created vision > board DTSI file. > - Fixed bug encountered during testing. > - Moved logically independent changes to a new/seprate patch. > - Removed cci0 as no sensor is on this port and MCLK2, which was a > copy-paste error from the RB5 board reference. > - Added power rails, referencing the RB5 board. > - Discarded Patch 5/6 completely (not required). > - Removed unused enums. > - Link to v1: https://lore.kernel.org/linux-arm-msm/20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com/ > > Suresh Vankadara (1): > media: qcom: camss: Add support for camss driver on SC7280 > > Vikram Sharma (5): > media: dt-bindings: media: camss: Add qcom,sc7280-camss binding > media: qcom: camss: Sort CAMSS version enums and compatible strings > media: qcom: camss: Restructure camss_link_entities > arm64: dts: qcom: sc7280: Add support for camss > arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision > mezzanine > > .../bindings/media/qcom,sc7280-camss.yaml | 439 +++++++++++++++ > arch/arm64/boot/dts/qcom/Makefile | 4 + > .../qcs6490-rb3gen2-vision-mezzanine.dtso | 73 +++ > arch/arm64/boot/dts/qcom/sc7280.dtsi | 208 ++++++++ > .../media/platform/qcom/camss/camss-csid.c | 1 - > .../qcom/camss/camss-csiphy-3ph-1-0.c | 13 +- > .../media/platform/qcom/camss/camss-csiphy.c | 5 + > .../media/platform/qcom/camss/camss-csiphy.h | 1 + > drivers/media/platform/qcom/camss/camss-vfe.c | 8 +- > drivers/media/platform/qcom/camss/camss.c | 500 ++++++++++++++++-- > drivers/media/platform/qcom/camss/camss.h | 1 + > 11 files changed, 1190 insertions(+), 63 deletions(-) > create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso ^ permalink raw reply [flat|nested] 16+ messages in thread
[parent not found: <1f173036-279d-4802-bf04-cfa2d8066e68@quicinc.com>]
* Re: [PATCH v4 0/6] media: qcom: camss: Add sc7280 support [not found] ` <1f173036-279d-4802-bf04-cfa2d8066e68@quicinc.com> @ 2024-11-05 12:40 ` Luca Weiss 0 siblings, 0 replies; 16+ messages in thread From: Luca Weiss @ 2024-11-05 12:40 UTC (permalink / raw) To: Vikram Sharma, rfoss, todor.too, bryan.odonoghue, mchehab, robh, krzk+dt, conor+dt, akapatra, hariramp, andersson, konradybcio, hverkuil-cisco, cros-qcom-dts-watchers, catalin.marinas, will, matti.lehtimaki Cc: bryan.odonoghue, linux-arm-kernel, linux-media, linux-arm-msm, devicetree, linux-kernel, kernel [-- Attachment #1.1: Type: text/plain, Size: 6310 bytes --] Hi Vikram, On Mon Nov 4, 2024 at 10:08 AM CET, Vikram Sharma wrote: > Hi Luca, > > Thanks for your review and your efforts to validate tpg for this > Please find my comments inline. > > Regards, > Vikram > > On 11/1/2024 8:57 PM, Luca Weiss wrote: > > On Wed Oct 30, 2024 at 11:53 AM CET, Vikram Sharma wrote: > >> SC7280 is a Qualcomm SoC. This series adds support to bring up the CSIPHY, > >> CSID, VFE/RDI interfaces in SC7280. > >> > >> SC7280 provides > >> > >> - 3 x VFE, 3 RDI per VFE > >> - 2 x VFE Lite, 4 RDI per VFE > >> - 3 x CSID > >> - 2 x CSID Lite > >> - 5 x CSI PHY > >> > >> The changes are verified on SC7280 qcs6490-rb3gen2 board, with attached vision mezzanine > >> the base dts for qcs6490-rb3gen2 is: > >> https://lore.kernel.org/all/20231103184655.23555-1-quic_kbajaj@quicinc.com/ > > Hi Vikram! > > > > Two things: > > > > You use the property "power-domains-names" in both bindings and dtsi but > > this property is never parsed in the kernel. This should be > > "power-domain-names" > Thanks for this catch. I will update this in next version. > > > > Second, I still can't get the test pattern to work on my QCM6490-based > > phone (Fairphone 5). Could you please try if the commands as per [0] > > work on your board? > I verified TPG with this change. but only mode 8 and 9 are working for TPG. > Rest of the modes are getting stuck. To debug this I have verified the > register dump for all the TPG registers in all the modes. > as expected the register programming is similar for all the modes just > mode field is getting updated. > We are discussing this issue with TPG hardware team. Will keep you posted. > > Steps I used to validate TPG: > > echo "* Reset pipeline" > media-ctl-d**/dev/media0**--reset > yavta --list /dev/v4l-subdev5 > > # /dev/v4l-subdev5 represent CSID0 can be different as well. > yavta --no-query -w '0x009f0903*8*' /dev/v4l-subdev5 > > media-ctl -d/dev/media0*-*V '"msm_csid0":0[fmt:SRGGB10/4056x3040]' > > media-ctl-d/dev/media0**-V '"msm_vfe0_rdi0":0[fmt:SRGGB10/4056x3040]' > > media-ctl-d/dev/media0**-l '"msm_csid0":1->"msm_vfe0_rdi0":0[1]' > > yavta -B capture-mplane -c -I -n 5 -f SRGGB10P -s 4056x3040 -F /dev/video0 Thanks for checking, I can confirm I see the same behavior on my board, test pattern 8 and 9 work as expected. This seems to be some issue with the clocks since taking the clock definitions from older sc7280 camss patches (never sent to the list) test patterns 1-7 work properly. Please see attached patch on top of yours with which it works. I haven't dug into it more to find out which exact clock is causing this, but this should be a good starting point for you & the hardware team. Regards Luca > > > > > [0]https://lore.kernel.org/linux-arm-msm/c912f2da-519c-4bdc-a5cb-e19c3aa63ea8@linaro.org/ > > > > Regards > > Luca > > > >> Changes in V4: > >> - V3 had 8 patches and V4 is reduced to 6. > >> - Removed [Patch v3 2/8] as binding change is not required for dtso. > >> - Removed [Patch v3 3/8] as the fix is already taken care in latest > >> kernel tip. > >> - Updated alignment for dtsi and dt-bindings. > >> - Adding qcs6490-rb3gen2-vision-mezzanine as overlay. > >> - Link to v3:https://lore.kernel.org/linux-arm-msm/20241011140932.1744124-1-quic_vikramsa@quicinc.com/ > >> > >> Changes in V3: > >> - Added missed subject line for cover letter of V2. > >> - Updated Alignment, indentation and properties order. > >> - edit commit text for [PATCH 02/10] and [PATCH 03/10]. > >> - Refactor camss_link_entities. > >> - Removed camcc enablement changes as it already done. > >> - Link to v2:https://lore.kernel.org/linux-arm-msm/20240904-camss_on_sc7280_rb3gen2_vision_v2_patches-v1-0-b18ddcd7d9df@quicinc.com/ > >> > >> Changes in V2: > >> - Improved indentation/formatting. > >> - Removed _src clocks and misleading code comments. > >> - Added name fields for power domains and csid register offset in DTSI. > >> - Dropped minItems field from YAML file. > >> - Listed changes in alphabetical order. > >> - Updated description and commit text to reflect changes > >> - Changed the compatible string from imx412 to imx577. > >> - Added board-specific enablement changes in the newly created vision > >> board DTSI file. > >> - Fixed bug encountered during testing. > >> - Moved logically independent changes to a new/seprate patch. > >> - Removed cci0 as no sensor is on this port and MCLK2, which was a > >> copy-paste error from the RB5 board reference. > >> - Added power rails, referencing the RB5 board. > >> - Discarded Patch 5/6 completely (not required). > >> - Removed unused enums. > >> - Link to v1:https://lore.kernel.org/linux-arm-msm/20240629-camss_first_post_linux_next-v1-0-bc798edabc3a@quicinc.com/ > >> > >> Suresh Vankadara (1): > >> media: qcom: camss: Add support for camss driver on SC7280 > >> > >> Vikram Sharma (5): > >> media: dt-bindings: media: camss: Add qcom,sc7280-camss binding > >> media: qcom: camss: Sort CAMSS version enums and compatible strings > >> media: qcom: camss: Restructure camss_link_entities > >> arm64: dts: qcom: sc7280: Add support for camss > >> arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision > >> mezzanine > >> > >> .../bindings/media/qcom,sc7280-camss.yaml | 439 +++++++++++++++ > >> arch/arm64/boot/dts/qcom/Makefile | 4 + > >> .../qcs6490-rb3gen2-vision-mezzanine.dtso | 73 +++ > >> arch/arm64/boot/dts/qcom/sc7280.dtsi | 208 ++++++++ > >> .../media/platform/qcom/camss/camss-csid.c | 1 - > >> .../qcom/camss/camss-csiphy-3ph-1-0.c | 13 +- > >> .../media/platform/qcom/camss/camss-csiphy.c | 5 + > >> .../media/platform/qcom/camss/camss-csiphy.h | 1 + > >> drivers/media/platform/qcom/camss/camss-vfe.c | 8 +- > >> drivers/media/platform/qcom/camss/camss.c | 500 ++++++++++++++++-- > >> drivers/media/platform/qcom/camss/camss.h | 1 + > >> 11 files changed, 1190 insertions(+), 63 deletions(-) > >> create mode 100644 Documentation/devicetree/bindings/media/qcom,sc7280-camss.yaml > >> create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-vision-mezzanine.dtso [-- Attachment #2: sc7280-camss-tpg-clocks.diff --] [-- Type: text/x-patch, Size: 12677 bytes --] diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 01f18080a798..69955d5f2e73 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -4422,12 +4422,12 @@ cci1_i2c1: i2c-bus@1 { camss: camss@acaf000 { compatible = "qcom,sc7280-camss"; - clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, - <&camcc CAM_CC_IFE_0_CSID_CLK>, - <&camcc CAM_CC_IFE_1_CSID_CLK>, - <&camcc CAM_CC_IFE_2_CSID_CLK>, - <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, - <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>, + clocks = <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPHY_RX_CLK_SRC>, <&camcc CAM_CC_CSIPHY0_CLK>, <&camcc CAM_CC_CSI0PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY1_CLK>, @@ -4438,29 +4438,32 @@ camss: camss@acaf000 { <&camcc CAM_CC_CSI3PHYTIMER_CLK>, <&camcc CAM_CC_CSIPHY4_CLK>, <&camcc CAM_CC_CSI4PHYTIMER_CLK>, - <&gcc GCC_CAMERA_AHB_CLK>, - <&gcc GCC_CAMERA_HF_AXI_CLK>, - <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, <&camcc CAM_CC_IFE_0_AXI_CLK>, <&camcc CAM_CC_IFE_0_CLK>, <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_0_CSID_CLK>, <&camcc CAM_CC_IFE_1_AXI_CLK>, <&camcc CAM_CC_IFE_1_CLK>, <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_1_CSID_CLK>, <&camcc CAM_CC_IFE_2_AXI_CLK>, <&camcc CAM_CC_IFE_2_CLK>, <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_2_CSID_CLK>, <&camcc CAM_CC_IFE_LITE_0_CLK>, <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, <&camcc CAM_CC_IFE_LITE_1_CLK>, - <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>; - - clock-names = "camnoc_axi", - "csi0", - "csi1", - "csi2", - "csi3", - "csi4", + <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; + clock-names = "cam_hf_axi", + "cam_sf_axi", + "camnoc_axi", + "camnoc_axi_src", + "cpas_ahb", + "cphy_rx_src", "csiphy0", "csiphy0_timer", "csiphy1", @@ -4471,22 +4474,26 @@ camss: camss@acaf000 { "csiphy3_timer", "csiphy4", "csiphy4_timer", - "gcc_camera_ahb", - "gcc_camera_axi", - "soc_ahb", + "icp_ahb", + "slow_ahb_src", "vfe0_axi", "vfe0", "vfe0_cphy_rx", + "vfe0_csid", "vfe1_axi", "vfe1", "vfe1_cphy_rx", + "vfe1_csid", "vfe2_axi", "vfe2", "vfe2_cphy_rx", - "vfe0_lite", - "vfe0_lite_cphy_rx", - "vfe1_lite", - "vfe1_lite_cphy_rx"; + "vfe2_csid", + "vfe_lite0", + "vfe_lite0_cphy_rx", + "vfe_lite0_csid", + "vfe_lite1", + "vfe_lite1_cphy_rx", + "vfe_lite1_csid"; interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_CAMERA_CFG 0>, <&mmss_noc MASTER_CAMNOC_HF 0 &mc_virt SLAVE_EBI1 0>; diff --git a/drivers/media/platform/qcom/camss/camss.c b/drivers/media/platform/qcom/camss/camss.c index 319281bcc7a5..cb8921c65196 100644 --- a/drivers/media/platform/qcom/camss/camss.c +++ b/drivers/media/platform/qcom/camss/camss.c @@ -1484,11 +1484,9 @@ static const struct camss_subdev_resources csiphy_res_7280[] = { /* CSIPHY0 */ { .regulators = {}, - .clock = { "csiphy0", "csiphy0_timer"}, - .clock_rate = { - { 300000000 }, - { 300000000 } - }, + .clock = { "csiphy0", "csiphy0_timer" }, + .clock_rate = { { 300000000, 400000000 }, + { 300000000 } }, .reg = { "csiphy0" }, .interrupt = { "csiphy0" }, .csiphy = { @@ -1499,11 +1497,9 @@ static const struct camss_subdev_resources csiphy_res_7280[] = { /* CSIPHY1 */ { .regulators = {}, - .clock = { "csiphy1", "csiphy1_timer"}, - .clock_rate = { - { 300000000 }, - { 300000000 } - }, + .clock = { "csiphy1", "csiphy1_timer" }, + .clock_rate = { { 300000000, 400000000 }, + { 300000000 } }, .reg = { "csiphy1" }, .interrupt = { "csiphy1" }, .csiphy = { @@ -1514,11 +1510,9 @@ static const struct camss_subdev_resources csiphy_res_7280[] = { /* CSIPHY2 */ { .regulators = {}, - .clock = { "csiphy2", "csiphy2_timer"}, - .clock_rate = { - { 300000000 }, - { 300000000 } - }, + .clock = { "csiphy2", "csiphy2_timer" }, + .clock_rate = { { 300000000, 400000000 }, + { 300000000 } }, .reg = { "csiphy2" }, .interrupt = { "csiphy2" }, .csiphy = { @@ -1529,11 +1523,9 @@ static const struct camss_subdev_resources csiphy_res_7280[] = { /* CSIPHY3 */ { .regulators = {}, - .clock = { "csiphy3", "csiphy3_timer"}, - .clock_rate = { - { 300000000 }, - { 300000000 } - }, + .clock = { "csiphy3", "csiphy3_timer" }, + .clock_rate = { { 300000000, 400000000 }, + { 300000000 } }, .reg = { "csiphy3" }, .interrupt = { "csiphy3" }, .csiphy = { @@ -1544,11 +1536,9 @@ static const struct camss_subdev_resources csiphy_res_7280[] = { /* CSIPHY4 */ { .regulators = {}, - .clock = { "csiphy4", "csiphy4_timer"}, - .clock_rate = { - { 300000000 }, - { 300000000 } - }, + .clock = { "csiphy4", "csiphy4_timer" }, + .clock_rate = { { 300000000, 400000000 }, + { 300000000 } }, .reg = { "csiphy4" }, .interrupt = { "csiphy4" }, .csiphy = { @@ -1563,13 +1553,10 @@ static const struct camss_subdev_resources csid_res_7280[] = { { .regulators = { "vdda-phy", "vdda-pll" }, - .clock = { "csi0", "vfe0_cphy_rx", "vfe0", "soc_ahb"}, - .clock_rate = { - { 300000000, 0, 380000000, 0}, - { 400000000, 0, 510000000, 0}, - { 400000000, 0, 637000000, 0}, - { 400000000, 0, 760000000, 0} - }, + .clock = { "vfe0_csid", "vfe0_cphy_rx", "vfe0" }, + .clock_rate = { { 300000000, 400000000 }, + { 0 }, + { 380000000, 510000000, 637000000, 760000000 } }, .reg = { "csid0" }, .interrupt = { "csid0" }, @@ -1584,13 +1571,10 @@ static const struct camss_subdev_resources csid_res_7280[] = { { .regulators = { "vdda-phy", "vdda-pll" }, - .clock = { "csi1", "vfe1_cphy_rx", "vfe1", "soc_ahb"}, - .clock_rate = { - { 300000000, 0, 380000000, 0}, - { 400000000, 0, 510000000, 0}, - { 400000000, 0, 637000000, 0}, - { 400000000, 0, 760000000, 0} - }, + .clock = { "vfe1_csid", "vfe1_cphy_rx", "vfe1" }, + .clock_rate = { { 300000000, 400000000 }, + { 0 }, + { 380000000, 510000000, 637000000, 760000000 } }, .reg = { "csid1" }, .interrupt = { "csid1" }, @@ -1605,13 +1589,10 @@ static const struct camss_subdev_resources csid_res_7280[] = { { .regulators = { "vdda-phy", "vdda-pll" }, - .clock = { "csi2", "vfe2_cphy_rx", "vfe2", "soc_ahb"}, - .clock_rate = { - { 300000000, 0, 380000000, 0}, - { 400000000, 0, 510000000, 0}, - { 400000000, 0, 637000000, 0}, - { 400000000, 0, 760000000, 0} - }, + .clock = { "vfe2_csid", "vfe2_cphy_rx", "vfe2" }, + .clock_rate = { { 300000000, 400000000 }, + { 0 }, + { 380000000, 510000000, 637000000, 760000000 } }, .reg = { "csid2" }, .interrupt = { "csid2" }, @@ -1626,13 +1607,10 @@ static const struct camss_subdev_resources csid_res_7280[] = { { .regulators = { "vdda-phy", "vdda-pll" }, - .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, - .clock_rate = { - { 300000000, 0, 320000000, 0}, - { 400000000, 0, 400000000, 0}, - { 400000000, 0, 480000000, 0}, - { 400000000, 0, 600000000, 0} - }, + .clock = { "vfe_lite0_csid", "vfe_lite0_cphy_rx", "vfe_lite0" }, + .clock_rate = { { 300000000, 400000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 } }, .reg = { "csid_lite0" }, .interrupt = { "csid_lite0" }, @@ -1647,13 +1625,10 @@ static const struct camss_subdev_resources csid_res_7280[] = { { .regulators = { "vdda-phy", "vdda-pll" }, - .clock = { "csi3", "vfe0_lite_cphy_rx", "vfe0_lite", "soc_ahb"}, - .clock_rate = { - { 300000000, 0, 320000000, 0}, - { 400000000, 0, 400000000, 0}, - { 400000000, 0, 480000000, 0}, - { 400000000, 0, 600000000, 0} - }, + .clock = { "vfe_lite1_csid", "vfe_lite1_cphy_rx", "vfe_lite1" }, + .clock_rate = { { 300000000, 400000000 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 } }, .reg = { "csid_lite1" }, .interrupt = { "csid_lite1" }, @@ -1671,15 +1646,16 @@ static const struct camss_subdev_resources vfe_res_7280[] = { { .regulators = {}, - .clock = { "vfe0", "vfe0_axi", "soc_ahb", - "camnoc_axi", "gcc_camera_axi"}, - .clock_rate = { - { 380000000, 0, 80000000, 150000000, 0}, - { 510000000, 0, 80000000, 240000000, 0}, - { 637000000, 0, 80000000, 320000000, 0}, - { 760000000, 0, 80000000, 400000000, 0}, - { 760000000, 0, 80000000, 480000000, 0}, - }, + .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "icp_ahb", "vfe0", "vfe0_axi", "cam_hf_axi" }, + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, + { 80000000 }, + { 80000000 }, + { 0 }, + { 0 }, + { 380000000, 510000000, 637000000, 760000000 }, + { 0 }, + { 0 } }, .reg = { "vfe0" }, .interrupt = { "vfe0" }, @@ -1697,15 +1673,16 @@ static const struct camss_subdev_resources vfe_res_7280[] = { { .regulators = {}, - .clock = { "vfe1", "vfe1_axi", "soc_ahb", - "camnoc_axi", "gcc_camera_axi"}, - .clock_rate = { - { 380000000, 0, 80000000, 150000000, 0}, - { 510000000, 0, 80000000, 240000000, 0}, - { 637000000, 0, 80000000, 320000000, 0}, - { 760000000, 0, 80000000, 400000000, 0}, - { 760000000, 0, 80000000, 480000000, 0}, - }, + .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "icp_ahb", "vfe1", "vfe1_axi", "cam_hf_axi" }, + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, + { 80000000 }, + { 80000000 }, + { 0 }, + { 0 }, + { 380000000, 510000000, 637000000, 760000000 }, + { 0 }, + { 0 } }, .reg = { "vfe1" }, .interrupt = { "vfe1" }, @@ -1723,15 +1700,16 @@ static const struct camss_subdev_resources vfe_res_7280[] = { { .regulators = {}, - .clock = { "vfe2", "vfe2_axi", "soc_ahb", - "camnoc_axi", "gcc_camera_axi"}, - .clock_rate = { - { 380000000, 0, 80000000, 150000000, 0}, - { 510000000, 0, 80000000, 240000000, 0}, - { 637000000, 0, 80000000, 320000000, 0}, - { 760000000, 0, 80000000, 400000000, 0}, - { 760000000, 0, 80000000, 480000000, 0}, - }, + .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "icp_ahb", "vfe2", "vfe2_axi", "cam_hf_axi" }, + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, + { 80000000 }, + { 80000000 }, + { 0 }, + { 0 }, + { 380000000, 510000000, 637000000, 760000000 }, + { 0 }, + { 0 } }, .reg = { "vfe2" }, .interrupt = { "vfe2" }, @@ -1747,14 +1725,15 @@ static const struct camss_subdev_resources vfe_res_7280[] = { }, /* VFE3 (lite) */ { - .clock = { "vfe0_lite", "soc_ahb", - "camnoc_axi", "gcc_camera_axi"}, - .clock_rate = { - { 320000000, 80000000, 150000000, 0}, - { 400000000, 80000000, 240000000, 0}, - { 480000000, 80000000, 320000000, 0}, - { 600000000, 80000000, 400000000, 0}, - }, + .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "icp_ahb", "vfe_lite0", "cam_hf_axi" }, + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, + { 80000000 }, + { 80000000 }, + { 0 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, + { 0 } }, .regulators = {}, .reg = { "vfe_lite0" }, @@ -1769,14 +1748,15 @@ static const struct camss_subdev_resources vfe_res_7280[] = { }, /* VFE4 (lite) */ { - .clock = { "vfe1_lite", "soc_ahb", - "camnoc_axi", "gcc_camera_axi"}, - .clock_rate = { - { 320000000, 80000000, 150000000, 0}, - { 400000000, 80000000, 240000000, 0}, - { 480000000, 80000000, 320000000, 0}, - { 600000000, 80000000, 400000000, 0}, - }, + .clock = { "camnoc_axi_src", "slow_ahb_src", "cpas_ahb", + "camnoc_axi", "icp_ahb", "vfe_lite1", "cam_hf_axi" }, + .clock_rate = { { 150000000, 240000000, 320000000, 400000000, 480000000 }, + { 80000000 }, + { 80000000 }, + { 0 }, + { 0 }, + { 320000000, 400000000, 480000000, 600000000 }, + { 0 } }, .regulators = {}, .reg = { "vfe_lite1" }, ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2024-11-05 12:40 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
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2024-10-30 10:53 [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Vikram Sharma
2024-10-30 10:53 ` [PATCH v4 1/6] media: dt-bindings: media: camss: Add qcom,sc7280-camss binding Vikram Sharma
2024-10-30 11:10 ` Vladimir Zapolskiy
2024-11-01 10:09 ` Krzysztof Kozlowski
2024-10-30 10:53 ` [PATCH v4 2/6] media: qcom: camss: Sort CAMSS version enums and compatible strings Vikram Sharma
2024-10-30 10:53 ` [PATCH v4 3/6] media: qcom: camss: Add support for camss driver on SC7280 Vikram Sharma
2024-10-30 11:15 ` Vladimir Zapolskiy
2024-10-31 17:58 ` Bryan O'Donoghue
2024-10-30 10:53 ` [PATCH v4 4/6] media: qcom: camss: Restructure camss_link_entities Vikram Sharma
2024-10-30 11:17 ` Vladimir Zapolskiy
2024-10-30 10:53 ` [PATCH v4 5/6] arm64: dts: qcom: sc7280: Add support for camss Vikram Sharma
2024-10-31 18:09 ` Bryan O'Donoghue
2024-10-30 10:53 ` [PATCH v4 6/6] arm64: dts: qcom: qcs6490-rb3gen2-vision-mezzanine: Add vision mezzanine Vikram Sharma
2024-10-30 11:29 ` Vladimir Zapolskiy
2024-11-01 15:27 ` [PATCH v4 0/6] media: qcom: camss: Add sc7280 support Luca Weiss
[not found] ` <1f173036-279d-4802-bf04-cfa2d8066e68@quicinc.com>
2024-11-05 12:40 ` Luca Weiss
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