* [PATCH v4 0/4] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon
@ 2025-01-19 0:54 Bryan O'Donoghue
2025-01-19 0:54 ` [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
` (3 more replies)
0 siblings, 4 replies; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-01-19 0:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Krzysztof Kozlowski,
Konrad Dybcio
v4:
- Applies RB from Konrad
- Adds the second CCI I2C bus to CCI commit log description.
I previously considered leaving out the always on pins but, decided
to include them in the end and forgot to align the commit log.
- Alphabetises the camcc.h included in the dtsi. - Vlad
- Link to v3: https://lore.kernel.org/r/20250102-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v3-0-cb66d55d20cc@linaro.org
v3:
- Fixes ordering of headers in dtsi - Vlad
- Changes camcc to always on - Vlad
- Applies RB as indicated - Krzysztof, Konrad
- Link to v2: https://lore.kernel.org/r/20241227-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v2-0-06fdd5a7d5bb@linaro.org
v2:
I've gone through each comment and implemented each suggestion since IMO
they were all good/correct comments.
Detail:
- Moves x1e80100 camcc to its own yaml - Krzysztof
- csid_wrapper comes first because it is the most relevant
register set - configuring all CSID blocks subordinate to it - bod, Krzysztof
- Fixes missing commit log - Krz
- Updates to latest format established @ sc7280 - bod
- Includes CSID lite which I forgot to add @ v1 - Konrad, bod
- Replaces static ICC parameters with defines - Konrad
- Drops newlines between x and x-name - Konrad
- Drops redundant iommu extents - Konrad
- Leaves CAMERA_AHB_CLK as-is - Kronrad, Dmitry
Link: https://lore.kernel.org/r/3f1a960f-062e-4c29-ae7d-126192f35a8b@oss.qualcomm.com
- Interrupt EDGE_RISING - Vladimir
- Implements suggested regulator names pending refactor to PHY API - Vladimir
- Drop slow_ahb_src clock - Vladimir
Link to v1:
https://lore.kernel.org/r/20241119-b4-linux-next-24-11-18-dtsi-x1e80100-camss-v1-0-54075d75f654@linaro.org
Working tree:
https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/arm-laptop/wip/x1e80100-6.13-rc3
v1:
This series adds dt-bindings and dtsi for CAMSS on x1e80100.
The primary difference between x1e80100 and other platforms is a new VFE
and CSID pair at version 680.
Some minor driver churn will be required to support outside of the new VFE
and CSID blocks but nothing too major.
The CAMCC in this silicon requires two, not one power-domain requiring
either this fix I've proposed here or something similar:
https://lore.kernel.org/linux-arm-msm/bad60452-41b3-42fb-acba-5b7226226d2d@linaro.org/T/#t
That doesn't gate adoption of the binding description though.
A working tree in progress can be found here:
https://git.codelinaro.org/bryan.odonoghue/kernel/-/tree/x1e80100-6.12-rc7+camss?ref_type=heads
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
Bryan O'Donoghue (4):
dt-bindings: media: Add qcom,x1e80100-camss
arm64: dts: qcom: x1e80100: Add CAMCC block definition
arm64: dts: qcom: x1e80100: Add CCI definitions
arm64: dts: qcom: x1e80100: Add CAMSS block definition
.../bindings/media/qcom,x1e80100-camss.yaml | 367 +++++++++++++++++++++
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 351 ++++++++++++++++++++
2 files changed, 718 insertions(+)
---
base-commit: 0907e7fb35756464aa34c35d6abb02998418164b
change-id: 20241119-b4-linux-next-24-11-18-dtsi-x1e80100-camss-82a63736d072
Best regards,
--
Bryan O'Donoghue <bryan.odonoghue@linaro.org>
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss
2025-01-19 0:54 [PATCH v4 0/4] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
@ 2025-01-19 0:54 ` Bryan O'Donoghue
2025-03-10 21:35 ` Vladimir Zapolskiy
` (2 more replies)
2025-01-19 0:54 ` [PATCH v4 2/4] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
` (2 subsequent siblings)
3 siblings, 3 replies; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-01-19 0:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Krzysztof Kozlowski
Add bindings for qcom,x1e80100-camss in order to support the camera
subsystem for x1e80100 as found in various Co-Pilot laptops.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
.../bindings/media/qcom,x1e80100-camss.yaml | 367 +++++++++++++++++++++
1 file changed, 367 insertions(+)
diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
new file mode 100644
index 0000000000000..88eeac262f0e2
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
@@ -0,0 +1,367 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm X1E80100 Camera Subsystem (CAMSS)
+
+maintainers:
+ - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+
+description: |
+ The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
+
+properties:
+ compatible:
+ const: qcom,x1e80100-camss
+
+ reg:
+ maxItems: 17
+
+ reg-names:
+ items:
+ - const: csid_wrapper
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy4
+ - const: csitpg0
+ - const: csitpg1
+ - const: csitpg2
+ - const: vfe_lite0
+ - const: vfe_lite1
+ - const: vfe0
+ - const: vfe1
+
+ clocks:
+ maxItems: 29
+
+ clock-names:
+ items:
+ - const: camnoc_rt_axi
+ - const: camnoc_nrt_axi
+ - const: core_ahb
+ - const: cpas_ahb
+ - const: cpas_fast_ahb
+ - const: cpas_vfe0
+ - const: cpas_vfe1
+ - const: cpas_vfe_lite
+ - const: cphy_rx_clk_src
+ - const: csid
+ - const: csid_csiphy_rx
+ - const: csiphy0
+ - const: csiphy0_timer
+ - const: csiphy1
+ - const: csiphy1_timer
+ - const: csiphy2
+ - const: csiphy2_timer
+ - const: csiphy4
+ - const: csiphy4_timer
+ - const: gcc_axi_hf
+ - const: gcc_axi_sf
+ - const: vfe0
+ - const: vfe0_fast_ahb
+ - const: vfe1
+ - const: vfe1_fast_ahb
+ - const: vfe_lite
+ - const: vfe_lite_ahb
+ - const: vfe_lite_cphy_rx
+ - const: vfe_lite_csid
+
+ interrupts:
+ maxItems: 13
+
+ interrupt-names:
+ items:
+ - const: csid0
+ - const: csid1
+ - const: csid2
+ - const: csid_lite0
+ - const: csid_lite1
+ - const: csiphy0
+ - const: csiphy1
+ - const: csiphy2
+ - const: csiphy4
+ - const: vfe0
+ - const: vfe1
+ - const: vfe_lite0
+ - const: vfe_lite1
+
+ interconnects:
+ maxItems: 4
+
+ interconnect-names:
+ items:
+ - const: cam_ahb
+ - const: cam_hf_mnoc
+ - const: cam_sf_mnoc
+ - const: cam_sf_icp_mnoc
+
+ iommus:
+ maxItems: 8
+
+ power-domains:
+ items:
+ - description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
+ - description: Titan Top GDSC - Titan ISP Block, Global Distributed Switch Controller.
+
+ power-domain-names:
+ items:
+ - const: ife0
+ - const: ife1
+ - const: top
+
+ vdd-csiphy-0p8-supply:
+ description:
+ Phandle to a 0.8V regulator supply to a PHY.
+
+ vdd-csiphy-1p2-supply:
+ description:
+ Phandle to 1.8V regulator supply to a PHY.
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ description:
+ CSI input ports.
+
+ patternProperties:
+ "^port@[0-3]+$":
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ unevaluatedProperties: false
+
+ description:
+ Input port for receiving CSI data from a CSIPHY.
+
+ properties:
+ endpoint:
+ $ref: video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ clock-lanes:
+ maxItems: 1
+
+ data-lanes:
+ minItems: 1
+ maxItems: 4
+
+ required:
+ - clock-lanes
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - clocks
+ - clock-names
+ - interrupts
+ - interrupt-names
+ - interconnects
+ - interconnect-names
+ - iommus
+ - power-domains
+ - power-domain-names
+ - vdd-csiphy-0p8-supply
+ - vdd-csiphy-1p2-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+ #include <dt-bindings/clock/qcom,x1e80100-camcc.h>
+ #include <dt-bindings/interconnect/qcom,icc.h>
+ #include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ camss: isp@acb6000 {
+ compatible = "qcom,x1e80100-camss";
+
+ reg = <0 0x0acb6000 0 0x1000>,
+ <0 0x0acb7000 0 0x2000>,
+ <0 0x0acb9000 0 0x2000>,
+ <0 0x0acbb000 0 0x2000>,
+ <0 0x0acc6000 0 0x1000>,
+ <0 0x0acca000 0 0x1000>,
+ <0 0x0ace4000 0 0x1000>,
+ <0 0x0ace6000 0 0x1000>,
+ <0 0x0ace8000 0 0x1000>,
+ <0 0x0acec000 0 0x4000>,
+ <0 0x0acf6000 0 0x1000>,
+ <0 0x0acf7000 0 0x1000>,
+ <0 0x0acf8000 0 0x1000>,
+ <0 0x0acc7000 0 0x2000>,
+ <0 0x0accb000 0 0x2000>,
+ <0 0x0ac62000 0 0x4000>,
+ <0 0x0ac71000 0 0x4000>;
+
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe0",
+ "vfe1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+
+ clock-names = "camnoc_rt_axi",
+ "camnoc_nrt_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe_lite",
+ "cphy_rx_clk_src",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ interconnect-names = "cam_ahb",
+ "cam_hf_mnoc",
+ "cam_sf_mnoc",
+ "cam_sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x60>,
+ <&apps_smmu 0x860 0x60>,
+ <&apps_smmu 0x1800 0x60>,
+ <&apps_smmu 0x1860 0x60>,
+ <&apps_smmu 0x18e0 0x00>,
+ <&apps_smmu 0x1980 0x20>,
+ <&apps_smmu 0x1900 0x00>,
+ <&apps_smmu 0x19a0 0x20>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ vdd-csiphy-0p8-supply = <&csiphy_0p8_supply>;
+ vdd-csiphy-1p2-supply = <&csiphy_1p2_supply>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ csiphy_ep0: endpoint {
+ clock-lanes = <7>;
+ data-lanes = <0 1>;
+ remote-endpoint = <&sensor_ep>;
+ };
+ };
+ };
+ };
+ };
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 2/4] arm64: dts: qcom: x1e80100: Add CAMCC block definition
2025-01-19 0:54 [PATCH v4 0/4] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
2025-01-19 0:54 ` [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
@ 2025-01-19 0:54 ` Bryan O'Donoghue
2025-03-10 10:44 ` Vladimir Zapolskiy
2025-01-19 0:54 ` [PATCH v4 3/4] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
2025-01-19 0:54 ` [PATCH v4 4/4] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
3 siblings, 1 reply; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-01-19 0:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Konrad Dybcio
Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration
of previous CAMCC blocks with the exception of having two required
power-domains not just one.
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 9d38436763432..10035bcfa89bb 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
+#include <dt-bindings/clock/qcom,x1e80100-camcc.h>
#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
@@ -5109,6 +5110,21 @@ usb_1_ss1_dwc3_ss: endpoint {
};
};
+ camcc: clock-controller@ade0000 {
+ compatible = "qcom,x1e80100-camcc";
+ reg = <0 0x0ade0000 0 0x20000>;
+ clocks = <&gcc GCC_CAMERA_AHB_CLK>,
+ <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&sleep_clk>;
+ power-domains = <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
mdss: display-subsystem@ae00000 {
compatible = "qcom,x1e80100-mdss";
reg = <0 0x0ae00000 0 0x1000>;
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 3/4] arm64: dts: qcom: x1e80100: Add CCI definitions
2025-01-19 0:54 [PATCH v4 0/4] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
2025-01-19 0:54 ` [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
2025-01-19 0:54 ` [PATCH v4 2/4] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
@ 2025-01-19 0:54 ` Bryan O'Donoghue
2025-03-10 21:15 ` Vladimir Zapolskiy
2025-01-19 0:54 ` [PATCH v4 4/4] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
3 siblings, 1 reply; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-01-19 0:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Konrad Dybcio
Add in two CCI busses.
One bus has two CCI bus master pinouts:
cci_i2c_scl0 = gpio102
cci_i2c_sda0 = gpio101
cci_i2c_scl1 = gpio104
cci_i2c_sda1 = gpio103
The second bus has two CCI bus master pinouts:
cci_i2c_scl2 = gpio106
cci_i2c_sda2 = gpio105
aon_cci_i2c_scl3 = gpio236
aon_cci_i2c_sda3 = gpio235
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 150 +++++++++++++++++++++++++++++++++
1 file changed, 150 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 10035bcfa89bb..de05916e6f295 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5110,6 +5110,84 @@ usb_1_ss1_dwc3_ss: endpoint {
};
};
+ cci0: cci@ac15000 {
+ compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac15000 0 0x1000>;
+
+ interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_0_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci0_default>;
+ pinctrl-1 = <&cci0_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci0_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci0_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
+ cci1: cci@ac16000 {
+ compatible = "qcom,x1e80100-cci", "qcom,msm8996-cci";
+ reg = <0 0x0ac16000 0 0x1000>;
+
+ interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>;
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CCI_1_CLK>;
+ clock-names = "camnoc_axi",
+ "cpas_ahb",
+ "cci";
+
+ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>;
+
+ pinctrl-0 = <&cci1_default>;
+ pinctrl-1 = <&cci1_sleep>;
+ pinctrl-names = "default", "sleep";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+
+ cci1_i2c0: i2c-bus@0 {
+ reg = <0>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ cci1_i2c1: i2c-bus@1 {
+ reg = <1>;
+ clock-frequency = <1000000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,x1e80100-camcc";
reg = <0 0x0ade0000 0 0x20000>;
@@ -5733,6 +5811,78 @@ tlmm: pinctrl@f100000 {
gpio-ranges = <&tlmm 0 0 239>;
wakeup-parent = <&pdc>;
+ cci0_default: cci0-default-state {
+ cci0_i2c0_default: cci0-i2c0-default-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio101", "gpio102";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci0_i2c1_default: cci0-i2c1-default-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio103", "gpio104";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci0_sleep: cci0-sleep-state {
+ cci0_i2c0_sleep: cci0-i2c0-sleep-pins {
+ /* cci_i2c_sda0, cci_i2c_scl0 */
+ pins = "gpio101", "gpio102";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci0_i2c1_sleep: cci0-i2c1-sleep-pins {
+ /* cci_i2c_sda1, cci_i2c_scl1 */
+ pins = "gpio103", "gpio104";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
+ cci1_default: cci1-default-state {
+ cci1_i2c0_default: cci1-i2c0-default-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ cci1_i2c1_default: cci1-i2c1-default-pins {
+ /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
+ pins = "gpio235","gpio236";
+ function = "aon_cci";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+ };
+
+ cci1_sleep: cci1-sleep-state {
+ cci1_i2c0_sleep: cci1-i2c0-sleep-pins {
+ /* cci_i2c_sda2, cci_i2c_scl2 */
+ pins = "gpio105","gpio106";
+ function = "cci_i2c";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ cci1_i2c1_sleep: cci1-i2c1-sleep-pins {
+ /* aon_cci_i2c_sda3, aon_cci_i2c_scl3 */
+ pins = "gpio235","gpio236";
+ function = "aon_cci";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+ };
+
qup_i2c0_data_clk: qup-i2c0-data-clk-state {
/* SDA, SCL */
pins = "gpio0", "gpio1";
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v4 4/4] arm64: dts: qcom: x1e80100: Add CAMSS block definition
2025-01-19 0:54 [PATCH v4 0/4] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
` (2 preceding siblings ...)
2025-01-19 0:54 ` [PATCH v4 3/4] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
@ 2025-01-19 0:54 ` Bryan O'Donoghue
3 siblings, 0 replies; 10+ messages in thread
From: Bryan O'Donoghue @ 2025-01-19 0:54 UTC (permalink / raw)
To: Loic Poulain, Robert Foss, Andi Shyti, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Vladimir Zapolskiy, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Bryan O'Donoghue, Konrad Dybcio
Add dtsi to describe the xe180100 CAMSS block
4 x CSIPHY
2 x CSID
2 x CSID Lite
2 x IFE
2 x IFE Lite
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 185 +++++++++++++++++++++++++++++++++
1 file changed, 185 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index de05916e6f295..ebfcb3d60d9fb 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5188,6 +5188,191 @@ cci1_i2c1: i2c-bus@1 {
};
};
+ camss: isp@acb6000 {
+ compatible = "qcom,x1e80100-camss";
+
+ reg = <0 0x0acb6000 0 0x1000>,
+ <0 0x0acb7000 0 0x2000>,
+ <0 0x0acb9000 0 0x2000>,
+ <0 0x0acbb000 0 0x2000>,
+ <0 0x0acc6000 0 0x1000>,
+ <0 0x0acca000 0 0x1000>,
+ <0 0x0ace4000 0 0x2000>,
+ <0 0x0ace6000 0 0x2000>,
+ <0 0x0ace8000 0 0x2000>,
+ <0 0x0acec000 0 0x2000>,
+ <0 0x0acf6000 0 0x1000>,
+ <0 0x0acf7000 0 0x1000>,
+ <0 0x0acf8000 0 0x1000>,
+ <0 0x0acc7000 0 0x2000>,
+ <0 0x0accb000 0 0x2000>,
+ <0 0x0ac62000 0 0x4000>,
+ <0 0x0ac71000 0 0x4000>;
+ reg-names = "csid_wrapper",
+ "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "csitpg0",
+ "csitpg1",
+ "csitpg2",
+ "vfe_lite0",
+ "vfe_lite1",
+ "vfe0",
+ "vfe1";
+
+ clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
+ <&camcc CAM_CC_CAMNOC_AXI_NRT_CLK>,
+ <&camcc CAM_CC_CORE_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_0_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_1_CLK>,
+ <&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
+ <&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+ <&camcc CAM_CC_CSID_CLK>,
+ <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
+ <&camcc CAM_CC_CSIPHY0_CLK>,
+ <&camcc CAM_CC_CSI0PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY1_CLK>,
+ <&camcc CAM_CC_CSI1PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY2_CLK>,
+ <&camcc CAM_CC_CSI2PHYTIMER_CLK>,
+ <&camcc CAM_CC_CSIPHY4_CLK>,
+ <&camcc CAM_CC_CSI4PHYTIMER_CLK>,
+ <&gcc GCC_CAMERA_HF_AXI_CLK>,
+ <&gcc GCC_CAMERA_SF_AXI_CLK>,
+ <&camcc CAM_CC_IFE_0_CLK>,
+ <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_1_CLK>,
+ <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CLK>,
+ <&camcc CAM_CC_IFE_LITE_AHB_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
+ <&camcc CAM_CC_IFE_LITE_CSID_CLK>;
+ clock-names = "camnoc_rt_axi",
+ "camnoc_nrt_axi",
+ "core_ahb",
+ "cpas_ahb",
+ "cpas_fast_ahb",
+ "cpas_vfe0",
+ "cpas_vfe1",
+ "cpas_vfe_lite",
+ "cphy_rx_clk_src",
+ "csid",
+ "csid_csiphy_rx",
+ "csiphy0",
+ "csiphy0_timer",
+ "csiphy1",
+ "csiphy1_timer",
+ "csiphy2",
+ "csiphy2_timer",
+ "csiphy4",
+ "csiphy4_timer",
+ "gcc_axi_hf",
+ "gcc_axi_sf",
+ "vfe0",
+ "vfe0_fast_ahb",
+ "vfe1",
+ "vfe1_fast_ahb",
+ "vfe_lite",
+ "vfe_lite_ahb",
+ "vfe_lite_cphy_rx",
+ "vfe_lite_csid";
+
+ interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "csid0",
+ "csid1",
+ "csid2",
+ "csid_lite0",
+ "csid_lite1",
+ "csiphy0",
+ "csiphy1",
+ "csiphy2",
+ "csiphy4",
+ "vfe0",
+ "vfe1",
+ "vfe_lite0",
+ "vfe_lite1";
+
+ interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
+ <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "cam_ahb",
+ "cam_hf_mnoc",
+ "cam_sf_mnoc",
+ "cam_sf_icp_mnoc";
+
+ iommus = <&apps_smmu 0x800 0x60>,
+ <&apps_smmu 0x860 0x60>,
+ <&apps_smmu 0x1800 0x60>,
+ <&apps_smmu 0x1860 0x60>,
+ <&apps_smmu 0x18e0 0x00>,
+ <&apps_smmu 0x1900 0x00>,
+ <&apps_smmu 0x1980 0x20>,
+ <&apps_smmu 0x19a0 0x20>;
+
+ power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
+ <&camcc CAM_CC_IFE_1_GDSC>,
+ <&camcc CAM_CC_TITAN_TOP_GDSC>;
+ power-domain-names = "ife0",
+ "ife1",
+ "top";
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@1 {
+ reg = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@2 {
+ reg = <2>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ port@3 {
+ reg = <3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+ };
+
camcc: clock-controller@ade0000 {
compatible = "qcom,x1e80100-camcc";
reg = <0 0x0ade0000 0 0x20000>;
--
2.47.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/4] arm64: dts: qcom: x1e80100: Add CAMCC block definition
2025-01-19 0:54 ` [PATCH v4 2/4] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
@ 2025-03-10 10:44 ` Vladimir Zapolskiy
0 siblings, 0 replies; 10+ messages in thread
From: Vladimir Zapolskiy @ 2025-03-10 10:44 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Konrad Dybcio
Hello Bryan.
On 1/19/25 02:54, Bryan O'Donoghue wrote:
> Add the CAMCC block for x1e80100. The x1e80100 CAMCC block is an iteration
> of previous CAMCC blocks with the exception of having two required
> power-domains not just one.
>
> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> arch/arm64/boot/dts/qcom/x1e80100.dtsi | 16 ++++++++++++++++
> 1 file changed, 16 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> index 9d38436763432..10035bcfa89bb 100644
> --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
> @@ -5,6 +5,7 @@
>
> #include <dt-bindings/clock/qcom,rpmh.h>
> #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h>
> +#include <dt-bindings/clock/qcom,x1e80100-camcc.h>
> #include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
> #include <dt-bindings/clock/qcom,x1e80100-gcc.h>
> #include <dt-bindings/clock/qcom,x1e80100-gpucc.h>
> @@ -5109,6 +5110,21 @@ usb_1_ss1_dwc3_ss: endpoint {
> };
> };
>
> + camcc: clock-controller@ade0000 {
> + compatible = "qcom,x1e80100-camcc";
> + reg = <0 0x0ade0000 0 0x20000>;
> + clocks = <&gcc GCC_CAMERA_AHB_CLK>,
> + <&bi_tcxo_div2>,
> + <&bi_tcxo_ao_div2>,
> + <&sleep_clk>;
> + power-domains = <&rpmhpd RPMHPD_MXC>,
> + <&rpmhpd RPMHPD_MMCX>;
> + required-opps = <&rpmhpd_opp_low_svs>;
Since I believe here is the error in the device tree bindings, it makes
sense to fix it before adding the clock controller into the platform dtsi
file, please review the proposed change:
https://lore.kernel.org/all/20250304143152.1799966-1-vladimir.zapolskiy@linaro.org/
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + };
> +
> mdss: display-subsystem@ae00000 {
> compatible = "qcom,x1e80100-mdss";
> reg = <0 0x0ae00000 0 0x1000>;
>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 3/4] arm64: dts: qcom: x1e80100: Add CCI definitions
2025-01-19 0:54 ` [PATCH v4 3/4] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
@ 2025-03-10 21:15 ` Vladimir Zapolskiy
0 siblings, 0 replies; 10+ messages in thread
From: Vladimir Zapolskiy @ 2025-03-10 21:15 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Konrad Dybcio
Hi Bryan.
On 1/19/25 02:54, Bryan O'Donoghue wrote:
> Add in two CCI busses.
>
> One bus has two CCI bus master pinouts:
> cci_i2c_scl0 = gpio102
> cci_i2c_sda0 = gpio101
> cci_i2c_scl1 = gpio104
> cci_i2c_sda1 = gpio103
>
> The second bus has two CCI bus master pinouts:
> cci_i2c_scl2 = gpio106
> cci_i2c_sda2 = gpio105
> aon_cci_i2c_scl3 = gpio236
> aon_cci_i2c_sda3 = gpio235
Nitpick, please consider to swap SDA/SCL everywhere above, this will convert
the list of GPIO pads into a neat alphanumerically sorted list.
>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss
2025-01-19 0:54 ` [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
@ 2025-03-10 21:35 ` Vladimir Zapolskiy
2025-03-11 21:53 ` Vladimir Zapolskiy
2025-03-11 21:56 ` Vladimir Zapolskiy
2 siblings, 0 replies; 10+ messages in thread
From: Vladimir Zapolskiy @ 2025-03-10 21:35 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Krzysztof Kozlowski
Hi Bryan.
On 1/19/25 02:54, Bryan O'Donoghue wrote:
> Add bindings for qcom,x1e80100-camss in order to support the camera
> subsystem for x1e80100 as found in various Co-Pilot laptops.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> ---
> .../bindings/media/qcom,x1e80100-camss.yaml | 367 +++++++++++++++++++++
> 1 file changed, 367 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
> new file mode 100644
> index 0000000000000..88eeac262f0e2
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
> @@ -0,0 +1,367 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/media/qcom,x1e80100-camss.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm X1E80100 Camera Subsystem (CAMSS)
> +
> +maintainers:
> + - Bryan O'Donoghue <bryan.odonoghue@linaro.org>
> +
> +description: |
Please drop '|' here.
> + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
> +
<snip>
> +
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: cam_ahb
> + - const: cam_hf_mnoc
> + - const: cam_sf_mnoc
> + - const: cam_sf_icp_mnoc
Once Krzysztof objected to the "cam_" prefix in the interconnect names,
and it's a pretty reasonable comment, and also it's been applied for
sc7280-camss and sm8550-camss:
https://lore.kernel.org/all/087e7f29-1fa8-4bc2-bb3d-acb941432381@kernel.org/
<snip>
> +
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-3]+$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
It's a smart enumeration, nice to see it.
After minor updates done,
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss
2025-01-19 0:54 ` [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
2025-03-10 21:35 ` Vladimir Zapolskiy
@ 2025-03-11 21:53 ` Vladimir Zapolskiy
2025-03-11 21:56 ` Vladimir Zapolskiy
2 siblings, 0 replies; 10+ messages in thread
From: Vladimir Zapolskiy @ 2025-03-11 21:53 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Krzysztof Kozlowski
Hi Bryan.
On 1/19/25 02:54, Bryan O'Donoghue wrote:
> Add bindings for qcom,x1e80100-camss in order to support the camera
> subsystem for x1e80100 as found in various Co-Pilot laptops.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
<snip>
> +
> + reg-names:
> + items:
> + - const: csid_wrapper
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy4
> + - const: csitpg0
> + - const: csitpg1
> + - const: csitpg2
> + - const: vfe_lite0
> + - const: vfe_lite1
> + - const: vfe0
> + - const: vfe1
Here I'm a bit lost about the selected ordering rule, I kindly
ask for a clarification.
In ASCII the underscore symbol '_' goes way after any 7-bit symbols
including '0' and other digits, but this is violated in the sorting
order above.
The expected sorting order would rather be like this one:
- const: csid0
- const: csid1
- const: csid2
- const: csid_lite0
- const: csid_lite1
- const: csid_wrapper
- const: csiphy0
- const: csiphy1
- const: csiphy2
- const: csiphy4
- const: csitpg0
- const: csitpg1
- const: csitpg2
- const: vfe0
- const: vfe1
- const: vfe_lite0
- const: vfe_lite1
> +
> + clocks:
> + maxItems: 29
> +
> + clock-names:
> + items:
> + - const: camnoc_rt_axi
> + - const: camnoc_nrt_axi
Okay, there might be some explanations about the underscore symbol,
anyway I would appreciate to get them, but here it's definitely
incorrect, it's very unlikely that the symbol 'r' precedes 'n'.
> + - const: core_ahb
> + - const: cpas_ahb
> + - const: cpas_fast_ahb
> + - const: cpas_vfe0
> + - const: cpas_vfe1
> + - const: cpas_vfe_lite
> + - const: cphy_rx_clk_src
> + - const: csid
> + - const: csid_csiphy_rx
> + - const: csiphy0
> + - const: csiphy0_timer
> + - const: csiphy1
> + - const: csiphy1_timer
> + - const: csiphy2
> + - const: csiphy2_timer
> + - const: csiphy4
> + - const: csiphy4_timer
> + - const: gcc_axi_hf
> + - const: gcc_axi_sf
> + - const: vfe0
> + - const: vfe0_fast_ahb
> + - const: vfe1
> + - const: vfe1_fast_ahb
> + - const: vfe_lite
> + - const: vfe_lite_ahb
> + - const: vfe_lite_cphy_rx
> + - const: vfe_lite_csid
> +
> + interrupts:
> + maxItems: 13
> +
> + interrupt-names:
> + items:
> + - const: csid0
> + - const: csid1
> + - const: csid2
> + - const: csid_lite0
> + - const: csid_lite1
> + - const: csiphy0
> + - const: csiphy1
> + - const: csiphy2
> + - const: csiphy4
> + - const: vfe0
> + - const: vfe1
> + - const: vfe_lite0
> + - const: vfe_lite1
Same as above.
> + interconnects:
> + maxItems: 4
> +
> + interconnect-names:
> + items:
> + - const: cam_ahb
> + - const: cam_hf_mnoc
> + - const: cam_sf_mnoc
> + - const: cam_sf_icp_mnoc
> +
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss
2025-01-19 0:54 ` [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
2025-03-10 21:35 ` Vladimir Zapolskiy
2025-03-11 21:53 ` Vladimir Zapolskiy
@ 2025-03-11 21:56 ` Vladimir Zapolskiy
2 siblings, 0 replies; 10+ messages in thread
From: Vladimir Zapolskiy @ 2025-03-11 21:56 UTC (permalink / raw)
To: Bryan O'Donoghue, Loic Poulain, Robert Foss, Andi Shyti,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Todor Tomov,
Mauro Carvalho Chehab, Bjorn Andersson, Michael Turquette,
Stephen Boyd, Jagadeesh Kona, Konrad Dybcio
Cc: linux-i2c, linux-arm-msm, devicetree, linux-kernel, linux-media,
linux-clk, Krzysztof Kozlowski
On 1/19/25 02:54, Bryan O'Donoghue wrote:
> Add bindings for qcom,x1e80100-camss in order to support the camera
> subsystem for x1e80100 as found in various Co-Pilot laptops.
>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
<snip>
> + ports:
> + $ref: /schemas/graph.yaml#/properties/ports
> +
> + description:
> + CSI input ports.
> +
> + patternProperties:
> + "^port@[0-3]+$":
> + $ref: /schemas/graph.yaml#/$defs/port-base
> + unevaluatedProperties: false
> +
> + description:
> + Input port for receiving CSI data from a CSIPHY.
> +
> + properties:
> + endpoint:
> + $ref: video-interfaces.yaml#
> + unevaluatedProperties: false
> +
> + properties:
> + clock-lanes:
> + maxItems: 1
> +
> + data-lanes:
> + minItems: 1
> + maxItems: 4
> +
> + required:
> + - clock-lanes
> + - data-lanes
> +
bus-type property of the endpoint is missing.
--
Best wishes,
Vladimir
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-03-11 21:56 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-01-19 0:54 [PATCH v4 0/4] Add dt-bindings and dtsi changes for CAMSS on x1e80100 silicon Bryan O'Donoghue
2025-01-19 0:54 ` [PATCH v4 1/4] dt-bindings: media: Add qcom,x1e80100-camss Bryan O'Donoghue
2025-03-10 21:35 ` Vladimir Zapolskiy
2025-03-11 21:53 ` Vladimir Zapolskiy
2025-03-11 21:56 ` Vladimir Zapolskiy
2025-01-19 0:54 ` [PATCH v4 2/4] arm64: dts: qcom: x1e80100: Add CAMCC block definition Bryan O'Donoghue
2025-03-10 10:44 ` Vladimir Zapolskiy
2025-01-19 0:54 ` [PATCH v4 3/4] arm64: dts: qcom: x1e80100: Add CCI definitions Bryan O'Donoghue
2025-03-10 21:15 ` Vladimir Zapolskiy
2025-01-19 0:54 ` [PATCH v4 4/4] arm64: dts: qcom: x1e80100: Add CAMSS block definition Bryan O'Donoghue
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