From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
agross@kernel.org
Cc: andersson@kernel.org, luca@z3ntu.xyz,
dmitry.baryshkov@linaro.org, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org,
robdclark@gmail.com, linux-arm-msm@vger.kernel.org,
iommu@lists.linux.dev, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, kernel@collabora.com
Subject: Re: [PATCH v5 3/6] iommu/qcom: Disable and reset context bank before programming
Date: Thu, 22 Jun 2023 11:32:49 +0200 [thread overview]
Message-ID: <79413af7-da90-6503-c939-a24fc6f273b4@linaro.org> (raw)
In-Reply-To: <20230622092742.74819-4-angelogioacchino.delregno@collabora.com>
On 22.06.2023 11:27, AngeloGioacchino Del Regno wrote:
> Writing the new TTBRs, TCRs and MAIRs on a previously enabled
> context bank may trigger a context fault, resulting in firmware
> driven AP resets: change the domain initialization programming
> sequence to disable the context bank(s) and to also clear the
> related fault address (CB_FAR) and fault status (CB_FSR)
> registers before writing new values to TTBR0/1, TCR/TCR2, MAIR0/1.
>
> Fixes: 0ae349a0f33f ("iommu/qcom: Add qcom_iommu")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
> drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> index 8face57c4180..f1bd7c035db8 100644
> --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c
> @@ -273,6 +273,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain,
> ctx->secure_init = true;
> }
>
> + /* Disable context bank before programming */
> + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
> +
> + /* Clear context bank fault address fault status registers */
> + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
> + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT);
> +
> /* TTBRs */
> iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
> pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
next prev parent reply other threads:[~2023-06-22 9:49 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-22 9:27 [PATCH v5 0/6] Add support for Qualcomm's legacy IOMMU v2 AngeloGioacchino Del Regno
2023-06-22 9:27 ` [PATCH v5 1/6] dt-bindings: iommu: qcom,iommu: Add qcom,ctx-asid property AngeloGioacchino Del Regno
2023-06-22 14:52 ` Rob Herring
2023-06-22 9:27 ` [PATCH v5 2/6] iommu/qcom: Use the asid read from device-tree if specified AngeloGioacchino Del Regno
2023-06-22 9:31 ` Konrad Dybcio
2023-08-01 13:49 ` Will Deacon
2023-08-01 14:02 ` AngeloGioacchino Del Regno
2023-06-22 9:27 ` [PATCH v5 3/6] iommu/qcom: Disable and reset context bank before programming AngeloGioacchino Del Regno
2023-06-22 9:32 ` Konrad Dybcio [this message]
2023-06-22 9:27 ` [PATCH v5 4/6] iommu/qcom: Index contexts by asid number to allow asid 0 AngeloGioacchino Del Regno
2023-06-22 9:35 ` Konrad Dybcio
2023-08-01 13:55 ` Will Deacon
2023-06-22 9:27 ` [PATCH v5 5/6] dt-bindings: iommu: qcom,iommu: Add QSMMUv2 and MSM8976 compatibles AngeloGioacchino Del Regno
2023-06-22 9:27 ` [PATCH v5 6/6] iommu/qcom: Add support for QSMMUv2 and QSMMU-500 secured contexts AngeloGioacchino Del Regno
2023-06-22 9:36 ` Konrad Dybcio
2023-08-11 11:44 ` [PATCH v5 0/6] Add support for Qualcomm's legacy IOMMU v2 Will Deacon
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