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[83.9.31.165]) by smtp.gmail.com with ESMTPSA id v21-20020a2e9915000000b002adb0164258sm1242072lji.112.2023.06.22.02.32.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 22 Jun 2023 02:32:51 -0700 (PDT) Message-ID: <79413af7-da90-6503-c939-a24fc6f273b4@linaro.org> Date: Thu, 22 Jun 2023 11:32:49 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v5 3/6] iommu/qcom: Disable and reset context bank before programming Content-Language: en-US To: AngeloGioacchino Del Regno , agross@kernel.org Cc: andersson@kernel.org, luca@z3ntu.xyz, dmitry.baryshkov@linaro.org, joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, robdclark@gmail.com, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com References: <20230622092742.74819-1-angelogioacchino.delregno@collabora.com> <20230622092742.74819-4-angelogioacchino.delregno@collabora.com> From: Konrad Dybcio In-Reply-To: <20230622092742.74819-4-angelogioacchino.delregno@collabora.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 22.06.2023 11:27, AngeloGioacchino Del Regno wrote: > Writing the new TTBRs, TCRs and MAIRs on a previously enabled > context bank may trigger a context fault, resulting in firmware > driven AP resets: change the domain initialization programming > sequence to disable the context bank(s) and to also clear the > related fault address (CB_FAR) and fault status (CB_FSR) > registers before writing new values to TTBR0/1, TCR/TCR2, MAIR0/1. > > Fixes: 0ae349a0f33f ("iommu/qcom: Add qcom_iommu") > Signed-off-by: AngeloGioacchino Del Regno > --- Reviewed-by: Konrad Dybcio Konrad > drivers/iommu/arm/arm-smmu/qcom_iommu.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/drivers/iommu/arm/arm-smmu/qcom_iommu.c b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > index 8face57c4180..f1bd7c035db8 100644 > --- a/drivers/iommu/arm/arm-smmu/qcom_iommu.c > +++ b/drivers/iommu/arm/arm-smmu/qcom_iommu.c > @@ -273,6 +273,13 @@ static int qcom_iommu_init_domain(struct iommu_domain *domain, > ctx->secure_init = true; > } > > + /* Disable context bank before programming */ > + iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0); > + > + /* Clear context bank fault address fault status registers */ > + iommu_writel(ctx, ARM_SMMU_CB_FAR, 0); > + iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); > + > /* TTBRs */ > iommu_writeq(ctx, ARM_SMMU_CB_TTBR0, > pgtbl_cfg.arm_lpae_s1_cfg.ttbr |