From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5875BC433EF for ; Mon, 23 May 2022 02:23:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229725AbiEWCXr (ORCPT ); Sun, 22 May 2022 22:23:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1352264AbiEWCXq (ORCPT ); Sun, 22 May 2022 22:23:46 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D23D3668E; Sun, 22 May 2022 19:23:41 -0700 (PDT) X-UUID: 2106b57dfb15452ab38b03e275ddf03e-20220523 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.5,REQID:82fb58b2-77f8-4c66-ae5f-cec585b30937,OB:0,LO B:0,IP:0,URL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACT ION:release,TS:25 X-CID-META: VersionHash:2a19b09,CLOUDID:9b92357a-5ef6-470b-96c9-bdb8ced32786,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,URL:1,File:nil ,QS:0,BEC:nil X-UUID: 2106b57dfb15452ab38b03e275ddf03e-20220523 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 493076538; Mon, 23 May 2022 10:23:36 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Mon, 23 May 2022 10:23:36 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Mon, 23 May 2022 10:23:36 +0800 Received: from mhfsdcap04 (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Mon, 23 May 2022 10:23:32 +0800 Message-ID: <79706876349c3670f8831e75f70722f0bca200cb.camel@mediatek.com> Subject: Re: [PATCH v9 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY From: Chunfeng Yun To: Jianjun Wang , Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Matthias Brugger , "Chen-Yu Tsai" , AngeloGioacchino Del Regno , Krzysztof Kozlowski CC: Wei-Shun Chang , , , , , , , , , , , Date: Mon, 23 May 2022 10:23:31 +0800 In-Reply-To: <20220520064920.27313-2-jianjun.wang@mediatek.com> References: <20220520064920.27313-1-jianjun.wang@mediatek.com> <20220520064920.27313-2-jianjun.wang@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, 2022-05-20 at 14:49 +0800, Jianjun Wang wrote: > Add YAML schema documentation for PCIe PHY on MediaTek chipsets. > > Signed-off-by: Jianjun Wang > Reviewed-by: Krzysztof Kozlowski > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > .../bindings/phy/mediatek,pcie-phy.yaml | 75 > +++++++++++++++++++ > 1 file changed, 75 insertions(+) > create mode 100644 > Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/mediatek,pcie- > phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,pcie- > phy.yaml > new file mode 100644 > index 000000000000..422750cc4121 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/mediatek,pcie-phy.yaml > @@ -0,0 +1,75 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/phy/mediatek,pcie-phy.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek PCIe PHY > + > +maintainers: > + - Jianjun Wang > + > +description: | > + The PCIe PHY supports physical layer functionality for PCIe Gen3 > port. > + > +properties: > + compatible: > + const: mediatek,mt8195-pcie-phy > + > + reg: > + maxItems: 1 > + > + reg-names: > + items: > + - const: sif > + > + "#phy-cells": > + const: 0 > + > + nvmem-cells: > + maxItems: 7 Seems no need 'maxItems', we can get it from items of 'nvmem-cell- names' > + description: > + Phandles to nvmem cell that contains the efuse data, if > unspecified, > + default value is used. > + > + nvmem-cell-names: > + items: > + - const: glb_intr > + - const: tx_ln0_pmos > + - const: tx_ln0_nmos > + - const: rx_ln0 > + - const: tx_ln1_pmos > + - const: tx_ln1_nmos > + - const: rx_ln1 > + > + power-domains: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - reg-names > + - "#phy-cells" > + > +additionalProperties: false > + > +examples: > + - | > + phy@11e80000 { > + compatible = "mediatek,mt8195-pcie-phy"; > + #phy-cells = <0>; > + reg = <0x11e80000 0x10000>; > + reg-names = "sif"; > + nvmem-cells = <&pciephy_glb_intr>, > + <&pciephy_tx_ln0_pmos>, > + <&pciephy_tx_ln0_nmos>, > + <&pciephy_rx_ln0>, > + <&pciephy_tx_ln1_pmos>, > + <&pciephy_tx_ln1_nmos>, > + <&pciephy_rx_ln1>; > + nvmem-cell-names = "glb_intr", "tx_ln0_pmos", > + "tx_ln0_nmos", "rx_ln0", > + "tx_ln1_pmos", "tx_ln1_nmos", > + "rx_ln1"; > + power-domains = <&spm 2>; > + };