From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F339248F7E; Tue, 27 May 2025 08:25:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748334359; cv=none; b=jfU8mhbvXnTMRiKLxgJ4W4xPf07TzKjACQ1xNKZoYLZnG8iapbCICaDqaPcL/mYDm7KJjF4SDd1oOtG6Dcwhuy106ahNW5aS4Adt73fMNtQ5gO2SivIqOAXIMMaF9m/3pvfZlBZSx0Tb9ghZjM9xww7THsA+/to2zVILs8IIj5c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748334359; c=relaxed/simple; bh=NwYxuhdKhAtS82rT21lXM3rwQbj/RLr2/4w6g3+066k=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=pYWL74/VOjGR2rfMTUfgjIqAUiPZhSqakswN/MJGVNgmaiT56B4dra9XFov3uPgR2v8ELYSwiUc1g6nBRXwQW6sH7qNaJy7Ba2MngyhlPV1fOMS2tpwlGnj0Jwmsh8VD3rpFZh5cCp7fsc8a7W1aI1VFBbsX0VbdT9H3pDrVaT4= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=qPgOnCVD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="qPgOnCVD" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49A8FC4CEE9; Tue, 27 May 2025 08:25:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748334358; bh=NwYxuhdKhAtS82rT21lXM3rwQbj/RLr2/4w6g3+066k=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=qPgOnCVDcUhDxtqz1Ktm1KLNFlEbvSKlr8Yj2bkXtansz3O5aQ+wB3eNQsIbSga7P DxWV0PPjNQZHotVNvt+Rm1ndQQAdR5Um4iE0Dxi8eQOs48WijuTB/rCMYTRi+zEVAf CmABlOjWjJFsAnivaaQaltqKumx1tp+naSZOdJxoqOnJPSYvqWUzCALhr1zQwYk7eR STPZAFQ81B7+KaoLKaF94W4OZGP9pURimDXH/xQ/O1JFjERkCAB9U0GJ2yTRWv70/H bcTYtkaCVsA8NkN7OW3UJg0V3Lq05wOHYMA1JmoTJnAqXRMlbIoO3i1jkMnOsd6t3K N6tmh7oi8txCQ== Message-ID: <79903ad6-0228-41a3-b733-415cc43ec786@kernel.org> Date: Tue, 27 May 2025 10:25:53 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 1/4] dt-bindings: mfd: rk806: allow to customize PMIC reset method To: Quentin Schulz , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz References: <20250526-rk8xx-rst-fun-v1-0-ea894d9474e0@cherry.de> <20250526-rk8xx-rst-fun-v1-1-ea894d9474e0@cherry.de> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 26/05/2025 19:05, Quentin Schulz wrote: > From: Quentin Schulz > > The RK806 PMIC (and RK809, RK817; but those aren't handled here) has a > bitfield for configuring the restart/reset behavior (which I assume > Rockchip calls "function") whenever the PMIC is reset (at least by > software; c.f. DEV_RST in the datasheet). > > For RK806, the following values are possible for RST_FUN: > > 0b00 means "restart PMU" > 0b01 means "Reset all the power off reset registers, forcing > the state to switch to ACTIVE mode" > 0b10 means "Reset all the power off reset registers, forcing > the state to switch to ACTIVE mode, and simultaneously > pull down the RESETB PIN for 5mS before releasing" > 0b11 means the same as for 0b10 just above. > > I don't believe this is suitable for a subsystem-generic property hence > let's make it a vendor property called rockchip,rst-fun. > > The first few sentences in the description of the property are > voluntarily generic so they could be copied to the DT binding for > RK809/RK817 whenever someone wants to implement that for those PMIC. > > Signed-off-by: Quentin Schulz > --- > .../devicetree/bindings/mfd/rockchip,rk806.yaml | 24 ++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml > index 3c2b06629b75ea94f90712470bf14ed7fc16d68d..0f931a6da93f7596eac89c5f0deb8ee3bd934c31 100644 > --- a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml > +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml > @@ -31,6 +31,30 @@ properties: > > system-power-controller: true > > + rockchip,rst-fun: > + $ref: /schemas/types.yaml#/definitions/uint32 > + enum: [0, 1, 2, 3] > + description: > + RST_FUN value to set for the PMIC. > + > + This is the value in the RST_FUN bitfield according to the > + datasheet. I.e. if RST_FUN is bits 6 and 7 and the desired value > + of RST_FUN is 1, this property needs to be set to 1 (and not 64, > + 0x40, or BIT(6)). > + > + The meaning of this value is specific to the PMIC and is > + explained in the datasheet. And why would that be exactly board-level configuration? IOW, I expect all boards to be reset in the same - correct and optimal - way. Looks close to SW policy. > + > + For RK806, the following applies > + > + 0b00 means "restart PMU" Use decimal numbers. > + 0b01 means "Reset all the power off reset registers, forcing > + the state to switch to ACTIVE mode" > + 0b10 means "Reset all the power off reset registers, forcing > + the state to switch to ACTIVE mode, and simultaneously > + pull down the RESETB PIN for 5mS before releasing" > + 0b11 means the same as for 0b10 just above. > + > vcc1-supply: > description: > The input supply for dcdc-reg1. > Best regards, Krzysztof