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AJvYcCU8SoppQiYQ3WmwA/7qB7RhY6Bkke6+VVXTO1hM6h9qYXsaO7s51RwDl3M5EYPP+GcD/QrdOZ/jWiB19lScSkp7LI12Yg6lV2cdyA== X-Gm-Message-State: AOJu0Yxm4w2btZTGqWd/HtGSowqrz1Qj35SFWpXub6GjH8G0Qjd9BKG9 Ka/DAyr1LPbt3C7ygjaO64hWYgsVY3OxCsYKgLpSdKqi57Ev0/1/WcPzsXn8H5g= X-Google-Smtp-Source: AGHT+IG7q7oi4YXSsJv2pPn8DgaqByv+geulrEaq3/D4qWFq4GHO/t+UK7v1odxUlJcJAkqeN1/hBw== X-Received: by 2002:a05:6512:3da3:b0:52c:e728:cca1 with SMTP id 2adb3069b0e04-52ce728cd5bmr11772828e87.39.1719562367184; Fri, 28 Jun 2024 01:12:47 -0700 (PDT) Received: from [192.168.50.4] ([82.78.167.70]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4256b0c17e6sm23433785e9.42.2024.06.28.01.12.45 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 28 Jun 2024 01:12:46 -0700 (PDT) Message-ID: <79c26030-4b92-4ef3-b8ce-d011f492161b@tuxon.dev> Date: Fri, 28 Jun 2024 11:12:45 +0300 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 07/12] i2c: riic: Define individual arrays to describe the register offsets Content-Language: en-US To: Biju Das , Chris Brandt , "andi.shyti@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "geert+renesas@glider.be" , "magnus.damm@gmail.com" , "mturquette@baylibre.com" , "sboyd@kernel.org" , "p.zabel@pengutronix.de" , "wsa+renesas@sang-engineering.com" Cc: "linux-renesas-soc@vger.kernel.org" , "linux-i2c@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-clk@vger.kernel.org" , Claudiu Beznea References: <20240625121358.590547-1-claudiu.beznea.uj@bp.renesas.com> <20240625121358.590547-8-claudiu.beznea.uj@bp.renesas.com> <6289f329-118f-4970-a525-75c3a48bd28b@tuxon.dev> <2f162986-33c5-4d80-958c-4f857adaad20@tuxon.dev> From: claudiu beznea In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 28.06.2024 11:09, Biju Das wrote: > > Hi Claudiu, > >> -----Original Message----- >> From: claudiu beznea >> Sent: Friday, June 28, 2024 9:03 AM >> Subject: Re: [PATCH v2 07/12] i2c: riic: Define individual arrays to describe the register offsets >> >> >> >> On 28.06.2024 10:55, Biju Das wrote: >>> Hi Claudiu, >>> >>>> -----Original Message----- >>>> From: claudiu beznea >>>> Sent: Friday, June 28, 2024 8:32 AM >>>> Subject: Re: [PATCH v2 07/12] i2c: riic: Define individual arrays to >>>> describe the register offsets >>>> >>>> Hi, Biju, >>>> >>>> On 28.06.2024 08:59, Biju Das wrote: >>>>> Hi Claudiu, >>>>> >>>>>> -----Original Message----- >>>>>> From: Claudiu >>>>>> Sent: Tuesday, June 25, 2024 1:14 PM >>>>>> Subject: [PATCH v2 07/12] i2c: riic: Define individual arrays to >>>>>> describe the register offsets >>>>>> >>>>>> From: Claudiu Beznea >>>>>> >>>>>> Define individual arrays to describe the register offsets. In this >>>>>> way we can describe different IP variants that share the same >>>>>> register offsets but have differences in other characteristics. >>>>>> Commit prepares for the addition >>>> of fast mode plus. >>>>>> >>>>>> Signed-off-by: Claudiu Beznea >>>>>> --- >>>>>> >>>>>> Changes in v2: >>>>>> - none >>>>>> >>>>>> drivers/i2c/busses/i2c-riic.c | 58 >>>>>> +++++++++++++++++++---------------- >>>>>> 1 file changed, 31 insertions(+), 27 deletions(-) >>>>>> >>>>>> diff --git a/drivers/i2c/busses/i2c-riic.c >>>>>> b/drivers/i2c/busses/i2c-riic.c index >>>>>> 9fe007609076..8ffbead95492 100644 >>>>>> --- a/drivers/i2c/busses/i2c-riic.c >>>>>> +++ b/drivers/i2c/busses/i2c-riic.c >>>>>> @@ -91,7 +91,7 @@ enum riic_reg_list { }; >>>>>> >>>>>> struct riic_of_data { >>>>>> - u8 regs[RIIC_REG_END]; >>>>>> + const u8 *regs; >>>>> >>>>> >>>>> Since you are touching this part, can we drop struct and Use u8* as >>>>> device_data instead? >>>> >>>> Patch 09/12 "i2c: riic: Add support for fast mode plus" adds a new member to struct >> riic_of_data. >>>> That new member is needed to differentiate b/w hardware versions >>>> supporting fast mode plus based on compatible. >>> >>> Are we sure RZ/A does not support fast mode plus? >> >> From commit description of patch 09/12: >> >> Fast mode plus is available on most of the IP variants that RIIC driver is working with. The >> exception is (according to HW manuals of the SoCs where this IP is available) the Renesas RZ/A1H. >> For this, patch introduces the struct riic_of_data::fast_mode_plus. >> >> I checked the manuals of all the SoCs where this driver is used. >> >> I haven't checked the H/W manual? >> >> On the manual I've downloaded from Renesas web site the FMPE bit of RIICnFER is not available on >> RZ/A1H. > > I just found RZ/A2M manual, it supports FMP and register layout looks similar to RZ/G2L. I introduced struct riic_of_data::fast_mode_plus because of RZ/A1H. > Wolfram tested it with r7s72100 genmai board acessing an eeprom. Not sure is it RZ/A1 or RZ/A2? > > Cheers, > Biju >