From: Krzysztof Kozlowski <krzk@kernel.org>
To: E Shattow <e@freeshell.de>,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, Rob Herring <robh@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Subject: Re: [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC
Date: Mon, 23 Jun 2025 08:45:04 +0200 [thread overview]
Message-ID: <79d84bc5-1b39-433d-afc3-b6ca84f274f0@kernel.org> (raw)
In-Reply-To: <20250606130253.1105273-2-e@freeshell.de>
On 06/06/2025 15:02, E Shattow wrote:
> Document bindings for the JH7110 SoC DMC as implemented in downstream
> U-Boot driver starfive_ddr.c
Heh, I totally missed "downstream"... We do not add bindings for
downstream. We do not care about downstream, so I should not spend my
time on this.
Do not send code for downstream.
Best regards,
Krzysztof
next prev parent reply other threads:[~2025-06-23 6:45 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-06 13:02 [PATCH v1 0/3] riscv: dts: starfive: jh7110: More U-Boot downstream changes for JH7110 E Shattow
2025-06-06 13:02 ` [PATCH v1 1/3] dt-bindings: memory-controllers: add StarFive JH7110 SoC DMC E Shattow
2025-06-23 6:44 ` Krzysztof Kozlowski
2025-06-23 6:45 ` Krzysztof Kozlowski [this message]
2025-06-23 15:56 ` Conor Dooley
2025-06-23 16:11 ` Krzysztof Kozlowski
2025-06-06 13:02 ` [PATCH v1 2/3] riscv: dts: starfive: jh7110: add memory controller node E Shattow
2025-06-06 13:02 ` [PATCH v1 3/3] riscv: dts: starfive: jh7110: bootph-pre-ram hinting needed by boot loader E Shattow
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