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[98.57.15.22]) by smtp.gmail.com with ESMTPSA id 006d021491bc7-5c4149c37c4sm153200eaf.42.2024.06.27.21.39.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Jun 2024 21:39:12 -0700 (PDT) Message-ID: <79e57338-1671-4574-b1e2-3b3aa9045ec9@gmail.com> Date: Thu, 27 Jun 2024 23:39:10 -0500 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 8/8] arm64: dts: qcom: ipq9574: add PCIe2 and PCIe3 nodes To: Manivannan Sadhasivam Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, quic_kathirav@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org References: <20240501040800.1542805-1-mr.nuke.me@gmail.com> <20240501040800.1542805-9-mr.nuke.me@gmail.com> <20240624041832.GD10250@thinkpad> Content-Language: en-US From: "Alex G." In-Reply-To: <20240624041832.GD10250@thinkpad> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 6/23/24 23:18, Manivannan Sadhasivam wrote: > On Tue, Apr 30, 2024 at 11:07:50PM -0500, Alexandru Gagniuc wrote: >> On ipq9574, there are 4 PCIe controllers. Describe the pcie2 and pcie3 >> nodes, and their PHYs in devicetree. >> >> The pcie0 and pcie1 controllers use a gen3x1 PHY, which is not >> currently supported. Hence, only pcie2 and pcie3 are described. Only >> pcie2 was tested because my devboard only has conenctions to pcie2. >> >> Signed-off-by: Alexandru Gagniuc >> --- >> arch/arm64/boot/dts/qcom/ipq9574.dtsi | 178 +++++++++++++++++++++++++- >> 1 file changed, 176 insertions(+), 2 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> index 7f2e5cbf3bbb..c391886cf9ab 100644 >> --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi >> @@ -300,8 +300,8 @@ gcc: clock-controller@1800000 { >> <0>, >> <0>, >> <0>, >> - <0>, >> - <0>, >> + <&pcie2_phy>, >> + <&pcie3_phy>, >> <0>; >> #clock-cells = <1>; >> #reset-cells = <1>; >> @@ -745,6 +745,180 @@ frame@b128000 { >> status = "disabled"; >> }; >> }; >> + >> + pcie2_phy: phy@8c000 { >> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; >> + reg = <0x0008c000 0x14f4>; >> + >> + clocks = <&gcc GCC_PCIE2_AUX_CLK>, >> + <&gcc GCC_PCIE2_AHB_CLK>, >> + <&gcc GCC_PCIE2_PIPE_CLK>; >> + clock-names = "aux", >> + "cfg_ahb", >> + "pipe"; >> + >> + clock-output-names = "pcie_phy2_pipe_clk"; >> + #clock-cells = <0>; >> + #phy-cells = <0>; >> + >> + resets = <&gcc GCC_PCIE2_PHY_BCR>, >> + <&gcc GCC_PCIE2PHY_PHY_BCR>; >> + reset-names = "phy", >> + "common"; >> + status = "disabled"; >> + }; >> + >> + pcie3_phy: phy@f4000 { >> + compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy"; >> + reg = <0x000f4000 0x14f4>; >> + >> + clocks = <&gcc GCC_PCIE3_AUX_CLK>, >> + <&gcc GCC_PCIE3_AHB_CLK>, >> + <&gcc GCC_PCIE3_PIPE_CLK>; >> + clock-names = "aux", >> + "cfg_ahb", >> + "pipe"; >> + >> + clock-output-names = "pcie_phy3_pipe_clk"; >> + #clock-cells = <0>; >> + #phy-cells = <0>; >> + >> + resets = <&gcc GCC_PCIE3_PHY_BCR>, >> + <&gcc GCC_PCIE3PHY_PHY_BCR>; >> + reset-names = "phy", >> + "common"; >> + status = "disabled"; >> + }; >> + >> + /* TODO: Populate pcie0/pcie1 when gen3x1 phy support is added. */ >> + >> + pcie2: pcie@20000000 { >> + compatible = "qcom,pcie-ipq9574"; >> + reg = <0x20000000 0xf1d>, >> + <0x20000f20 0xa8>, >> + <0x20001000 0x1000>, >> + <0x00088000 0x4000>, >> + <0x20100000 0x1000>; >> + reg-names = "dbi", "elbi", "atu", "parf", "config"; >> + >> + ranges = <0x81000000 0x0 0x20200000 0x20200000 0x0 0x00100000>, >> + <0x82000000 0x0 0x20300000 0x20300000 0x0 0x07d00000>; > > Please cross check 'ranges' property with other platforms. > > > Cross check 'interrupt-map' as well. I'm not seeing the smoking gun. What am I looking for? Alex