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charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-ORIG-GUID: Ur5GIsbpaO27DzSJCs7eo7OFs0XTCIe9 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDExMDAxOCBTYWx0ZWRfXx9Th2k4x1pHp fezHMyL4iJXbbzGrusULU5MUEFjGX3/kPfx3eC75VOgyHJQ6wnE2LJ7FbOqHJNTmxvsHzOgOjMB 5KW1HR1CS4O/uPh/emwAzObbO+yrYU+UrQ9wFblL5CHJIZpgYaBx8n6yL3uxuvT61uzhz6xLc+i JwTx4kP3T1bsCcbi/UyzFtQYB8dgxCfne3omCKRkmoMy2cKW64097zmkbb8wMZBpNRrkccMjC68 eJLYNnwsoU1dtvYpuzqcP8HlATVpLb8IE4AceOk+rOeGFRapsR07hFR/ej4W9nOuKdl9lUQ6h4k 75lh2yiK05s75fw3Qq3NqArFCG5A9yiMfBw1msh/CKLQkk5LizeGV9C26T0AThAXSxOm00Ako3g /EwaUf7aMUMozCEfMOufRAtjdaoQIA== X-Proofpoint-GUID: Ur5GIsbpaO27DzSJCs7eo7OFs0XTCIe9 X-Authority-Analysis: v=2.4 cv=PdTyRyhd c=1 sm=1 tr=0 ts=68ecc692 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=x6icFKpwvdMA:10 a=EUspDBNiAAAA:8 a=49XlnRG1adklC0iOWOYA:9 a=QEXdDO2ut3YA:10 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-13_03,2025-10-06_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1011 adultscore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510110018 On 9/25/2025 3:55 PM, Konrad Dybcio wrote: > On 9/25/25 8:32 AM, Pankaj Patil wrote: >> From: Maulik Shah >> >> Add CPU power domains > > The commit message could say something about what kind of states > are being added, what their impact on the running system is, etc.. This will be squashed with cpus node. > > [...] > >> + idle-states { >> + entry-method = "psci"; >> + >> + CLUSTER0_C4: cpu-sleep-0 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "ret"; >> + arm,psci-suspend-param = <0x00000004>; >> + entry-latency-us = <180>; >> + exit-latency-us = <320>; >> + min-residency-us = <1000>; >> + }; >> + >> + CLUSTER1_C4: cpu-sleep-1 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "ret"; >> + arm,psci-suspend-param = <0x00000004>; >> + entry-latency-us = <180>; >> + exit-latency-us = <320>; >> + min-residency-us = <1000>; >> + }; >> + >> + CLUSTER2_C4: cpu-sleep-2 { >> + compatible = "arm,idle-state"; >> + idle-state-name = "ret"; >> + arm,psci-suspend-param = <0x00000004>; >> + entry-latency-us = <180>; >> + exit-latency-us = <320>; >> + min-residency-us = <1000>; >> + }; > > All three are identical (should they be?), just call it CPU_C4 and de- > duplicate it (unless the framework would read that as "all CPUs in the > system must sleep at the same time" which I don't know if it would) Updated to call cpu_c4, cluster_cl5 and domain_ss3 (inline with SM8750). > >> + >> + cluster0_cl5: cluster-sleep-0 { >> + compatible = "domain-idle-state"; >> + idle-state-name = "ret"; >> + arm,psci-suspend-param = <0x01000054>; >> + entry-latency-us = <2000>; >> + exit-latency-us = <2000>; >> + min-residency-us = <9000>; >> + }; >> + >> + cluster1_cl5: cluster-sleep-1 { >> + compatible = "domain-idle-state"; >> + idle-state-name = "ret"; >> + arm,psci-suspend-param = <0x01000054>; >> + entry-latency-us = <2000>; >> + exit-latency-us = <2000>; >> + min-residency-us = <9000>; >> + }; >> + >> + cluster2_cl5: cluster-sleep-2 { >> + compatible = "domain-idle-state"; >> + idle-state-name = "ret"; >> + arm,psci-suspend-param = <0x01000054>; >> + entry-latency-us = <2000>; >> + exit-latency-us = <2000>; >> + min-residency-us = <9000>; >> + }; > > ditto Updated in next revision. > >> + >> + APSS_OFF: cluster-ss3 { > > labels must be lowercase Updated in next revision. > >> + compatible = "domain-idle-state"; >> + idle-state-name = "apps-pc"; >> + entry-latency-us = <2800>; >> + exit-latency-us = <4400>; >> + min-residency-us = <10150>; >> + arm,psci-suspend-param = <0x0200C354>; > > lowercase hex, please > > also, this node oddly puts arm,psci-suspend-param at a different place, > please align it with the prvious ones Both updated in next revision. > > [...] > >> + CLUSTER3_PD: power-domain-cpu-cluster3 { > > "SYSTEM_PD"? Updated in next revision. >> + #power-domain-cells = <0>; >> + domain-idle-states = <&APSS_OFF>; > > Does it make sense to include some shallower idle states? Shallower idle states for cluster (CL4) and system (SS1) did not give benefits for power/performance. Thanks, Maulik > > Konrad