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([2a01:e0a:e17:9700:16d2:7456:6634:9626]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-439069290c7sm87180725e9.0.2025.02.07.01.21.20 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Feb 2025 01:21:21 -0800 (PST) Message-ID: <7aace8a9-0e62-4156-9c50-f7b399c4eba2@rivosinc.com> Date: Fri, 7 Feb 2025 10:21:20 +0100 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 06/21] RISC-V: Add Smcntrpmf extension parsing To: Atish Patra , Paul Walmsley , Palmer Dabbelt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Anup Patel , Atish Patra , Will Deacon , Mark Rutland , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , weilin.wang@intel.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Conor Dooley , devicetree@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org References: <20250205-counter_delegation-v4-0-835cfa88e3b1@rivosinc.com> <20250205-counter_delegation-v4-6-835cfa88e3b1@rivosinc.com> Content-Language: en-US From: =?UTF-8?B?Q2zDqW1lbnQgTMOpZ2Vy?= In-Reply-To: <20250205-counter_delegation-v4-6-835cfa88e3b1@rivosinc.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On 06/02/2025 08:23, Atish Patra wrote: > Smcntrpmf extension allows M-mode to enable privilege mode filtering > for cycle/instret counters. However, the cyclecfg/instretcfg CSRs are > only available only in Ssccfg only Smcntrpmf is present. > > That's why, kernel needs to detect presence of Smcntrpmf extension and > enable privilege mode filtering for cycle/instret counters. > > Signed-off-by: Atish Patra > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 3d6e706fc5b2..b4eddcb57842 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -102,6 +102,7 @@ > #define RISCV_ISA_EXT_SVADU 93 > #define RISCV_ISA_EXT_SSCSRIND 94 > #define RISCV_ISA_EXT_SMCSRIND 95 > +#define RISCV_ISA_EXT_SMCNTRPMF 96 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index c6da81aa48aa..8f225c9c3055 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -390,6 +390,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_BUNDLE(zvksg, riscv_zvksg_bundled_exts), > __RISCV_ISA_EXT_DATA(zvkt, RISCV_ISA_EXT_ZVKT), > __RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA), > + __RISCV_ISA_EXT_DATA(smcntrpmf, RISCV_ISA_EXT_SMCNTRPMF), > __RISCV_ISA_EXT_DATA(smcsrind, RISCV_ISA_EXT_SMCSRIND), > __RISCV_ISA_EXT_DATA(smmpm, RISCV_ISA_EXT_SMMPM), > __RISCV_ISA_EXT_SUPERSET(smnpm, RISCV_ISA_EXT_SMNPM, riscv_xlinuxenvcfg_exts), > Looks good to me. Reviewed-by: Clément Léger Thanks, Clément