* [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree
@ 2023-11-21 10:59 Neil Armstrong
2023-11-21 11:00 ` [PATCH v3 1/8] dt-bindings: arm: qcom: document SM8650 and the reference boards Neil Armstrong
` (7 more replies)
0 siblings, 8 replies; 15+ messages in thread
From: Neil Armstrong @ 2023-11-21 10:59 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong,
Krzysztof Kozlowski
This introduces the Device Tree for the recently announced Snapdragon 8 Gen 3
from Qualcomm, you can find the marketing specifications at:
https://docs.qualcomm.com/bundle/publicresource/87-71408-1_REV_B_Snapdragon_8_gen_3_Mobile_Platform_Product_Brief.pdf
Bindings and base Device Tree for the SM8650 SoC, MTP (Mobile Test Platform)
and QRD (Qualcommm Reference Device) are splited in two:
- 1-5: boot-to-shell first set that are only build-dependent on Clock bindings
- 6-8: multimedia second set that are build-dependent with Interconnect bindings
Features added and enabled:
- CPUs with CPUFREQ, SCPI idle states
- QICv3, IOMMU, Timers
- Interconnect NoCs with LLCC/CPU BWMONs
- SoC 3xTemperature Sensors
- Pinctrl/GPIO with PDC wakeup support
- Global, GPU, Display, TCSR Clock Controllers
- cDSP, aDSP and MPSS with SMP2P
- QuP/I2C Master Hub I2C and SPI controllers + GPI DMA
- PCIe 0/1
- USB2/USB3 with USB3/DP Combo PHY
- UFS with Inline Crypto Engine
- Crypto Engine + DMA and True Random Generator
- SDHCI
- Mobile Display Subsystem with 2xDSI output
- PMIC Glink (USB-PD UCSI + Altmode) provided by aDSP firmware
- GPIO and PMIC Buttons/LEDs on QRD board
- WCN7850 Bluetooth
- DSI + Touch panel
Bindings Dependencies:
- aoss-qmp: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-aoss-qmp-v1-1-8940621d704c@linaro.org/ - Reviewed
- bwmon: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-bwmon-v1-1-11efcdd8799e@linaro.org/ - Reviewed
- cpufreq: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-cpufreq-v1-1-31dec4887d14@linaro.org/ - Applied
- dwc3: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-bindings-dwc3-v2-1-60c0824fb835@linaro.org/ - Reviewed
- gpi: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-gpi-v2-1-4de85293d730@linaro.org/ - Reviewed
- ice: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-ice-v1-1-6b2bc14e71db@linaro.org/ - Applied
- ipcc: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-ipcc-v1-1-acca4318d06e@linaro.org/ - Reviewed
- pcie: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-pcie-v1-1-0e3d6f0c5827@linaro.org/ - Reviewed
- pcd: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-pdc-v1-1-42f62cc9858c@linaro.org/ - Reviewed
- pmic-glink: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-pmic-glink-v1-1-0c2829a62565@linaro.org/ - Reviewed
- qce: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-qce-v1-1-7e30dba20dbf@linaro.org/ - Applied
- rng: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-rng-v1-1-6b6a020e3441@linaro.org/ - Applied
- scm: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-scm-v2-1-68a8db7ae434@linaro.org/ - Reviewed
- sdhci: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-scm-v2-1-68a8db7ae434@linaro.org/ - Applied
- smmu: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-smmu-v1-1-bfa25faa061e@linaro.org/ - Reviewed
- tsens: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-bindings-tsens-v2-1-5add2ac04943@linaro.org/ - Reviewed
- ufs: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-bindings-ufs-v3-1-a96364463fd5@linaro.org - Applied
- clocks: https://lore.kernel.org/all/20231106-topic-sm8650-upstream-clocks-v3-0-761a6fadb4c0@linaro.org/
- interconnect: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-interconnect-v1-0-b7277e03aa3d@linaro.org/ - Reviewed
- llcc: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-llcc-v2-0-f281cec608e2@linaro.org - Reviewed
- mdss: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-mdss-v2-0-43f1887c82b8@linaro.org/ - Reviewed
- phy: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-phy-v2-0-a543a4c4b491@linaro.org/ - Applied
- remoteproc: https://lore.kernel.org/r/20231030-topic-sm8650-upstream-remoteproc-v2-0-609ee572e0a2@linaro.org
- rpmpd: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-rpmpd-v1-0-f25d313104c6@linaro.org/ - Applied
- tlmm: https://lore.kernel.org/all/20231106-topic-sm8650-upstream-tlmm-v3-0-0e179c368933@linaro.org/ - Applied
- goodix: https://lore.kernel.org/all/20231106-topic-goodix-berlin-upstream-initial-v11-0-5c47e9707c03@linaro.org/ - Reviewed
Build Dependencies:
- clocks: https://lore.kernel.org/all/20231106-topic-sm8650-upstream-clocks-v3-0-761a6fadb4c0@linaro.org/
- interconnect: https://lore.kernel.org/all/20231025-topic-sm8650-upstream-interconnect-v1-0-b7277e03aa3d@linaro.org/ - Reviewed
Other:
- socinfo: https://lore.kernel.org/all/20231030-topic-sm8650-upstream-socinfo-v2-0-4751e7391dc9@linaro.org/ - Reviewed
- defconfig: https://lore.kernel.org/all/20231121-topic-sm8650-upstream-defconfig-v1-1-2500565fc21b@linaro.org/
Merge Strategy:
- Merge patches 1-5 with Clock bindings immutable branch
- Merge patches 6-8 with Interconnect immutable branch
For convenience, a regularly refreshed linux-next based git tree containing
all the SM8650 related work is available at:
https://git.codelinaro.org/neil.armstrong/linux/-/tree/topic/sm8650/upstream/integ
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Changes in v3:
- Cleanup of thermal zones
- Rename SDE pinctrl to real signal names
- Link to v2: https://lore.kernel.org/r/20231106-topic-sm8650-upstream-dt-v2-0-44d6f9710fa7@linaro.org
Changes in v2:
- Drop RFC since most of bindings were reviewed
- Collect Reviewed-by/Acked-bys
- Remove #ifndef PMK8550VE_SID in favor of #define in sm8550 dts
- Add allow-set-load/allowed-modes to LDOs
- Add QCOM_ICC_TAG_ALWAYS/QCOM_ICC_TAG_ACTIVE_ONLY to interconnects = <> instead of 0 & 3
- minimal sm8650-qrd.dts cleanup
- Link to v1: https://lore.kernel.org/r/20231025-topic-sm8650-upstream-dt-v1-0-a821712af62f@linaro.org
---
Neil Armstrong (8):
dt-bindings: arm: qcom: document SM8650 and the reference boards
arm64: dts: qcom: add initial SM8650 dtsi
arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable
arm64: dts: qcom: sm8650: add initial SM8650 MTP dts
arm64: dts: qcom: sm8650: add initial SM8650 QRD dts
arm64: dts: qcom: sm8650: add interconnect dependent device nodes
arm64: dts: qcom: sm8650-mtp: add interconnect dependent device nodes
arm64: dts: qcom: sm8650-qrd: add interconnect dependent device nodes
Documentation/devicetree/bindings/arm/qcom.yaml | 7 +
arch/arm64/boot/dts/qcom/Makefile | 2 +
arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 6 +-
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 1 +
arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 1 +
arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 678 +++
arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 803 ++++
arch/arm64/boot/dts/qcom/sm8650.dtsi | 5382 +++++++++++++++++++++++
8 files changed, 6877 insertions(+), 3 deletions(-)
---
base-commit: 07b677953b9dca02928be323e2db853511305fa9
change-id: 20231016-topic-sm8650-upstream-dt-ee696999df62
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 15+ messages in thread* [PATCH v3 1/8] dt-bindings: arm: qcom: document SM8650 and the reference boards 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi Neil Armstrong ` (6 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong, Krzysztof Kozlowski Document the SM8650 SoC and based MTP (Mobile Test Platforms) and QRD (Qualcomm Reference Device) boards. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 88b84035e7b1..c5b6518973d8 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -87,6 +87,7 @@ description: | sm8350 sm8450 sm8550 + sm8650 The 'board' element must be one of the following strings: @@ -1044,6 +1045,12 @@ properties: - qcom,sm8550-qrd - const: qcom,sm8550 + - items: + - enum: + - qcom,sm8650-mtp + - qcom,sm8650-qrd + - const: qcom,sm8650 + # Board compatibles go above qcom,msm-id: -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 1/8] dt-bindings: arm: qcom: document SM8650 and the reference boards Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 2023-11-22 8:07 ` Krishna Kurapati PSSNV 2023-11-22 16:36 ` Konrad Dybcio 2023-11-21 11:00 ` [PATCH v3 3/8] arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable Neil Armstrong ` (5 subsequent siblings) 7 siblings, 2 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Add initial DTSI for the Qualcomm SM8650 platform, only contains nodes which doesn't depend on interconnect. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 2437 ++++++++++++++++++++++++++++++++++ 1 file changed, 2437 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi new file mode 100644 index 000000000000..e6a862230c30 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -0,0 +1,2437 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +#include <dt-bindings/clock/qcom,rpmh.h> +#include <dt-bindings/clock/qcom,sm8650-dispcc.h> +#include <dt-bindings/clock/qcom,sm8650-gcc.h> +#include <dt-bindings/clock/qcom,sm8650-gpucc.h> +#include <dt-bindings/clock/qcom,sm8650-tcsr.h> +#include <dt-bindings/dma/qcom-gpi.h> +#include <dt-bindings/firmware/qcom,scm.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/mailbox/qcom-ipcc.h> +#include <dt-bindings/phy/phy-qcom-qmp.h> +#include <dt-bindings/power/qcom,rpmhpd.h> +#include <dt-bindings/power/qcom-rpmpd.h> +#include <dt-bindings/reset/qcom,sm8650-gpucc.h> +#include <dt-bindings/soc/qcom,gpr.h> +#include <dt-bindings/soc/qcom,rpmh-rsc.h> +#include <dt-bindings/thermal/thermal.h> + +/ { + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen { }; + + clocks { + xo_board: xo-board { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + bi_tcxo_div2: bi-tcxo-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-mult = <1>; + clock-div = <2>; + }; + + bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + + clocks = <&rpmhcc RPMH_CXO_CLK_A>; + clock-mult = <1>; + clock-div = <2>; + }; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0 0>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&CPU_PD0>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + + L2_0: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a520"; + reg = <0 0x100>; + + clocks = <&cpufreq_hw 0>; + + power-domains = <&CPU_PD1>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_0>; + capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <100>; + + qcom,freq-domain = <&cpufreq_hw 0>; + + #cooling-cells = <2>; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0 0x200>; + + clocks = <&cpufreq_hw 3>; + + power-domains = <&CPU_PD2>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_200>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 3>; + + #cooling-cells = <2>; + + L2_200: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0 0x300>; + + clocks = <&cpufreq_hw 3>; + + power-domains = <&CPU_PD3>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_200>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 3>; + + #cooling-cells = <2>; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0 0x400>; + + clocks = <&cpufreq_hw 3>; + + power-domains = <&CPU_PD4>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_400>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 3>; + + #cooling-cells = <2>; + + L2_400: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0 0x500>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&CPU_PD5>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_500>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + L2_500: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + reg = <0 0x600>; + + clocks = <&cpufreq_hw 1>; + + power-domains = <&CPU_PD6>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_600>; + capacity-dmips-mhz = <1792>; + dynamic-power-coefficient = <238>; + + qcom,freq-domain = <&cpufreq_hw 1>; + + #cooling-cells = <2>; + + L2_600: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-x4"; + reg = <0 0x700>; + + clocks = <&cpufreq_hw 2>; + + power-domains = <&CPU_PD7>; + power-domain-names = "psci"; + + enable-method = "psci"; + next-level-cache = <&L2_700>; + capacity-dmips-mhz = <1894>; + dynamic-power-coefficient = <588>; + + qcom,freq-domain = <&cpufreq_hw 2>; + + #cooling-cells = <2>; + + L2_700: l2-cache { + compatible = "cache"; + cache-level = <2>; + cache-unified; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + + core6 { + cpu = <&CPU6>; + }; + + core7 { + cpu = <&CPU7>; + }; + }; + }; + + idle-states { + entry-method = "psci"; + + SILVER_CPU_SLEEP_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <550>; + exit-latency-us = <750>; + min-residency-us = <6700>; + local-timer-stop; + }; + + GOLD_CPU_SLEEP_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <600>; + exit-latency-us = <1300>; + min-residency-us = <8136>; + local-timer-stop; + }; + + GOLD_PLUS_CPU_SLEEP_0: cpu-sleep-2-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-plus-rail-power-collapse"; + arm,psci-suspend-param = <0x40000004>; + entry-latency-us = <500>; + exit-latency-us = <1350>; + min-residency-us = <7480>; + local-timer-stop; + }; + }; + + domain-idle-states { + CLUSTER_SLEEP_0: cluster-sleep-0 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x41000044>; + entry-latency-us = <750>; + exit-latency-us = <2350>; + min-residency-us = <9144>; + }; + + CLUSTER_SLEEP_1: cluster-sleep-1 { + compatible = "domain-idle-state"; + arm,psci-suspend-param = <0x4100c344>; + entry-latency-us = <2800>; + exit-latency-us = <4400>; + min-residency-us = <10150>; + }; + }; + }; + + firmware { + scm: scm { + compatible = "qcom,scm-sm8650", "qcom,scm"; + }; + }; + + memory@a0000000 { + device_type = "memory"; + /* We expect the bootloader to fill in the size */ + reg = <0 0xa0000000 0 0>; + }; + + pmu { + compatible = "arm,armv8-pmuv3"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + + CPU_PD0: power-domain-cpu0 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&SILVER_CPU_SLEEP_0>; + }; + + CPU_PD1: power-domain-cpu1 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&SILVER_CPU_SLEEP_0>; + }; + + CPU_PD2: power-domain-cpu2 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&SILVER_CPU_SLEEP_0>; + }; + + CPU_PD3: power-domain-cpu3 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&GOLD_CPU_SLEEP_0>; + }; + + CPU_PD4: power-domain-cpu4 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&GOLD_CPU_SLEEP_0>; + }; + + CPU_PD5: power-domain-cpu5 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&GOLD_CPU_SLEEP_0>; + }; + + CPU_PD6: power-domain-cpu6 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&GOLD_CPU_SLEEP_0>; + }; + + CPU_PD7: power-domain-cpu7 { + #power-domain-cells = <0>; + power-domains = <&CLUSTER_PD>; + domain-idle-states = <&GOLD_PLUS_CPU_SLEEP_0>; + }; + + CLUSTER_PD: power-domain-cluster { + #power-domain-cells = <0>; + domain-idle-states = <&CLUSTER_SLEEP_0>, + <&CLUSTER_SLEEP_1>; + }; + }; + + reserved_memory: reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hyp_mem: hyp@80000000 { + reg = <0 0x80000000 0 0xe00000>; + no-map; + }; + + cpusys_vm_mem: cpusys-vm@80e00000 { + reg = <0 0x80e00000 0 0x400000>; + no-map; + }; + + /* Merged xbl_dtlog, xbl_ramdump and aop_image regions */ + xbl_dt_log_merged_mem: xbl-dt-log-merged@81a00000 { + reg = <0 0x81a00000 0 0x260000>; + no-map; + }; + + aop_cmd_db_mem: aop-cmd-db@81c60000 { + compatible = "qcom,cmd-db"; + reg = <0 0x81c60000 0 0x20000>; + no-map; + }; + + /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ + aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { + reg = <0 0x81c80000 0 0x74000>; + no-map; + }; + + /* Secdata region can be reused by apps */ + + smem: smem@81d00000 { + compatible = "qcom,smem"; + reg = <0 0x81d00000 0 0x200000>; + hwlocks = <&tcsr_mutex 3>; + no-map; + }; + + adsp_mhi_mem: adsp-mhi@81f00000 { + reg = <0 0x81f00000 0 0x20000>; + no-map; + }; + + pvmfw_mem: pvmfw@824a0000 { + reg = <0 0x824a0000 0 0x100000>; + no-map; + }; + + global_sync_mem: global-sync@82600000 { + reg = <0 0x82600000 0 0x100000>; + no-map; + }; + + tz_stat_mem: tz-stat@82700000 { + reg = <0 0x82700000 0 0x100000>; + no-map; + }; + + qdss_mem: qdss@82800000 { + reg = <0 0x82800000 0 0x2000000>; + no-map; + }; + + mpss_dsm_mem: mpss-dsm@86b00000 { + reg = <0 0x86b00000 0 0x4900000>; + no-map; + }; + + mpss_dsm_mem_2: mpss-dsm-2@8b400000 { + reg = <0 0x8b400000 0 0x800000>; + no-map; + }; + + mpss_mem: mpss@8bc00000 { + reg = <0 0x8bc00000 0 0xf400000>; + no-map; + }; + + q6_mpss_dtb_mem: q6-mpss-dtb@9b000000 { + reg = <0 0x9b000000 0 0x80000>; + no-map; + }; + + ipa_fw_mem: ipa-fw@9b080000 { + reg = <0 0x9b080000 0 0x10000>; + no-map; + }; + + ipa_gsi_mem: ipa-gsi@9b090000 { + reg = <0 0x9b090000 0 0xa000>; + no-map; + }; + + gpu_micro_code_mem: gpu-micro-code@9b09a000 { + reg = <0 0x9b09a000 0 0x2000>; + no-map; + }; + + spss_region_mem: spss@9b0a0000 { + reg = <0 0x9b0a0000 0 0x1e0000>; + no-map; + }; + + /* First part of the "SPU secure shared memory" region */ + spu_tz_shared_mem: spu-tz-shared@9b280000 { + reg = <0 0x9b280000 0 0x60000>; + no-map; + }; + + /* Second part of the "SPU secure shared memory" region */ + spu_modem_shared_mem: spu-modem-shared@9b2e0000 { + reg = <0 0x9b2e0000 0 0x20000>; + no-map; + }; + + camera_mem: camera@9b300000 { + reg = <0 0x9b300000 0 0x800000>; + no-map; + }; + + video_mem: video@9bb00000 { + reg = <0 0x9bb00000 0 0x800000>; + no-map; + }; + + cvp_mem: cvp@9c300000 { + reg = <0 0x9c300000 0 0x700000>; + no-map; + }; + + cdsp_mem: cdsp@9ca00000 { + reg = <0 0x9ca00000 0 0x1400000>; + no-map; + }; + + q6_cdsp_dtb_mem: q6-cdsp-dtb@9de00000 { + reg = <0 0x9de00000 0 0x80000>; + no-map; + }; + + q6_adsp_dtb_mem: q6-adsp-dtb@9de80000 { + reg = <0 0x9de80000 0 0x80000>; + no-map; + }; + + adspslpi_mem: adspslpi@9df00000 { + reg = <0 0x9df00000 0 0x4080000>; + no-map; + }; + + rmtfs_mem: rmtfs@d7c00000 { + compatible = "qcom,rmtfs-mem"; + reg = <0 0xd7c00000 0 0x400000>; + no-map; + + qcom,client-id = <1>; + qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; + }; + + /* Merged tz_reserved, xbl_sc, cpucp_fw and qtee regions */ + tz_merged_mem: tz-merged@d8000000 { + reg = <0 0xd8000000 0 0x800000>; + no-map; + }; + + hwfence_shbuf: hwfence-shbuf@e6440000 { + reg = <0 0xe6440000 0 0x2dd000>; + no-map; + }; + + trust_ui_vm_mem: trust-ui-vm@f3800000 { + reg = <0 0xf3800000 0 0x4400000>; + no-map; + }; + + oem_vm_mem: oem-vm@f7c00000 { + reg = <0 0xf7c00000 0 0x4c00000>; + no-map; + }; + + llcc_lpi_mem: llcc-lpi@ff800000 { + reg = <0 0xff800000 0 0x600000>; + no-map; + }; + }; + + soc: soc@0 { + compatible = "simple-bus"; + + #address-cells = <2>; + #size-cells = <2>; + dma-ranges = <0 0 0 0 0x10 0>; + ranges = <0 0 0 0 0x10 0>; + + gcc: clock-controller@100000 { + compatible = "qcom,sm8650-gcc"; + reg = <0 0x00100000 0 0x1f4200>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&sleep_clk>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>, + <0>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + ipcc: mailbox@406000 { + compatible = "qcom,sm8650-ipcc", "qcom,ipcc"; + reg = <0 0x00406000 0 0x1000>; + + interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <3>; + + #mbox-cells = <2>; + }; + + gpi_dma2: dma-controller@800000 { + compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00800000 0 0x60000>; + + interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; + + dma-channels = <12>; + dma-channel-mask = <0x3f>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0x436 0>; + + dma-coherent; + + status = "disabled"; + }; + + qupv3_id_1: geniqup@8c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x008c0000 0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + iommus = <&apps_smmu 0x423 0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + uart15: serial@89c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0089c000 0 0x4000>; + + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + + pinctrl-0 = <&qup_uart15_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + + dma-channels = <12>; + dma-channel-mask = <0xc>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0>; + dma-coherent; + + status = "disabled"; + }; + + rng: rng@10c3000 { + compatible = "qcom,sm8650-trng", "qcom,trng"; + reg = <0 0x010c3000 0 0x1000>; + }; + + ice: crypto@1d88000 { + compatible = "qcom,sm8650-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,sm8650-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0xa0000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8650-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8650-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + status = "disabled"; + }; + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8650-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e3000 0 0x154>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8650-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x40 0>; + + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + }; + }; + }; + }; + }; + + pdc: interrupt-controller@b220000 { + compatible = "qcom,sm8650-pdc", "qcom,pdc"; + reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; + + interrupt-parent = <&intc>; + + qcom,pdc-ranges = <0 480 94>, <94 609 31>, + <125 63 1>, <126 716 12>, + <138 251 5>, <143 244 4>; + + #interrupt-cells = <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; + reg = <0 0x0c228000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; + reg = <0 0x0c229000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22a000 { + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; + reg = <0 0x0c22a000 0 0x1000>, /* TM */ + <0 0x0c224000 0 0x1000>; /* SROT */ + + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>, + <0 0x0c4c0000 0 0x20000>, + <0 0x0c42d000 0 0x4000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8650-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 211>; + + wakeup-parent = <&pdc>; + + qup_uart15_default: qup-uart15-default-state { + /* TX, RX */ + pins = "gpio30", "gpio31"; + function = "qup2_se7"; + drive-strength = <2>; + bias-disable; + }; + }; + + apps_smmu: iommu@15000000 { + compatible = "qcom,sm8650-smmu-500", "qcom,smmu-500", "arm,mmu-500"; + reg = <0 0x15000000 0 0x100000>; + + interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>; + + #iommu-cells = <2>; + #global-interrupts = <1>; + + dma-coherent; + }; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + reg = <0 0x17100000 0 0x10000>, /* GICD */ + <0 0x17180000 0 0x200000>; /* GICR * 8 */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + + #interrupt-cells = <3>; + interrupt-controller; + + #redistributor-regions = <1>; + redistributor-stride = <0 0x40000>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic_its: msi-controller@17140000 { + compatible = "arm,gic-v3-its"; + reg = <0 0x17140000 0 0x20000>; + + msi-controller; + #msi-cells = <1>; + }; + }; + + timer@17420000 { + compatible = "arm,armv7-timer-mem"; + reg = <0 0x17420000 0 0x1000>; + + ranges = <0 0 0 0x20000000>; + #address-cells = <1>; + #size-cells = <1>; + + frame@17421000 { + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; + + frame-number = <0>; + }; + + frame@17423000 { + reg = <0x17423000 0x1000>; + + interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; + + frame-number = <1>; + + status = "disabled"; + }; + + frame@17425000 { + reg = <0x17425000 0x1000>; + + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + + frame-number = <2>; + + status = "disabled"; + }; + + frame@17427000 { + reg = <0x17427000 0x1000>; + + interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; + + frame-number = <3>; + + status = "disabled"; + }; + + frame@17429000 { + reg = <0x17429000 0x1000>; + + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + + frame-number = <4>; + + status = "disabled"; + }; + + frame@1742b000 { + reg = <0x1742b000 0x1000>; + + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + + frame-number = <5>; + + status = "disabled"; + }; + + frame@1742d000 { + reg = <0x1742d000 0x1000>; + + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; + + frame-number = <6>; + + status = "disabled"; + }; + }; + + apps_rsc: rsc@17a00000 { + compatible = "qcom,rpmh-rsc"; + reg = <0 0x17a00000 0 0x10000>, + <0 0x17a10000 0 0x10000>, + <0 0x17a20000 0 0x10000>, + <0 0x17a30000 0 0x10000>; + reg-names = "drv-0", + "drv-1", + "drv-2"; + + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&CLUSTER_PD>; + + qcom,tcs-offset = <0xd00>; + qcom,drv-id = <2>; + qcom,tcs-config = <ACTIVE_TCS 3>, <SLEEP_TCS 2>, + <WAKE_TCS 2>, <CONTROL_TCS 0>; + + label = "apps_rsc"; + + apps_bcm_voter: bcm-voter { + compatible = "qcom,bcm-voter"; + }; + + rpmhcc: clock-controller { + compatible = "qcom,sm8650-rpmh-clk"; + + clocks = <&xo_board>; + clock-names = "xo"; + + #clock-cells = <1>; + }; + + rpmhpd: power-controller { + compatible = "qcom,sm8650-rpmhpd"; + + operating-points-v2 = <&rpmhpd_opp_table>; + + #power-domain-cells = <1>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp-16 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp-48 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs_d2: opp-52 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; + }; + + rpmhpd_opp_low_svs_d1: opp-56 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; + }; + + rpmhpd_opp_low_svs_d0: opp-60 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; + }; + + rpmhpd_opp_low_svs: opp-64 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_low_svs_l1: opp-80 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; + }; + + rpmhpd_opp_svs: opp-128 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l0: opp-144 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; + }; + + rpmhpd_opp_svs_l1: opp-192 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp-256 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp-320 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp-336 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp-384 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp-416 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; + }; + + cpufreq_hw: cpufreq@17d91000 { + compatible = "qcom,sm8650-cpufreq-epss", "qcom,cpufreq-epss"; + reg = <0 0x17d91000 0 0x1000>, + <0 0x17d92000 0 0x1000>, + <0 0x17d93000 0 0x1000>, + <0 0x17d94000 0 0x1000>; + reg-names = "freq-domain0", + "freq-domain1", + "freq-domain2", + "freq-domain3"; + + interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 738 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1", + "dcvsh-irq-2", + "dcvsh-irq-3"; + + clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; + clock-names = "xo", "alternate"; + + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + + system-cache-controller@25000000 { + compatible = "qcom,sm8650-llcc"; + reg = <0 0x25000000 0 0x200000>, + <0 0x25400000 0 0x200000>, + <0 0x25200000 0 0x200000>, + <0 0x25600000 0 0x200000>, + <0 0x25800000 0 0x200000>; + reg-names = "llcc0_base", + "llcc1_base", + "llcc2_base", + "llcc3_base", + "llcc_broadcast_base"; + + interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + thermal-zones { + aoss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss0-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss0-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss2-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpuss3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpuss3-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu2-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu2-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu2-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu3-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu3-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu4-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu4-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu5-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu5-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu6-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu6-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + aoss1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + cpu7-top-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-middle-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu7-bottom-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu7-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + cpu1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-point1 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu1-critical { + temperature = <110000>; + hysteresis = <1000>; + type = "critical"; + }; + }; + }; + + nsphvx0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsphvx1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphvx1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsphvx1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsphmx0-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsphmx1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsphmx2-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + nsphmx3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + nsphmx3-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + video-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + video-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + ddr-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens1 13>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + ddr-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 14>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera0-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + camera1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 15>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + camera1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + aoss2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 0>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + aoss2-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss0-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 1>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss0-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss1-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 2>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss2-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 3>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss2-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss3-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 4>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss3-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss4-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 5>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss4-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss5-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 6>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss5-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss6-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 7>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss6-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpuss7-thermal { + polling-delay-passive = <10>; + polling-delay = <0>; + thermal-sensors = <&tsens2 8>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + gpuss7-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem0-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 9>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + modem0-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem1-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 10>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + modem1-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem2-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 11>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + modem2-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + modem3-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens2 12>; + + trips { + trip-point0 { + temperature = <90000>; + hysteresis = <2000>; + type = "hot"; + }; + + modem3-critical { + temperature = <110000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; + }; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi 2023-11-21 11:00 ` [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi Neil Armstrong @ 2023-11-22 8:07 ` Krishna Kurapati PSSNV 2023-11-23 13:28 ` Neil Armstrong 2023-11-22 16:36 ` Konrad Dybcio 1 sibling, 1 reply; 15+ messages in thread From: Krishna Kurapati PSSNV @ 2023-11-22 8:07 UTC (permalink / raw) To: Neil Armstrong, Konrad Dybcio Cc: linux-arm-msm, devicetree, Andy Gross, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, Bjorn Andersson > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + > + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 15 IRQ_TYPE_EDGE_RISING>, > + <&pdc 14 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", Hi Neil, This GIC_SPI 130 is actually pwr_event IRQ, not hs_phy_irq. > + "ss_phy_irq", > + "dm_hs_phy_irq", > + "dp_hs_phy_irq"; > + Regards, Krishna, ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi 2023-11-22 8:07 ` Krishna Kurapati PSSNV @ 2023-11-23 13:28 ` Neil Armstrong 0 siblings, 0 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-23 13:28 UTC (permalink / raw) To: Krishna Kurapati PSSNV, Konrad Dybcio Cc: linux-arm-msm, devicetree, Andy Gross, Conor Dooley, Krzysztof Kozlowski, Rob Herring, linux-kernel, Bjorn Andersson On 22/11/2023 09:07, Krishna Kurapati PSSNV wrote: >> + >> + usb_1: usb@a6f8800 { >> + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; >> + reg = <0 0x0a6f8800 0 0x400>; >> + >> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 15 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 14 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "hs_phy_irq", > > Hi Neil, > > This GIC_SPI 130 is actually pwr_event IRQ, not hs_phy_irq. Thanks, Will fix in v4 Neil > >> + "ss_phy_irq", >> + "dm_hs_phy_irq", >> + "dp_hs_phy_irq"; >> + > > Regards, > Krishna, ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi 2023-11-21 11:00 ` [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi Neil Armstrong 2023-11-22 8:07 ` Krishna Kurapati PSSNV @ 2023-11-22 16:36 ` Konrad Dybcio 1 sibling, 0 replies; 15+ messages in thread From: Konrad Dybcio @ 2023-11-22 16:36 UTC (permalink / raw) To: Neil Armstrong, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel On 11/21/23 12:00, Neil Armstrong wrote: > Add initial DTSI for the Qualcomm SM8650 platform, > only contains nodes which doesn't depend on interconnect. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- [...] It's quite a bit to chew through, but I don't think I have anything to point out now Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 3/8] arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 1/8] dt-bindings: arm: qcom: document SM8650 and the reference boards Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 4/8] arm64: dts: qcom: sm8650: add initial SM8650 MTP dts Neil Armstrong ` (4 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong The pm8550ve can be found with a different SID on SM8650 platforms, make it configurable. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/pm8550ve.dtsi | 6 +++--- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 1 + arch/arm64/boot/dts/qcom/sm8550-qrd.dts | 1 + 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi index c47646a467be..4dc1f03ab2c7 100644 --- a/arch/arm64/boot/dts/qcom/pm8550ve.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8550ve.dtsi @@ -33,16 +33,16 @@ trip1 { &spmi_bus { - pm8550ve: pmic@5 { + pm8550ve: pmic@PMK8550VE_SID { compatible = "qcom,pm8550", "qcom,spmi-pmic"; - reg = <0x5 SPMI_USID>; + reg = <PMK8550VE_SID SPMI_USID>; #address-cells = <1>; #size-cells = <0>; pm8550ve_temp_alarm: temp-alarm@a00 { compatible = "qcom,spmi-temp-alarm"; reg = <0xa00>; - interrupts = <0x5 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; + interrupts = <PMK8550VE_SID 0xa 0x0 IRQ_TYPE_EDGE_BOTH>; #thermal-sensor-cells = <0>; }; diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 9a70875028b7..ac045bfc51e5 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -10,6 +10,7 @@ #include "pm8010.dtsi" #include "pm8550.dtsi" #include "pm8550b.dtsi" +#define PMK8550VE_SID 5 #include "pm8550ve.dtsi" #include "pm8550vs.dtsi" #include "pmk8550.dtsi" diff --git a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts index eef811def39b..6d5c2312960f 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-qrd.dts @@ -11,6 +11,7 @@ #include "pm8010.dtsi" #include "pm8550.dtsi" #include "pm8550b.dtsi" +#define PMK8550VE_SID 5 #include "pm8550ve.dtsi" #include "pm8550vs.dtsi" #include "pmk8550.dtsi" -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 4/8] arm64: dts: qcom: sm8650: add initial SM8650 MTP dts 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong ` (2 preceding siblings ...) 2023-11-21 11:00 ` [PATCH v3 3/8] arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 5/8] arm64: dts: qcom: sm8650: add initial SM8650 QRD dts Neil Armstrong ` (3 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Add initial QRD (Qualcomm Reference Device) DT, only boots to shell with USB device support. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 445 ++++++++++++++++++++++++++++++++ 2 files changed, 446 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d6cb840b7050..d73fd2332a34 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -231,3 +231,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx223.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts new file mode 100644 index 000000000000..5738791fea2a --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -0,0 +1,445 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8650.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d_a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8650 MTP"; + compatible = "qcom,sm8650-mtp", "qcom,sm8650"; + + aliases { + serial0 = &uart15; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s1c_1p2>; + vdd-l12-supply = <&vreg_s6c_1p8>; + vdd-l15-supply = <&vreg_s6c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l9b_2p9: ldo9 { + regulator-name = "vreg_l9b_2p9"; + regulator-min-microvolt = <2960000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1c_1p2>; + vdd-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s1c_1p2: smps1 { + regulator-name = "vreg_s1c_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1348000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3c_0p9: smps3 { + regulator-name = "vreg_s3c_0p9"; + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4c_1p2: smps4 { + regulator-name = "vreg_s4c_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1280000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5c_0p7: smps5 { + regulator-name = "vreg_s5c_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6c_1p8: smps6 { + regulator-name = "vreg_s6c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name = "vreg_l3c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name = "vreg_l3e_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name = "vreg_l1g_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name = "vreg_l3g_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l2-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "i"; + + vreg_s4i_0p85: smps4 { + regulator-name = "vreg_s4i_0p85"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name = "vreg_l1i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name = "vreg_l2i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name = "vreg_l3i_0p91"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart15 { + status = "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> USB-C + * USB SS -> USB-C + */ + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1i_0p88>; + vdda12-supply = <&vreg_l3i_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3i_1p2>; + vdda-pll-supply = <&vreg_l3g_0p91>; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 5/8] arm64: dts: qcom: sm8650: add initial SM8650 QRD dts 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong ` (3 preceding siblings ...) 2023-11-21 11:00 ` [PATCH v3 4/8] arm64: dts: qcom: sm8650: add initial SM8650 MTP dts Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 6/8] arm64: dts: qcom: sm8650: add interconnect dependent device nodes Neil Armstrong ` (2 subsequent siblings) 7 siblings, 0 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Add initial QRD (Qualcomm Reference Device) DT, it supports boot to shell with buttons, leds and USB peripheral. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 530 ++++++++++++++++++++++++++++++++ 2 files changed, 531 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index d73fd2332a34..821bacf3ddb5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -232,3 +232,4 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8450-sony-xperia-nagara-pdx224.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8550-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8650-mtp.dtb +dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts new file mode 100644 index 000000000000..f5ce4c889680 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -0,0 +1,530 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2023, Linaro Limited + */ + +/dts-v1/; + +#include <dt-bindings/leds/common.h> +#include <dt-bindings/regulator/qcom,rpmh-regulator.h> +#include "sm8650.dtsi" +#include "pm8010.dtsi" +#include "pm8550.dtsi" +#include "pm8550b.dtsi" +#define PMK8550VE_SID 8 +#include "pm8550ve.dtsi" +#include "pm8550vs.dtsi" +#include "pmk8550.dtsi" +#include "pmr735d_a.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. SM8650 QRD"; + compatible = "qcom,sm8650-qrd", "qcom,sm8650"; + + aliases { + serial0 = &uart15; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&volume_up_n>; + pinctrl-names = "default"; + + key-volume-up { + label = "Volume Up"; + linux,code = <KEY_VOLUMEUP>; + gpios = <&pm8550_gpios 6 GPIO_ACTIVE_LOW>; + debounce-interval = <15>; + linux,can-disable; + wakeup-source; + }; + }; + + vph_pwr: vph-pwr-regulator { + compatible = "regulator-fixed"; + + regulator-name = "vph_pwr"; + regulator-min-microvolt = <3700000>; + regulator-max-microvolt = <3700000>; + + regulator-always-on; + regulator-boot-on; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8550-rpmh-regulators"; + + vdd-bob1-supply = <&vph_pwr>; + vdd-bob2-supply = <&vph_pwr>; + vdd-l2-l13-l14-supply = <&vreg_bob1>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-l5-l16-supply = <&vreg_bob1>; + vdd-l6-l7-supply = <&vreg_bob1>; + vdd-l8-l9-supply = <&vreg_bob1>; + vdd-l11-supply = <&vreg_s1c_1p2>; + vdd-l12-supply = <&vreg_s6c_1p8>; + vdd-l15-supply = <&vreg_s6c_1p8>; + vdd-l17-supply = <&vreg_bob2>; + + qcom,pmic-id = "b"; + + vreg_bob1: bob1 { + regulator-name = "vreg_bob1"; + regulator-min-microvolt = <3296000>; + regulator-max-microvolt = <3960000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_bob2: bob2 { + regulator-name = "vreg_bob2"; + regulator-min-microvolt = <2720000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2b_3p0: ldo2 { + regulator-name = "vreg_l2b_3p0"; + regulator-min-microvolt = <3008000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l5b_3p1: ldo5 { + regulator-name = "vreg_l5b_3p1"; + regulator-min-microvolt = <3104000>; + regulator-max-microvolt = <3104000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l6b_1p8: ldo6 { + regulator-name = "vreg_l6b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l7b_1p8: ldo7 { + regulator-name = "vreg_l7b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l8b_1p8: ldo8 { + regulator-name = "vreg_l8b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3008000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l11b_1p2: ldo11 { + regulator-name = "vreg_l11b_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l12b_1p8: ldo12 { + regulator-name = "vreg_l12b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l13b_3p0: ldo13 { + regulator-name = "vreg_l13b_3p0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l14b_3p2: ldo14 { + regulator-name = "vreg_l14b_3p2"; + regulator-min-microvolt = <3200000>; + regulator-max-microvolt = <3200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l15b_1p8: ldo15 { + regulator-name = "vreg_l15b_1p8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l16b_2p8: ldo16 { + regulator-name = "vreg_l16b_2p8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l17b_2p5: ldo17 { + regulator-name = "vreg_l17b_2p5"; + regulator-min-microvolt = <2504000>; + regulator-max-microvolt = <2504000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-1 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s1c_1p2>; + vdd-l2-supply = <&vreg_s1c_1p2>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s1-supply = <&vph_pwr>; + vdd-s2-supply = <&vph_pwr>; + vdd-s3-supply = <&vph_pwr>; + vdd-s4-supply = <&vph_pwr>; + vdd-s5-supply = <&vph_pwr>; + vdd-s6-supply = <&vph_pwr>; + + qcom,pmic-id = "c"; + + vreg_s1c_1p2: smps1 { + regulator-name = "vreg_s1c_1p2"; + regulator-min-microvolt = <1256000>; + regulator-max-microvolt = <1348000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s2c_0p8: smps2 { + regulator-name = "vreg_s2c_0p8"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1036000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s3c_0p9: smps3 { + regulator-name = "vreg_s3c_0p9"; + regulator-min-microvolt = <976000>; + regulator-max-microvolt = <1064000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s4c_1p2: smps4 { + regulator-name = "vreg_s4c_1p2"; + regulator-min-microvolt = <1224000>; + regulator-max-microvolt = <1280000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s5c_0p7: smps5 { + regulator-name = "vreg_s5c_0p7"; + regulator-min-microvolt = <752000>; + regulator-max-microvolt = <900000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_s6c_1p8: smps6 { + regulator-name = "vreg_s6c_1p8"; + regulator-min-microvolt = <1856000>; + regulator-max-microvolt = <2000000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1c_1p2: ldo1 { + regulator-name = "vreg_l1c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3c_1p2: ldo3 { + regulator-name = "vreg_l3c_1p2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-2 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "d"; + + vreg_l1d_0p88: ldo1 { + regulator-name = "vreg_l1d_0p88"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-3 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "e"; + + vreg_l3e_0p9: ldo3 { + regulator-name = "vreg_l3e_0p9"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-4 { + compatible = "qcom,pm8550vs-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s3c_0p9>; + + qcom,pmic-id = "g"; + + vreg_l1g_0p91: ldo1 { + regulator-name = "vreg_l1g_0p91"; + regulator-min-microvolt = <912000>; + regulator-max-microvolt = <920000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3g_0p91: ldo3 { + regulator-name = "vreg_l3g_0p91"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; + + regulators-5 { + compatible = "qcom,pm8550ve-rpmh-regulators"; + + vdd-l1-supply = <&vreg_s3c_0p9>; + vdd-l2-supply = <&vreg_s3c_0p9>; + vdd-l3-supply = <&vreg_s1c_1p2>; + vdd-s4-supply = <&vph_pwr>; + + qcom,pmic-id = "i"; + + vreg_s4i_0p85: smps4 { + regulator-name = "vreg_s4i_0p85"; + regulator-min-microvolt = <852000>; + regulator-max-microvolt = <1004000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l1i_0p88: ldo1 { + regulator-name = "vreg_l1i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l2i_0p88: ldo2 { + regulator-name = "vreg_l2i_0p88"; + regulator-min-microvolt = <880000>; + regulator-max-microvolt = <912000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + + vreg_l3i_1p2: ldo3 { + regulator-name = "vreg_l3i_0p91"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; + }; + }; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = <KEY_VOLUMEDOWN>; + + status = "okay"; +}; + +&pm8550_flash { + status = "okay"; + + led-0 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_YELLOW>; + led-sources = <1>, <4>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <0>; + }; + + led-1 { + function = LED_FUNCTION_FLASH; + color = <LED_COLOR_ID_WHITE>; + led-sources = <2>, <3>; + led-max-microamp = <500000>; + flash-max-microamp = <2000000>; + flash-max-timeout-us = <1280000>; + function-enumerator = <1>; + }; +}; + +&pm8550_gpios { + volume_up_n: volume-up-n-state { + pins = "gpio6"; + function = "normal"; + bias-pull-up; + input-enable; + power-source = <1>; + }; +}; + +&pm8550_pwm { + status = "okay"; + + multi-led { + color = <LED_COLOR_ID_RGB>; + function = LED_FUNCTION_STATUS; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + color = <LED_COLOR_ID_RED>; + }; + + led@2 { + reg = <2>; + color = <LED_COLOR_ID_GREEN>; + }; + + led@3 { + reg = <3>; + color = <LED_COLOR_ID_BLUE>; + }; + }; +}; + +&pm8550b_eusb2_repeater { + vdd18-supply = <&vreg_l15b_1p8>; + vdd3-supply = <&vreg_l5b_3p1>; +}; + +&pmk8550_rtc { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&sleep_clk { + clock-frequency = <32000>; +}; + +&tlmm { + gpio-reserved-ranges = <32 8>; +}; + +&uart15 { + status = "okay"; +}; + +/* + * DPAUX -> WCD9395 -> USB_SBU -> USB-C + * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C + * USB SS -> NB7VPQ904MMUTWG -> USB-C + */ + +&usb_1 { + status = "okay"; +}; + +&usb_1_dwc3 { + dr_mode = "peripheral"; +}; + +&usb_1_hsphy { + vdd-supply = <&vreg_l1i_0p88>; + vdda12-supply = <&vreg_l3i_1p2>; + + phys = <&pm8550b_eusb2_repeater>; + + status = "okay"; +}; + +&usb_dp_qmpphy { + vdda-phy-supply = <&vreg_l3i_1p2>; + vdda-pll-supply = <&vreg_l3g_0p91>; + + status = "okay"; +}; + +&xo_board { + clock-frequency = <76800000>; +}; -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH v3 6/8] arm64: dts: qcom: sm8650: add interconnect dependent device nodes 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong ` (4 preceding siblings ...) 2023-11-21 11:00 ` [PATCH v3 5/8] arm64: dts: qcom: sm8650: add initial SM8650 QRD dts Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 2023-11-21 11:24 ` Dmitry Baryshkov 2023-11-21 11:00 ` [PATCH v3 7/8] arm64: dts: qcom: sm8650-mtp: " Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 8/8] arm64: dts: qcom: sm8650-qrd: " Neil Armstrong 7 siblings, 1 reply; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Add Hardware nodes that depends on an interconnect property to be valid. The includes: - all QUP i2s/spi nodes - PCIe - UFS - SDHCI - Display - HWMON Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650.dtsi | 3467 +++++++++++++++++++++++++++++++--- 1 file changed, 3206 insertions(+), 261 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi index e6a862230c30..8e21335073bc 100644 --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi @@ -11,6 +11,8 @@ #include <dt-bindings/dma/qcom-gpi.h> #include <dt-bindings/firmware/qcom,scm.h> #include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interconnect/qcom,icc.h> +#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/mailbox/qcom-ipcc.h> #include <dt-bindings/phy/phy-qcom-qmp.h> @@ -57,6 +59,11 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { clock-mult = <1>; clock-div = <2>; }; + + pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; }; cpus { @@ -363,9 +370,23 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { firmware { scm: scm { compatible = "qcom,scm-sm8650", "qcom,scm"; + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; }; }; + clk_virt: interconnect-0 { + compatible = "qcom,sm8650-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + mc_virt: interconnect-1 { + compatible = "qcom,sm8650-mc-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + memory@a0000000 { device_type = "memory"; /* We expect the bootloader to fill in the size */ @@ -626,6 +647,95 @@ llcc_lpi_mem: llcc-lpi@ff800000 { }; }; + smp2p-adsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <443>, <429>; + qcom,local-pid = <0>; + qcom,remote-pid = <2>; + + smp2p_adsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_adsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-cdsp { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <94>, <432>; + qcom,local-pid = <0>; + qcom,remote-pid = <5>; + + smp2p_cdsp_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_cdsp_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + + smp2p-modem { + compatible = "qcom,smp2p"; + + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_SMP2P>; + + qcom,smem = <435>, <428>; + qcom,local-pid = <0>; + qcom,remote-pid = <1>; + + smp2p_modem_out: master-kernel { + qcom,entry-name = "master-kernel"; + #qcom,smem-state-cells = <1>; + }; + + smp2p_modem_in: slave-kernel { + qcom,entry-name = "slave-kernel"; + interrupt-controller; + #interrupt-cells = <2>; + }; + + ipa_smp2p_out: ipa-ap-to-modem { + qcom,entry-name = "ipa"; + #qcom,smem-state-cells = <1>; + }; + + ipa_smp2p_in: ipa-modem-to-ap { + qcom,entry-name = "ipa"; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; @@ -641,13 +751,13 @@ gcc: clock-controller@100000 { clocks = <&bi_tcxo_div2>, <&bi_tcxo_ao_div2>, <&sleep_clk>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>, - <0>; + <&pcie0_phy>, + <&pcie1_phy>, + <&pcie_1_phy_aux_clk>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; #clock-cells = <1>; #reset-cells = <1>; @@ -712,234 +822,2310 @@ qupv3_id_1: geniqup@8c0000 { status = "disabled"; - uart15: serial@89c000 { - compatible = "qcom,geni-debug-uart"; - reg = <0 0x0089c000 0 0x4000>; + i2c8: i2c@880000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00880000 0 0x4000>; - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; clock-names = "se"; - pinctrl-0 = <&qup_uart15_default>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, + <&gpi_dma2 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c8_data_clk>; pinctrl-names = "default"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; }; - }; - gpi_dma1: dma-controller@a00000 { - compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; - reg = <0 0x00a00000 0 0x60000>; + spi8: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00880000 0 0x4000>; - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; - dma-channels = <12>; - dma-channel-mask = <0xc>; - #dma-cells = <3>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; - iommus = <&apps_smmu 0xb6 0>; - dma-coherent; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, + <&gpi_dma2 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; + pinctrl-names = "default"; - status = "disabled"; - }; + #address-cells = <1>; + #size-cells = <0>; - rng: rng@10c3000 { - compatible = "qcom,sm8650-trng", "qcom,trng"; - reg = <0 0x010c3000 0 0x1000>; - }; + status = "disabled"; + }; - ice: crypto@1d88000 { - compatible = "qcom,sm8650-inline-crypto-engine", - "qcom,inline-crypto-engine"; - reg = <0 0x01d88000 0 0x8000>; + i2c9: i2c@884000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00884000 0 0x4000>; - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; - }; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; - tcsr_mutex: hwlock@1f40000 { - compatible = "qcom,tcsr-mutex"; - reg = <0 0x01f40000 0 0x20000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; - #hwlock-cells = <1>; - }; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, + <&gpi_dma2 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c9_data_clk>; + pinctrl-names = "default"; - tcsr: clock-controller@1fc0000 { - compatible = "qcom,sm8650-tcsr", "syscon"; - reg = <0 0x01fc0000 0 0xa0000>; + #address-cells = <1>; + #size-cells = <0>; - clocks = <&rpmhcc RPMH_CXO_CLK>; + status = "disabled"; + }; - #clock-cells = <1>; - #reset-cells = <1>; - }; + spi9: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00884000 0 0x4000>; - gpucc: clock-controller@3d90000 { - compatible = "qcom,sm8650-gpucc"; - reg = <0 0x03d90000 0 0xa000>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&bi_tcxo_div2>, - <&gcc GCC_GPU_GPLL0_CLK_SRC>, - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; - }; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, + <&gpi_dma2 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; + pinctrl-names = "default"; - dispcc: clock-controller@af00000 { - compatible = "qcom,sm8650-dispcc"; - reg = <0 0x0af00000 0 0x20000>; + #address-cells = <1>; + #size-cells = <0>; - clocks = <&bi_tcxo_div2>, - <&bi_tcxo_ao_div2>, - <&gcc GCC_DISP_AHB_CLK>, - <&sleep_clk>, - <0>, /* dsi0 */ - <0>, - <0>, /* dsi1 */ - <0>, - <0>, /* dp0 */ - <0>, - <0>, /* dp1 */ - <0>, - <0>, /* dp2 */ - <0>, - <0>, /* dp3 */ - <0>; + status = "disabled"; + }; - power-domains = <&rpmhpd RPMHPD_MMCX>; - required-opps = <&rpmhpd_opp_low_svs>; + i2c10: i2c@888000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00888000 0 0x4000>; - #clock-cells = <1>; - #reset-cells = <1>; - #power-domain-cells = <1>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; - usb_1_hsphy: phy@88e3000 { - compatible = "qcom,sm8650-snps-eusb2-phy", - "qcom,sm8550-snps-eusb2-phy"; - reg = <0 0x088e3000 0 0x154>; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, + <&gpi_dma2 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c10_data_clk>; + pinctrl-names = "default"; - clocks = <&tcsr TCSR_USB2_CLKREF_EN>; - clock-names = "ref"; + #address-cells = <1>; + #size-cells = <0>; - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + status = "disabled"; + }; - #phy-cells = <0>; + spi10: spi@888000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00888000 0 0x4000>; - status = "disabled"; - }; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; - usb_dp_qmpphy: phy@88e8000 { - compatible = "qcom,sm8650-qmp-usb3-dp-phy"; - reg = <0 0x088e8000 0 0x3000>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, - <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; - clock-names = "aux", - "ref", - "com_aux", - "usb3_pipe"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, + <&gpi_dma2 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; + pinctrl-names = "default"; - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; - reset-names = "phy", - "common"; + #address-cells = <1>; + #size-cells = <0>; - power-domains = <&gcc USB3_PHY_GDSC>; + status = "disabled"; + }; - #clock-cells = <1>; - #phy-cells = <1>; + i2c11: i2c@88c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x0088c000 0 0x4000>; - status = "disabled"; - }; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; - usb_1: usb@a6f8800 { - compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; - reg = <0 0x0a6f8800 0 0x400>; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, - <&pdc 15 IRQ_TYPE_EDGE_RISING>, - <&pdc 14 IRQ_TYPE_EDGE_RISING>; - interrupt-names = "hs_phy_irq", - "ss_phy_irq", - "dm_hs_phy_irq", - "dp_hs_phy_irq"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, + <&gpi_dma2 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c11_data_clk>; + pinctrl-names = "default"; - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&tcsr TCSR_USB3_CLKREF_EN>; - clock-names = "cfg_noc", - "core", - "iface", - "sleep", - "mock_utmi", - "xo"; + #address-cells = <1>; + #size-cells = <0>; - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <200000000>; + status = "disabled"; + }; - resets = <&gcc GCC_USB30_PRIM_BCR>; + spi11: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x0088c000 0 0x4000>; - power-domains = <&gcc USB30_PRIM_GDSC>; - required-opps = <&rpmhpd_opp_nom>; + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; - #address-cells = <2>; - #size-cells = <2>; - ranges; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; - status = "disabled"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, + <&gpi_dma2 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; + pinctrl-names = "default"; - usb_1_dwc3: usb@a600000 { - compatible = "snps,dwc3"; - reg = <0 0x0a600000 0 0xcd00>; + #address-cells = <1>; + #size-cells = <0>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + }; - iommus = <&apps_smmu 0x40 0>; + i2c12: i2c@890000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00890000 0 0x4000>; - phys = <&usb_1_hsphy>, - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; - phy-names = "usb2-phy", - "usb3-phy"; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; - snps,hird-threshold = /bits/ 8 <0x0>; - snps,usb2-gadget-lpm-disable; - snps,dis_u2_susphy_quirk; - snps,dis_enblslpm_quirk; - snps,dis-u1-entry-quirk; - snps,dis-u2-entry-quirk; - snps,is-utmi-l1-suspend; - snps,usb3_lpm_capable; - snps,usb2-lpm-disable; - snps,has-lpm-erratum; - tx-fifo-resize; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; - dma-coherent; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, + <&gpi_dma2 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c12_data_clk>; + pinctrl-names = "default"; - ports { - #address-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi12: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00890000 0 0x4000>; + + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, + <&gpi_dma2 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c13: i2c@894000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00894000 0 0x4000>; + + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, + <&gpi_dma2 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c13_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi13: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00894000 0 0x4000>; + + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, + <&gpi_dma2 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + uart14: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0 0x00898000 0 0x4000>; + + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; + pinctrl-names = "default"; + + status = "disabled"; + }; + + uart15: serial@89c000 { + compatible = "qcom,geni-debug-uart"; + reg = <0 0x0089c000 0 0x4000>; + + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&qup_uart15_default>; + pinctrl-names = "default"; + + status = "disabled"; + }; + }; + + i2c_master_hub_0: geniqup@9c0000 { + compatible = "qcom,geni-se-i2c-master-hub"; + reg = <0 0x009c0000 0 0x2000>; + + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; + clock-names = "s-ahb"; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c_hub_0: i2c@980000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00980000 0 0x4000>; + + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_1: i2c@984000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00984000 0 0x4000>; + + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_2: i2c@988000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00988000 0 0x4000>; + + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_3: i2c@98c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x0098c000 0 0x4000>; + + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_4: i2c@990000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00990000 0 0x4000>; + + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_5: i2c@994000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00994000 0 0x4000>; + + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c5_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_6: i2c@998000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x00998000 0 0x4000>; + + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c6_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_7: i2c@99c000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x0099c000 0 0x4000>; + + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_8: i2c@9a0000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a0000 0 0x4000>; + + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c8_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c_hub_9: i2c@9a4000 { + compatible = "qcom,geni-i2c-master-hub"; + reg = <0 0x009a4000 0 0x4000>; + + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, + <&gcc GCC_QUPV3_I2C_CORE_CLK>; + clock-names = "se", + "core"; + + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config"; + + pinctrl-0 = <&hub_i2c9_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + gpi_dma1: dma-controller@a00000 { + compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x00a00000 0 0x60000>; + + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; + + dma-channels = <12>; + dma-channel-mask = <0xc>; + #dma-cells = <3>; + + iommus = <&apps_smmu 0xb6 0>; + dma-coherent; + + status = "disabled"; + }; + + qupv3_id_0: geniqup@ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0 0x00ac0000 0 0x2000>; + + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + clock-names = "m-ahb", + "s-ahb"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core"; + + iommus = <&apps_smmu 0xa3 0>; + + dma-coherent; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + i2c0: i2c@a80000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a80000 0 0x4000>; + + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c0_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi0: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a80000 0 0x4000>; + + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c1: i2c@a84000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a84000 0 0x4000>; + + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c1_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi1: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a84000 0 0x4000>; + + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c2: i2c@a88000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a88000 0 0x4000>; + + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c2_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi2: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a88000 0 0x4000>; + + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c3: i2c@a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a8c000 0 0x4000>; + + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c3_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi3: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a8c000 0 0x4000>; + + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c4: i2c@a90000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a90000 0 0x4000>; + + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c4_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi4: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a90000 0 0x4000>; + + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c5: i2c@a94000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a94000 0 0x4000>; + + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, + <&gpi_dma1 1 5 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c5_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi5: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a94000 0 0x4000>; + + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, + <&gpi_dma1 1 5 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c6: i2c@a98000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a98000 0 0x4000>; + + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, + <&gpi_dma1 1 6 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c6_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi6: spi@a98000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a98000 0 0x4000>; + + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, + <&gpi_dma1 1 6 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + i2c7: i2c@a9c000 { + compatible = "qcom,geni-i2c"; + reg = <0 0x00a9c000 0 0x4000>; + + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, + <&gpi_dma1 1 7 QCOM_GPI_I2C>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_i2c7_data_clk>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + + spi7: spi@a9c000 { + compatible = "qcom,geni-spi"; + reg = <0 0x00a9c000 0 0x4000>; + + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; + clock-names = "se"; + + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, + <&gpi_dma1 1 7 QCOM_GPI_SPI>; + dma-names = "tx", + "rx"; + + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + }; + }; + + cnoc_main: interconnect@1500000 { + compatible = "qcom,sm8650-cnoc-main"; + reg = <0 0x01500000 0 0x14080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + config_noc: interconnect@1600000 { + compatible = "qcom,sm8650-config-noc"; + reg = <0 0x01600000 0 0x6200>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + system_noc: interconnect@1680000 { + compatible = "qcom,sm8650-system-noc"; + reg = <0 0x01680000 0 0x1d080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + pcie_noc: interconnect@16c0000 { + compatible = "qcom,sm8650-pcie-anoc"; + reg = <0 0x016c0000 0 0x12200>; + + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8650-aggre1-noc"; + reg = <0 0x016e0000 0 0x16400>; + + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + aggre2_noc: interconnect@1700000 { + compatible = "qcom,sm8650-aggre2-noc"; + reg = <0 0x01700000 0 0x1e400>; + + clocks = <&rpmhcc RPMH_IPA_CLK>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + mmss_noc: interconnect@1780000 { + compatible = "qcom,sm8650-mmss-noc"; + reg = <0 0x01780000 0 0x5b800>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + rng: rng@10c3000 { + compatible = "qcom,sm8650-trng", "qcom,trng"; + reg = <0 0x010c3000 0 0x1000>; + }; + + pcie0: pci@1c00000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; + reg = <0 0x01c00000 0 0x3000>, + <0 0x60000000 0 0xf1d>, + <0 0x60000f20 0 0xa8>, + <0 0x60001000 0 0x1000>, + <0 0x60100000 0 0x100000>; + reg-names = "parf", "dbi", "elbi", "atu", "config"; + + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "pci"; + + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + power-domains = <&gcc PCIE_0_GDSC>; + + iommu-map = <0 &apps_smmu 0x1400 0x1>, + <0x100 &apps_smmu 0x1401 0x1>; + + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 0x7>; + #interrupt-cells = <1>; + + linux,pci-domain = <0>; + num-lanes = <2>; + bus-range = <0 0xff>; + + phys = <&pcie0_phy>; + phy-names = "pciephy"; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, + <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; + + dma-coherent; + + status = "disabled"; + }; + + pcie0_phy: phy@1c06000 { + compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; + reg = <0 0x01c06000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_0_CLKREF_EN>, + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_0_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_0_PHY_BCR>; + reset-names = "phy"; + + power-domains = <&gcc PCIE_0_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie0_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + pcie1: pci@1c08000 { + device_type = "pci"; + compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; + reg = <0 0x01c08000 0 0x3000>, + <0 0x40000000 0 0xf1d>, + <0 0x40000f20 0 0xa8>, + <0 0x40001000 0 0x1000>, + <0 0x40100000 0 0x100000>; + reg-names = "parf", + "dbi", + "elbi", + "atu", + "config"; + + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a", + "ddrss_sf_tbu", + "noc_aggr", + "cnoc_sf_axi"; + + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; + assigned-clock-rates = <19200000>; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; + reset-names = "pci", + "link_down"; + + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "pcie-mem", + "cpu-pcie"; + + power-domains = <&gcc PCIE_1_GDSC>; + + iommu-map = <0 &apps_smmu 0x1480 0x1>, + <0x100 &apps_smmu 0x1481 0x1>; + + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map-mask = <0 0 0 0x7>; + #interrupt-cells = <1>; + + linux,pci-domain = <1>; + num-lanes = <2>; + bus-range = <0 0xff>; + + phys = <&pcie1_phy>; + phy-names = "pciephy"; + + dma-coherent; + + #address-cells = <3>; + #size-cells = <2>; + ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, + <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; + + status = "disabled"; + }; + + pcie1_phy: phy@1c0e000 { + compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; + reg = <0 0x01c0e000 0 0x2000>; + + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&tcsr TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK>; + clock-names = "aux", + "cfg_ahb", + "ref", + "rchng", + "pipe"; + + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; + assigned-clock-rates = <100000000>; + + resets = <&gcc GCC_PCIE_1_PHY_BCR>, + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; + reset-names = "phy", + "phy_nocsr"; + + power-domains = <&gcc PCIE_1_PHY_GDSC>; + + #clock-cells = <0>; + clock-output-names = "pcie1_pipe_clk"; + + #phy-cells = <0>; + + status = "disabled"; + }; + + cryptobam: dma-controller@1dc4000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0 0x01dc4000 0 0x28000>; + + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; + + #dma-cells = <1>; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + + qcom,ee = <0>; + qcom,controlled-remotely; + }; + + crypto: crypto@1dfa000 { + compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; + reg = <0 0x01dfa000 0 0x6000>; + + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "memory"; + + dmas = <&cryptobam 4>, <&cryptobam 5>; + dma-names = "rx", "tx"; + + iommus = <&apps_smmu 0x480 0>, + <&apps_smmu 0x481 0>; + }; + + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,sm8650-qmp-ufs-phy"; + reg = <0 0x01d80000 0 0x2000>; + + clocks = <&tcsr TCSR_UFS_CLKREF_EN>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; + clock-names = "ref", + "ref_aux"; + + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; + reg = <0 0x01d84000 0 0x3000>; + + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + freq-table-hz = <100000000 403000000>, + <0 0>, + <0 0>, + <100000000 403000000>, + <100000000 403000000>, + <0 0>, + <0 0>, + <0 0>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x60 0>; + + lanes-per-direction = <2>; + qcom,ice = <&ice>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + }; + + ice: crypto@1d88000 { + compatible = "qcom,sm8650-inline-crypto-engine", + "qcom,inline-crypto-engine"; + reg = <0 0x01d88000 0 0x8000>; + + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; + }; + + tcsr_mutex: hwlock@1f40000 { + compatible = "qcom,tcsr-mutex"; + reg = <0 0x01f40000 0 0x20000>; + + #hwlock-cells = <1>; + }; + + tcsr: clock-controller@1fc0000 { + compatible = "qcom,sm8650-tcsr", "syscon"; + reg = <0 0x01fc0000 0 0xa0000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + + #clock-cells = <1>; + #reset-cells = <1>; + }; + + gpucc: clock-controller@3d90000 { + compatible = "qcom,sm8650-gpucc"; + reg = <0 0x03d90000 0 0xa000>; + + clocks = <&bi_tcxo_div2>, + <&gcc GCC_GPU_GPLL0_CLK_SRC>, + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + remoteproc_mpss: remoteproc@4080000 { + compatible = "qcom,sm8650-mpss-pas"; + reg = <0 0x04080000 0 0x4040>; + + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack", + "shutdown-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MSS>; + power-domain-names = "cx", + "mss"; + + memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, + <&mpss_dsm_mem>, <&mpss_dsm_mem_2>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_modem_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_MPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <1>; + + label = "mpss"; + }; + }; + + lpass_lpiaon_noc: interconnect@7400000 { + compatible = "qcom,sm8650-lpass-lpiaon-noc"; + reg = <0 0x07400000 0 0x19080>; + + #interconnect-cells = <2>; + + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_lpicx_noc: interconnect@7430000 { + compatible = "qcom,sm8650-lpass-lpicx-noc"; + reg = <0 0x07430000 0 0x3a200>; + + #interconnect-cells = <2>; + + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + lpass_ag_noc: interconnect@7e40000 { + compatible = "qcom,sm8650-lpass-ag-noc"; + reg = <0 0x07e40000 0 0xe080>; + + #interconnect-cells = <2>; + + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hc_irq", + "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "core", + "xo"; + + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "sdhc-ddr", + "cpu-sdhc"; + + power-domains = <&rpmhpd RPMHPD_CX>; + operating-points-v2 = <&sdhc2_opp_table>; + + iommus = <&apps_smmu 0x540 0>; + + bus-width = <4>; + + /* Forbid SDR104/SDR50 - broken hw! */ + sdhci-caps-mask = <0x3 0>; + + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + + dma-coherent; + + status = "disabled"; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss: display-subsystem@ae00000 { + compatible = "qcom,sm8650-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "mdp0-mem", + "mdp1-mem"; + + power-domains = <&dispcc MDSS_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8650-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,sm8650-dsi-phy-4nm"; + reg = <0 0x0ae95000 0 0x200>, + <0 0x0ae95200 0 0x280>, + <0 0x0ae95500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,sm8650-dsi-phy-4nm"; + reg = <0 0x0ae97000 0 0x200>, + <0 0x0ae97200 0 0x280>, + <0 0x0ae97500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8650-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + + clocks = <&bi_tcxo_div2>, + <&bi_tcxo_ao_div2>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + + status = "disabled"; + }; + + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8650-snps-eusb2-phy", + "qcom,sm8550-snps-eusb2-phy"; + reg = <0 0x088e3000 0 0x154>; + + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8650-qmp-usb3-dp-phy"; + reg = <0 0x088e8000 0 0x3000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + status = "disabled"; + }; + + usb_1: usb@a6f8800 { + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>, + <&pdc 14 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "hs_phy_irq", + "ss_phy_irq", + "dm_hs_phy_irq", + "dp_hs_phy_irq"; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&tcsr TCSR_USB3_CLKREF_EN>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi", + "xo"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + power-domains = <&gcc USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + usb_1_dwc3: usb@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>; + + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + + iommus = <&apps_smmu 0x40 0>; + + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + ports { + #address-cells = <1>; #size-cells = <0>; port@0 { @@ -969,115 +3155,602 @@ pdc: interrupt-controller@b220000 { <125 63 1>, <126 716 12>, <138 251 5>, <143 244 4>; - #interrupt-cells = <2>; - interrupt-controller; - }; + #interrupt-cells = <2>; + interrupt-controller; + }; + + tsens0: thermal-sensor@c228000 { + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; + reg = <0 0x0c228000 0 0x1000>, /* TM */ + <0 0x0c222000 0 0x1000>; /* SROT */ + + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <15>; + + #thermal-sensor-cells = <1>; + }; + + tsens1: thermal-sensor@c229000 { + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; + reg = <0 0x0c229000 0 0x1000>, /* TM */ + <0 0x0c223000 0 0x1000>; /* SROT */ + + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <16>; + + #thermal-sensor-cells = <1>; + }; + + tsens2: thermal-sensor@c22a000 { + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; + reg = <0 0x0c22a000 0 0x1000>, /* TM */ + <0 0x0c224000 0 0x1000>; /* SROT */ + + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "uplow", + "critical"; + + #qcom,sensors = <13>; + + #thermal-sensor-cells = <1>; + }; + + aoss_qmp: power-management@c300000 { + compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; + reg = <0 0x0c300000 0 0x400>; + + interrupt-parent = <&ipcc>; + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + + #clock-cells = <0>; + }; + + sram@c3f0000 { + compatible = "qcom,rpmh-stats"; + reg = <0 0x0c3f0000 0 0x400>; + }; + + spmi_bus: spmi@c400000 { + compatible = "qcom,spmi-pmic-arb"; + reg = <0 0x0c400000 0 0x3000>, + <0 0x0c500000 0 0x4000000>, + <0 0x0c440000 0 0x80000>, + <0 0x0c4c0000 0 0x20000>, + <0 0x0c42d000 0 0x4000>; + reg-names = "core", + "chnls", + "obsrvr", + "intr", + "cnfg"; + + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + + qcom,ee = <0>; + qcom,channel = <0>; + qcom,bus-id = <0>; + + interrupt-controller; + #interrupt-cells = <4>; + + #address-cells = <2>; + #size-cells = <0>; + }; + + tlmm: pinctrl@f100000 { + compatible = "qcom,sm8650-tlmm"; + reg = <0 0x0f100000 0 0x300000>; + + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 211>; + + wakeup-parent = <&pdc>; + + hub_i2c0_data_clk: hub-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio64", "gpio65"; + function = "i2chub0_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c1_data_clk: hub-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio66", "gpio67"; + function = "i2chub0_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c2_data_clk: hub-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio68", "gpio69"; + function = "i2chub0_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c3_data_clk: hub-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio70", "gpio71"; + function = "i2chub0_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c4_data_clk: hub-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio72", "gpio73"; + function = "i2chub0_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c5_data_clk: hub-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio74", "gpio75"; + function = "i2chub0_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c6_data_clk: hub-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio76", "gpio77"; + function = "i2chub0_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c7_data_clk: hub-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio78", "gpio79"; + function = "i2chub0_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c8_data_clk: hub-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio206", "gpio207"; + function = "i2chub0_se8"; + drive-strength = <2>; + bias-pull-up; + }; + + hub_i2c9_data_clk: hub-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio80", "gpio81"; + function = "i2chub0_se9"; + drive-strength = <2>; + bias-pull-up; + }; + + pcie0_default_state: pcie0-default-state { + perst-pins { + pins = "gpio94"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio95"; + function = "pcie0_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio96"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie1_default_state: pcie1-default-state { + perst-pins { + pins = "gpio97"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + clkreq-pins { + pins = "gpio98"; + function = "pcie1_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio99"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + qup_i2c0_data_clk: qup-i2c0-data-clk-state { + /* SDA, SCL */ + pins = "gpio32", "gpio33"; + function = "qup1_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_data_clk: qup-i2c1-data-clk-state { + /* SDA, SCL */ + pins = "gpio36", "gpio37"; + function = "qup1_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_data_clk: qup-i2c2-data-clk-state { + /* SDA, SCL */ + pins = "gpio40", "gpio41"; + function = "qup1_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c3_data_clk: qup-i2c3-data-clk-state { + /* SDA, SCL */ + pins = "gpio44", "gpio45"; + function = "qup1_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c4_data_clk: qup-i2c4-data-clk-state { + /* SDA, SCL */ + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c5_data_clk: qup-i2c5-data-clk-state { + /* SDA, SCL */ + pins = "gpio52", "gpio53"; + function = "qup1_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c6_data_clk: qup-i2c6-data-clk-state { + /* SDA, SCL */ + pins = "gpio56", "gpio57"; + function = "qup1_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c7_data_clk: qup-i2c7-data-clk-state { + /* SDA, SCL */ + pins = "gpio60", "gpio61"; + function = "qup1_se7"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_data_clk: qup-i2c8-data-clk-state { + /* SDA, SCL */ + pins = "gpio0", "gpio1"; + function = "qup2_se0"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c9_data_clk: qup-i2c9-data-clk-state { + /* SDA, SCL */ + pins = "gpio4", "gpio5"; + function = "qup2_se1"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_data_clk: qup-i2c10-data-clk-state { + /* SDA, SCL */ + pins = "gpio8", "gpio9"; + function = "qup2_se2"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c11_data_clk: qup-i2c11-data-clk-state { + /* SDA, SCL */ + pins = "gpio12", "gpio13"; + function = "qup2_se3"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c12_data_clk: qup-i2c12-data-clk-state { + /* SDA, SCL */ + pins = "gpio16", "gpio17"; + function = "qup2_se4"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c13_data_clk: qup-i2c13-data-clk-state { + /* SDA, SCL */ + pins = "gpio20", "gpio21"; + function = "qup2_se5"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c14_data_clk: qup-i2c14-data-clk-state { + /* SDA, SCL */ + pins = "gpio24", "gpio25"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_cs: qup-spi0-cs-state { + pins = "gpio35"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi0_data_clk: qup-spi0-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio32", "gpio33", "gpio34"; + function = "qup1_se0"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_cs: qup-spi1-cs-state { + pins = "gpio39"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; + + qup_spi1_data_clk: qup-spi1-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio36", "gpio37", "gpio38"; + function = "qup1_se1"; + drive-strength = <6>; + bias-disable; + }; - tsens0: thermal-sensor@c228000 { - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; - reg = <0 0x0c228000 0 0x1000>, /* TM */ - <0 0x0c222000 0 0x1000>; /* SROT */ + qup_spi2_cs: qup-spi2-cs-state { + pins = "gpio43"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", - "critical"; + qup_spi2_data_clk: qup-spi2-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio40", "gpio41", "gpio42"; + function = "qup1_se2"; + drive-strength = <6>; + bias-disable; + }; - #qcom,sensors = <15>; + qup_spi3_cs: qup-spi3-cs-state { + pins = "gpio47"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; - #thermal-sensor-cells = <1>; - }; + qup_spi3_data_clk: qup-spi3-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio44", "gpio45", "gpio46"; + function = "qup1_se3"; + drive-strength = <6>; + bias-disable; + }; - tsens1: thermal-sensor@c229000 { - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; - reg = <0 0x0c229000 0 0x1000>, /* TM */ - <0 0x0c223000 0 0x1000>; /* SROT */ + qup_spi4_cs: qup-spi4-cs-state { + pins = "gpio51"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", - "critical"; + qup_spi4_data_clk: qup-spi4-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio48", "gpio49", "gpio50"; + function = "qup1_se4"; + drive-strength = <6>; + bias-disable; + }; - #qcom,sensors = <16>; + qup_spi5_cs: qup-spi5-cs-state { + pins = "gpio55"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; - #thermal-sensor-cells = <1>; - }; + qup_spi5_data_clk: qup-spi5-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio52", "gpio53", "gpio54"; + function = "qup1_se5"; + drive-strength = <6>; + bias-disable; + }; - tsens2: thermal-sensor@c22a000 { - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; - reg = <0 0x0c22a000 0 0x1000>, /* TM */ - <0 0x0c224000 0 0x1000>; /* SROT */ + qup_spi6_cs: qup-spi6-cs-state { + pins = "gpio59"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; - interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "uplow", - "critical"; + qup_spi6_data_clk: qup-spi6-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio56", "gpio57", "gpio58"; + function = "qup1_se6"; + drive-strength = <6>; + bias-disable; + }; - #qcom,sensors = <13>; + qup_spi7_cs: qup-spi7-cs-state { + pins = "gpio63"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; - #thermal-sensor-cells = <1>; - }; + qup_spi7_data_clk: qup-spi7-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio60", "gpio61", "gpio62"; + function = "qup1_se7"; + drive-strength = <6>; + bias-disable; + }; - aoss_qmp: power-management@c300000 { - compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; - reg = <0 0x0c300000 0 0x400>; + qup_spi8_cs: qup-spi8-cs-state { + pins = "gpio3"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; - interrupt-parent = <&ipcc>; - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; + qup_spi8_data_clk: qup-spi8-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio0", "gpio1", "gpio2"; + function = "qup2_se0"; + drive-strength = <6>; + bias-disable; + }; - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; + qup_spi9_cs: qup-spi9-cs-state { + pins = "gpio7"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; - #clock-cells = <0>; - }; + qup_spi9_data_clk: qup-spi9-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio4", "gpio5", "gpio6"; + function = "qup2_se1"; + drive-strength = <6>; + bias-disable; + }; - sram@c3f0000 { - compatible = "qcom,rpmh-stats"; - reg = <0 0x0c3f0000 0 0x400>; - }; + qup_spi10_cs: qup-spi10-cs-state { + pins = "gpio11"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; - spmi_bus: spmi@c400000 { - compatible = "qcom,spmi-pmic-arb"; - reg = <0 0x0c400000 0 0x3000>, - <0 0x0c500000 0 0x4000000>, - <0 0x0c440000 0 0x80000>, - <0 0x0c4c0000 0 0x20000>, - <0 0x0c42d000 0 0x4000>; - reg-names = "core", - "chnls", - "obsrvr", - "intr", - "cnfg"; + qup_spi10_data_clk: qup-spi10-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio8", "gpio9", "gpio10"; + function = "qup2_se2"; + drive-strength = <6>; + bias-disable; + }; - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "periph_irq"; + qup_spi11_cs: qup-spi11-cs-state { + pins = "gpio15"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; - qcom,ee = <0>; - qcom,channel = <0>; - qcom,bus-id = <0>; + qup_spi11_data_clk: qup-spi11-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio12", "gpio13", "gpio14"; + function = "qup2_se3"; + drive-strength = <6>; + bias-disable; + }; - interrupt-controller; - #interrupt-cells = <4>; + qup_spi12_cs: qup-spi12-cs-state { + pins = "gpio19"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; - #address-cells = <2>; - #size-cells = <0>; - }; + qup_spi12_data_clk: qup-spi12-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio16", "gpio17", "gpio18"; + function = "qup2_se4"; + drive-strength = <6>; + bias-disable; + }; - tlmm: pinctrl@f100000 { - compatible = "qcom,sm8650-tlmm"; - reg = <0 0x0f100000 0 0x300000>; + qup_spi13_cs: qup-spi13-cs-state { + pins = "gpio23"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + qup_spi13_data_clk: qup-spi13-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio20", "gpio21", "gpio22"; + function = "qup2_se5"; + drive-strength = <6>; + bias-disable; + }; - gpio-controller; - #gpio-cells = <2>; + qup_spi14_cs: qup-spi14-cs-state { + pins = "gpio27"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; - interrupt-controller; - #interrupt-cells = <2>; + qup_spi14_data_clk: qup-spi14-data-clk-state { + /* MISO, MOSI, CLK */ + pins = "gpio24", "gpio25", "gpio26"; + function = "qup2_se6"; + drive-strength = <6>; + bias-disable; + }; - gpio-ranges = <&tlmm 0 0 211>; + qup_uart14_default: qup-uart14-default-state { + /* TX, RX */ + pins = "gpio26", "gpio27"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-up; + }; - wakeup-parent = <&pdc>; + qup_uart14_cts_rts: qup-uart14-cts-rts-state { + /* CTS, RTS */ + pins = "gpio24", "gpio25"; + function = "qup2_se6"; + drive-strength = <2>; + bias-pull-down; + }; qup_uart15_default: qup-uart15-default-state { /* TX, RX */ @@ -1086,6 +3759,46 @@ qup_uart15_default: qup-uart15-default-state { drive-strength = <2>; bias-disable; }; + + sdc2_sleep: sdc2-sleep-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <2>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <2>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + sdc2_default: sdc2-default-state { + clk-pins { + pins = "sdc2_clk"; + drive-strength = <16>; + bias-disable; + }; + + cmd-pins { + pins = "sdc2_cmd"; + drive-strength = <10>; + bias-pull-up; + }; + + data-pins { + pins = "sdc2_data"; + drive-strength = <10>; + bias-pull-up; + }; + }; }; apps_smmu: iommu@15000000 { @@ -1437,6 +4150,107 @@ cpufreq_hw: cpufreq@17d91000 { #clock-cells = <1>; }; + pmu@24091000 { + compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; + reg = <0 0x24091000 0 0x1000>; + + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&llcc_bwmon_opp_table>; + + llcc_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <2086000>; + }; + + opp-1 { + opp-peak-kBps = <2929000>; + }; + + opp-2 { + opp-peak-kBps = <5931000>; + }; + + opp-3 { + opp-peak-kBps = <6515000>; + }; + + opp-4 { + opp-peak-kBps = <7980000>; + }; + + opp-5 { + opp-peak-kBps = <10437000>; + }; + + opp-6 { + opp-peak-kBps = <12157000>; + }; + + opp-7 { + opp-peak-kBps = <14060000>; + }; + + opp-8 { + opp-peak-kBps = <16113000>; + }; + }; + }; + + pmu@240b7400 { + compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; + reg = <0 0x240b7400 0 0x600>; + + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; + + operating-points-v2 = <&cpu_bwmon_opp_table>; + + cpu_bwmon_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-0 { + opp-peak-kBps = <4577000>; + }; + + opp-1 { + opp-peak-kBps = <7110000>; + }; + + opp-2 { + opp-peak-kBps = <9155000>; + }; + + opp-3 { + opp-peak-kBps = <12298000>; + }; + + opp-4 { + opp-peak-kBps = <14236000>; + }; + + opp-5 { + opp-peak-kBps = <16265000>; + }; + }; + }; + + gem_noc: interconnect@24100000 { + compatible = "qcom,sm8650-gem-noc"; + reg = <0 0x24100000 0 0xc5080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + system-cache-controller@25000000 { compatible = "qcom,sm8650-llcc"; reg = <0 0x25000000 0 0x200000>, @@ -1452,6 +4266,137 @@ system-cache-controller@25000000 { interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; }; + + remoteproc_adsp: remoteproc@30000000 { + compatible = "qcom,sm8650-adsp-pas"; + reg = <0 0x30000000 0 0x100>; + + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_LCX>, + <&rpmhpd RPMHPD_LMX>; + power-domain-names = "lcx", + "lmx"; + + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_adsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + remoteproc_adsp_glink: glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_LPASS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <2>; + + label = "lpass"; + + fastrpc { + compatible = "qcom,fastrpc"; + + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + label = "adsp"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; + + nsp_noc: interconnect@320c0000 { + compatible = "qcom,sm8650-nsp-noc"; + reg = <0 0x320c0000 0 0xf080>; + + qcom,bcm-voters = <&apps_bcm_voter>; + + #interconnect-cells = <2>; + }; + + remoteproc_cdsp: remoteproc@32300000 { + compatible = "qcom,sm8650-cdsp-pas"; + reg = <0 0x32300000 0 0x1400000>; + + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", + "fatal", + "ready", + "handover", + "stop-ack"; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "xo"; + + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + + power-domains = <&rpmhpd RPMHPD_CX>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_NSP>; + power-domain-names = "cx", + "mxc", + "nsp"; + + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; + + qcom,qmp = <&aoss_qmp>; + + qcom,smem-states = <&smp2p_cdsp_out 0>; + qcom,smem-state-names = "stop"; + + status = "disabled"; + + glink-edge { + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP + IRQ_TYPE_EDGE_RISING>; + + mboxes = <&ipcc IPCC_CLIENT_CDSP + IPCC_MPROC_SIGNAL_GLINK_QMP>; + + qcom,remote-pid = <5>; + + label = "cdsp"; + + fastrpc { + compatible = "qcom,fastrpc"; + + qcom,glink-channels = "fastrpcglink-apps-dsp"; + + label = "cdsp"; + + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; }; thermal-zones { -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/8] arm64: dts: qcom: sm8650: add interconnect dependent device nodes 2023-11-21 11:00 ` [PATCH v3 6/8] arm64: dts: qcom: sm8650: add interconnect dependent device nodes Neil Armstrong @ 2023-11-21 11:24 ` Dmitry Baryshkov 2023-11-21 13:40 ` Neil Armstrong 0 siblings, 1 reply; 15+ messages in thread From: Dmitry Baryshkov @ 2023-11-21 11:24 UTC (permalink / raw) To: Neil Armstrong Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree, linux-kernel On Tue, 21 Nov 2023 at 13:00, Neil Armstrong <neil.armstrong@linaro.org> wrote: > > Add Hardware nodes that depends on an interconnect property to > be valid. > > The includes: > - all QUP i2s/spi nodes > - PCIe > - UFS > - SDHCI > - Display > - HWMON > > Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8650.dtsi | 3467 +++++++++++++++++++++++++++++++--- > 1 file changed, 3206 insertions(+), 261 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi > index e6a862230c30..8e21335073bc 100644 > --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi > @@ -11,6 +11,8 @@ > #include <dt-bindings/dma/qcom-gpi.h> > #include <dt-bindings/firmware/qcom,scm.h> > #include <dt-bindings/gpio/gpio.h> > +#include <dt-bindings/interconnect/qcom,icc.h> > +#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> > #include <dt-bindings/interrupt-controller/arm-gic.h> > #include <dt-bindings/mailbox/qcom-ipcc.h> > #include <dt-bindings/phy/phy-qcom-qmp.h> > @@ -57,6 +59,11 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { > clock-mult = <1>; > clock-div = <2>; > }; > + > + pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + }; I think this clock is provided by the PHY. Let's attribute it this way. > }; > > cpus { > @@ -363,9 +370,23 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { > firmware { > scm: scm { > compatible = "qcom,scm-sm8650", "qcom,scm"; > + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > }; > }; > > + clk_virt: interconnect-0 { > + compatible = "qcom,sm8650-clk-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + mc_virt: interconnect-1 { > + compatible = "qcom,sm8650-mc-virt"; > + #interconnect-cells = <2>; > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > memory@a0000000 { > device_type = "memory"; > /* We expect the bootloader to fill in the size */ > @@ -626,6 +647,95 @@ llcc_lpi_mem: llcc-lpi@ff800000 { > }; > }; > > + smp2p-adsp { > + compatible = "qcom,smp2p"; > + > + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS > + IPCC_MPROC_SIGNAL_SMP2P > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_LPASS > + IPCC_MPROC_SIGNAL_SMP2P>; > + > + qcom,smem = <443>, <429>; > + qcom,local-pid = <0>; > + qcom,remote-pid = <2>; > + > + smp2p_adsp_out: master-kernel { > + qcom,entry-name = "master-kernel"; > + #qcom,smem-state-cells = <1>; > + }; > + > + smp2p_adsp_in: slave-kernel { > + qcom,entry-name = "slave-kernel"; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + smp2p-cdsp { > + compatible = "qcom,smp2p"; > + > + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP > + IPCC_MPROC_SIGNAL_SMP2P > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_CDSP > + IPCC_MPROC_SIGNAL_SMP2P>; > + > + qcom,smem = <94>, <432>; > + qcom,local-pid = <0>; > + qcom,remote-pid = <5>; > + > + smp2p_cdsp_out: master-kernel { > + qcom,entry-name = "master-kernel"; > + #qcom,smem-state-cells = <1>; > + }; > + > + smp2p_cdsp_in: slave-kernel { > + qcom,entry-name = "slave-kernel"; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > + smp2p-modem { > + compatible = "qcom,smp2p"; > + > + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS > + IPCC_MPROC_SIGNAL_SMP2P > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_MPSS > + IPCC_MPROC_SIGNAL_SMP2P>; > + > + qcom,smem = <435>, <428>; > + qcom,local-pid = <0>; > + qcom,remote-pid = <1>; > + > + smp2p_modem_out: master-kernel { > + qcom,entry-name = "master-kernel"; > + #qcom,smem-state-cells = <1>; > + }; > + > + smp2p_modem_in: slave-kernel { > + qcom,entry-name = "slave-kernel"; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + > + ipa_smp2p_out: ipa-ap-to-modem { > + qcom,entry-name = "ipa"; > + #qcom,smem-state-cells = <1>; > + }; > + > + ipa_smp2p_in: ipa-modem-to-ap { > + qcom,entry-name = "ipa"; > + interrupt-controller; > + #interrupt-cells = <2>; > + }; > + }; > + > soc: soc@0 { > compatible = "simple-bus"; > > @@ -641,13 +751,13 @@ gcc: clock-controller@100000 { > clocks = <&bi_tcxo_div2>, > <&bi_tcxo_ao_div2>, > <&sleep_clk>, > - <0>, > - <0>, > - <0>, > - <0>, > - <0>, > - <0>, > - <0>; > + <&pcie0_phy>, > + <&pcie1_phy>, > + <&pcie_1_phy_aux_clk>, > + <&ufs_mem_phy 0>, > + <&ufs_mem_phy 1>, > + <&ufs_mem_phy 2>, > + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; > > #clock-cells = <1>; > #reset-cells = <1>; > @@ -712,234 +822,2310 @@ qupv3_id_1: geniqup@8c0000 { > > status = "disabled"; > > - uart15: serial@89c000 { > - compatible = "qcom,geni-debug-uart"; > - reg = <0 0x0089c000 0 0x4000>; I think, git diff got it wrong here. Is there any chance we can help it? > + i2c8: i2c@880000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00880000 0 0x4000>; > > - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; > clock-names = "se"; > > - pinctrl-0 = <&qup_uart15_default>; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, > + <&gpi_dma2 1 0 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c8_data_clk>; > pinctrl-names = "default"; > > + #address-cells = <1>; > + #size-cells = <0>; > + > status = "disabled"; > }; > - }; > > - gpi_dma1: dma-controller@a00000 { > - compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; > - reg = <0 0x00a00000 0 0x60000>; > + spi8: spi@880000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00880000 0 0x4000>; > > - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; > + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; > > - dma-channels = <12>; > - dma-channel-mask = <0xc>; > - #dma-cells = <3>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; > + clock-names = "se"; > > - iommus = <&apps_smmu 0xb6 0>; > - dma-coherent; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, > + <&gpi_dma2 1 0 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; > + pinctrl-names = "default"; > > - status = "disabled"; > - }; > + #address-cells = <1>; > + #size-cells = <0>; > > - rng: rng@10c3000 { > - compatible = "qcom,sm8650-trng", "qcom,trng"; > - reg = <0 0x010c3000 0 0x1000>; > - }; > + status = "disabled"; > + }; > > - ice: crypto@1d88000 { > - compatible = "qcom,sm8650-inline-crypto-engine", > - "qcom,inline-crypto-engine"; > - reg = <0 0x01d88000 0 0x8000>; > + i2c9: i2c@884000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00884000 0 0x4000>; > > - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > - }; > + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; > > - tcsr_mutex: hwlock@1f40000 { > - compatible = "qcom,tcsr-mutex"; > - reg = <0 0x01f40000 0 0x20000>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; > + clock-names = "se"; > > - #hwlock-cells = <1>; > - }; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, > + <&gpi_dma2 1 1 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c9_data_clk>; > + pinctrl-names = "default"; > > - tcsr: clock-controller@1fc0000 { > - compatible = "qcom,sm8650-tcsr", "syscon"; > - reg = <0 0x01fc0000 0 0xa0000>; > + #address-cells = <1>; > + #size-cells = <0>; > > - clocks = <&rpmhcc RPMH_CXO_CLK>; > + status = "disabled"; > + }; > > - #clock-cells = <1>; > - #reset-cells = <1>; > - }; > + spi9: spi@884000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00884000 0 0x4000>; > > - gpucc: clock-controller@3d90000 { > - compatible = "qcom,sm8650-gpucc"; > - reg = <0 0x03d90000 0 0xa000>; > + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; > > - clocks = <&bi_tcxo_div2>, > - <&gcc GCC_GPU_GPLL0_CLK_SRC>, > - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; > + clock-names = "se"; > > - #clock-cells = <1>; > - #reset-cells = <1>; > - #power-domain-cells = <1>; > - }; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, > + <&gpi_dma2 1 1 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; > + pinctrl-names = "default"; > > - dispcc: clock-controller@af00000 { > - compatible = "qcom,sm8650-dispcc"; > - reg = <0 0x0af00000 0 0x20000>; > + #address-cells = <1>; > + #size-cells = <0>; > > - clocks = <&bi_tcxo_div2>, > - <&bi_tcxo_ao_div2>, > - <&gcc GCC_DISP_AHB_CLK>, > - <&sleep_clk>, > - <0>, /* dsi0 */ > - <0>, > - <0>, /* dsi1 */ > - <0>, > - <0>, /* dp0 */ > - <0>, > - <0>, /* dp1 */ > - <0>, > - <0>, /* dp2 */ > - <0>, > - <0>, /* dp3 */ > - <0>; > + status = "disabled"; > + }; > > - power-domains = <&rpmhpd RPMHPD_MMCX>; > - required-opps = <&rpmhpd_opp_low_svs>; > + i2c10: i2c@888000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00888000 0 0x4000>; > > - #clock-cells = <1>; > - #reset-cells = <1>; > - #power-domain-cells = <1>; > + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; > > - status = "disabled"; > - }; > + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; > + clock-names = "se"; > > - usb_1_hsphy: phy@88e3000 { > - compatible = "qcom,sm8650-snps-eusb2-phy", > - "qcom,sm8550-snps-eusb2-phy"; > - reg = <0 0x088e3000 0 0x154>; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, > + <&gpi_dma2 1 2 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c10_data_clk>; > + pinctrl-names = "default"; > > - clocks = <&tcsr TCSR_USB2_CLKREF_EN>; > - clock-names = "ref"; > + #address-cells = <1>; > + #size-cells = <0>; > > - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + status = "disabled"; > + }; > > - #phy-cells = <0>; > + spi10: spi@888000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00888000 0 0x4000>; > > - status = "disabled"; > - }; > + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; > > - usb_dp_qmpphy: phy@88e8000 { > - compatible = "qcom,sm8650-qmp-usb3-dp-phy"; > - reg = <0 0x088e8000 0 0x3000>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; > + clock-names = "se"; > > - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > - <&rpmhcc RPMH_CXO_CLK>, > - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > - clock-names = "aux", > - "ref", > - "com_aux", > - "usb3_pipe"; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, > + <&gpi_dma2 1 2 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; > + pinctrl-names = "default"; > > - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, > - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; > - reset-names = "phy", > - "common"; > + #address-cells = <1>; > + #size-cells = <0>; > > - power-domains = <&gcc USB3_PHY_GDSC>; > + status = "disabled"; > + }; > > - #clock-cells = <1>; > - #phy-cells = <1>; > + i2c11: i2c@88c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x0088c000 0 0x4000>; > > - status = "disabled"; > - }; > + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; > > - usb_1: usb@a6f8800 { > - compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; > - reg = <0 0x0a6f8800 0 0x400>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; > + clock-names = "se"; > > - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, > - <&pdc 15 IRQ_TYPE_EDGE_RISING>, > - <&pdc 14 IRQ_TYPE_EDGE_RISING>; > - interrupt-names = "hs_phy_irq", > - "ss_phy_irq", > - "dm_hs_phy_irq", > - "dp_hs_phy_irq"; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, > + <&gpi_dma2 1 3 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c11_data_clk>; > + pinctrl-names = "default"; > > - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > - <&gcc GCC_USB30_PRIM_MASTER_CLK>, > - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > - <&tcsr TCSR_USB3_CLKREF_EN>; > - clock-names = "cfg_noc", > - "core", > - "iface", > - "sleep", > - "mock_utmi", > - "xo"; > + #address-cells = <1>; > + #size-cells = <0>; > > - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > - <&gcc GCC_USB30_PRIM_MASTER_CLK>; > - assigned-clock-rates = <19200000>, <200000000>; > + status = "disabled"; > + }; > > - resets = <&gcc GCC_USB30_PRIM_BCR>; > + spi11: spi@88c000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x0088c000 0 0x4000>; > > - power-domains = <&gcc USB30_PRIM_GDSC>; > - required-opps = <&rpmhpd_opp_nom>; > + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; > > - #address-cells = <2>; > - #size-cells = <2>; > - ranges; > + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; > + clock-names = "se"; > > - status = "disabled"; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, > + <&gpi_dma2 1 3 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; > + pinctrl-names = "default"; > > - usb_1_dwc3: usb@a600000 { > - compatible = "snps,dwc3"; > - reg = <0 0x0a600000 0 0xcd00>; > + #address-cells = <1>; > + #size-cells = <0>; > > - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + status = "disabled"; > + }; > > - iommus = <&apps_smmu 0x40 0>; > + i2c12: i2c@890000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00890000 0 0x4000>; > > - phys = <&usb_1_hsphy>, > - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; > - phy-names = "usb2-phy", > - "usb3-phy"; > + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; > > - snps,hird-threshold = /bits/ 8 <0x0>; > - snps,usb2-gadget-lpm-disable; > - snps,dis_u2_susphy_quirk; > - snps,dis_enblslpm_quirk; > - snps,dis-u1-entry-quirk; > - snps,dis-u2-entry-quirk; > - snps,is-utmi-l1-suspend; > - snps,usb3_lpm_capable; > - snps,usb2-lpm-disable; > - snps,has-lpm-erratum; > - tx-fifo-resize; > + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; > + clock-names = "se"; > > - dma-coherent; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, > + <&gpi_dma2 1 4 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c12_data_clk>; > + pinctrl-names = "default"; > > - ports { > - #address-cells = <1>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi12: spi@890000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00890000 0 0x4000>; > + > + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, > + <&gpi_dma2 1 4 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c13: i2c@894000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00894000 0 0x4000>; > + > + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, > + <&gpi_dma2 1 5 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c13_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi13: spi@894000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00894000 0 0x4000>; > + > + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, > + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, > + <&gpi_dma2 1 5 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + uart14: serial@898000 { > + compatible = "qcom,geni-uart"; > + reg = <0 0x00898000 0 0x4000>; > + > + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; > + pinctrl-names = "default"; > + > + status = "disabled"; > + }; > + > + uart15: serial@89c000 { > + compatible = "qcom,geni-debug-uart"; > + reg = <0 0x0089c000 0 0x4000>; > + > + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&qup_uart15_default>; > + pinctrl-names = "default"; > + > + status = "disabled"; > + }; > + }; > + > + i2c_master_hub_0: geniqup@9c0000 { > + compatible = "qcom,geni-se-i2c-master-hub"; > + reg = <0 0x009c0000 0 0x2000>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; > + clock-names = "s-ahb"; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + i2c_hub_0: i2c@980000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x00980000 0 0x4000>; > + > + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c0_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_1: i2c@984000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x00984000 0 0x4000>; > + > + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c1_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_2: i2c@988000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x00988000 0 0x4000>; > + > + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c2_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_3: i2c@98c000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x0098c000 0 0x4000>; > + > + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c3_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_4: i2c@990000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x00990000 0 0x4000>; > + > + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c4_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_5: i2c@994000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x00994000 0 0x4000>; > + > + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c5_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_6: i2c@998000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x00998000 0 0x4000>; > + > + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c6_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_7: i2c@99c000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x0099c000 0 0x4000>; > + > + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c7_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_8: i2c@9a0000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x009a0000 0 0x4000>; > + > + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c8_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c_hub_9: i2c@9a4000 { > + compatible = "qcom,geni-i2c-master-hub"; > + reg = <0 0x009a4000 0 0x4000>; > + > + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, > + <&gcc GCC_QUPV3_I2C_CORE_CLK>; > + clock-names = "se", > + "core"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config"; > + > + pinctrl-0 = <&hub_i2c9_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + }; > + > + gpi_dma1: dma-controller@a00000 { > + compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; > + reg = <0 0x00a00000 0 0x60000>; > + > + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; > + > + dma-channels = <12>; > + dma-channel-mask = <0xc>; > + #dma-cells = <3>; > + > + iommus = <&apps_smmu 0xb6 0>; > + dma-coherent; > + > + status = "disabled"; > + }; > + > + qupv3_id_0: geniqup@ac0000 { > + compatible = "qcom,geni-se-qup"; > + reg = <0 0x00ac0000 0 0x2000>; > + > + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, > + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; > + clock-names = "m-ahb", > + "s-ahb"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core"; > + > + iommus = <&apps_smmu 0xa3 0>; > + > + dma-coherent; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + i2c0: i2c@a80000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a80000 0 0x4000>; > + > + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, > + <&gpi_dma1 1 0 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c0_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi0: spi@a80000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a80000 0 0x4000>; > + > + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, > + <&gpi_dma1 1 0 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c1: i2c@a84000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a84000 0 0x4000>; > + > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, > + <&gpi_dma1 1 1 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c1_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi1: spi@a84000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a84000 0 0x4000>; > + > + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, > + <&gpi_dma1 1 1 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c2: i2c@a88000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a88000 0 0x4000>; > + > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, > + <&gpi_dma1 1 2 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c2_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi2: spi@a88000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a88000 0 0x4000>; > + > + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, > + <&gpi_dma1 1 2 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c3: i2c@a8c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a8c000 0 0x4000>; > + > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, > + <&gpi_dma1 1 3 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c3_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi3: spi@a8c000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a8c000 0 0x4000>; > + > + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, > + <&gpi_dma1 1 3 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c4: i2c@a90000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a90000 0 0x4000>; > + > + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, > + <&gpi_dma1 1 4 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c4_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi4: spi@a90000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a90000 0 0x4000>; > + > + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, > + <&gpi_dma1 1 4 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c5: i2c@a94000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a94000 0 0x4000>; > + > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, > + <&gpi_dma1 1 5 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c5_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi5: spi@a94000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a94000 0 0x4000>; > + > + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, > + <&gpi_dma1 1 5 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c6: i2c@a98000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a98000 0 0x4000>; > + > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, > + <&gpi_dma1 1 6 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c6_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi6: spi@a98000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a98000 0 0x4000>; > + > + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, > + <&gpi_dma1 1 6 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + i2c7: i2c@a9c000 { > + compatible = "qcom,geni-i2c"; > + reg = <0 0x00a9c000 0 0x4000>; > + > + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, > + <&gpi_dma1 1 7 QCOM_GPI_I2C>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_i2c7_data_clk>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + > + spi7: spi@a9c000 { > + compatible = "qcom,geni-spi"; > + reg = <0 0x00a9c000 0 0x4000>; > + > + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; > + clock-names = "se"; > + > + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, > + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", > + "qup-config", > + "qup-memory"; > + > + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, > + <&gpi_dma1 1 7 QCOM_GPI_SPI>; > + dma-names = "tx", > + "rx"; > + > + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; > + pinctrl-names = "default"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + }; > + }; > + > + cnoc_main: interconnect@1500000 { > + compatible = "qcom,sm8650-cnoc-main"; > + reg = <0 0x01500000 0 0x14080>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + config_noc: interconnect@1600000 { > + compatible = "qcom,sm8650-config-noc"; > + reg = <0 0x01600000 0 0x6200>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + system_noc: interconnect@1680000 { > + compatible = "qcom,sm8650-system-noc"; > + reg = <0 0x01680000 0 0x1d080>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + pcie_noc: interconnect@16c0000 { > + compatible = "qcom,sm8650-pcie-anoc"; > + reg = <0 0x016c0000 0 0x12200>; > + > + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, > + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + aggre1_noc: interconnect@16e0000 { > + compatible = "qcom,sm8650-aggre1-noc"; > + reg = <0 0x016e0000 0 0x16400>; > + > + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + aggre2_noc: interconnect@1700000 { > + compatible = "qcom,sm8650-aggre2-noc"; > + reg = <0 0x01700000 0 0x1e400>; > + > + clocks = <&rpmhcc RPMH_IPA_CLK>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + mmss_noc: interconnect@1780000 { > + compatible = "qcom,sm8650-mmss-noc"; > + reg = <0 0x01780000 0 0x5b800>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + rng: rng@10c3000 { > + compatible = "qcom,sm8650-trng", "qcom,trng"; > + reg = <0 0x010c3000 0 0x1000>; > + }; > + > + pcie0: pci@1c00000 { > + device_type = "pci"; > + compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; > + reg = <0 0x01c00000 0 0x3000>, > + <0 0x60000000 0 0xf1d>, > + <0 0x60000f20 0 0xa8>, > + <0 0x60001000 0 0x1000>, > + <0 0x60100000 0 0x100000>; > + reg-names = "parf", "dbi", "elbi", "atu", "config"; > + > + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi"; > + > + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, > + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, > + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, > + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "ddrss_sf_tbu", > + "noc_aggr", > + "cnoc_sf_axi"; > + > + resets = <&gcc GCC_PCIE_0_BCR>; > + reset-names = "pci"; > + > + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "pcie-mem", > + "cpu-pcie"; > + > + power-domains = <&gcc PCIE_0_GDSC>; > + > + iommu-map = <0 &apps_smmu 0x1400 0x1>, > + <0x100 &apps_smmu 0x1401 0x1>; > + > + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 0x7>; > + #interrupt-cells = <1>; > + > + linux,pci-domain = <0>; > + num-lanes = <2>; > + bus-range = <0 0xff>; > + > + phys = <&pcie0_phy>; > + phy-names = "pciephy"; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, > + <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; > + > + dma-coherent; > + > + status = "disabled"; > + }; > + > + pcie0_phy: phy@1c06000 { > + compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; > + reg = <0 0x01c06000 0 0x2000>; > + > + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&tcsr TCSR_PCIE_0_CLKREF_EN>, > + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, > + <&gcc GCC_PCIE_0_PIPE_CLK>; > + clock-names = "aux", > + "cfg_ahb", > + "ref", > + "rchng", > + "pipe"; > + > + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; > + assigned-clock-rates = <100000000>; > + > + resets = <&gcc GCC_PCIE_0_PHY_BCR>; > + reset-names = "phy"; > + > + power-domains = <&gcc PCIE_0_PHY_GDSC>; > + > + #clock-cells = <0>; > + clock-output-names = "pcie0_pipe_clk"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + pcie1: pci@1c08000 { > + device_type = "pci"; > + compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; > + reg = <0 0x01c08000 0 0x3000>, > + <0 0x40000000 0 0xf1d>, > + <0 0x40000f20 0 0xa8>, > + <0 0x40001000 0 0x1000>, > + <0 0x40100000 0 0x100000>; > + reg-names = "parf", > + "dbi", > + "elbi", > + "atu", > + "config"; > + > + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "msi"; > + > + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, > + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, > + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, > + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, > + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; > + clock-names = "aux", > + "cfg", > + "bus_master", > + "bus_slave", > + "slave_q2a", > + "ddrss_sf_tbu", > + "noc_aggr", > + "cnoc_sf_axi"; > + > + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; > + assigned-clock-rates = <19200000>; > + > + resets = <&gcc GCC_PCIE_1_BCR>, > + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; > + reset-names = "pci", > + "link_down"; > + > + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "pcie-mem", > + "cpu-pcie"; > + > + power-domains = <&gcc PCIE_1_GDSC>; > + > + iommu-map = <0 &apps_smmu 0x1480 0x1>, > + <0x100 &apps_smmu 0x1481 0x1>; > + > + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, > + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-map-mask = <0 0 0 0x7>; > + #interrupt-cells = <1>; > + > + linux,pci-domain = <1>; > + num-lanes = <2>; > + bus-range = <0 0xff>; > + > + phys = <&pcie1_phy>; > + phy-names = "pciephy"; > + > + dma-coherent; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, > + <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; > + > + status = "disabled"; > + }; > + > + pcie1_phy: phy@1c0e000 { > + compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; > + reg = <0 0x01c0e000 0 0x2000>; > + > + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, > + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, > + <&tcsr TCSR_PCIE_1_CLKREF_EN>, > + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, > + <&gcc GCC_PCIE_1_PIPE_CLK>; > + clock-names = "aux", > + "cfg_ahb", > + "ref", > + "rchng", > + "pipe"; > + > + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; > + assigned-clock-rates = <100000000>; > + > + resets = <&gcc GCC_PCIE_1_PHY_BCR>, > + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; > + reset-names = "phy", > + "phy_nocsr"; > + > + power-domains = <&gcc PCIE_1_PHY_GDSC>; > + > + #clock-cells = <0>; > + clock-output-names = "pcie1_pipe_clk"; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + cryptobam: dma-controller@1dc4000 { > + compatible = "qcom,bam-v1.7.0"; > + reg = <0 0x01dc4000 0 0x28000>; > + > + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; > + > + #dma-cells = <1>; > + > + iommus = <&apps_smmu 0x480 0>, > + <&apps_smmu 0x481 0>; > + > + qcom,ee = <0>; > + qcom,controlled-remotely; > + }; > + > + crypto: crypto@1dfa000 { > + compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; > + reg = <0 0x01dfa000 0 0x6000>; > + > + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "memory"; > + > + dmas = <&cryptobam 4>, <&cryptobam 5>; > + dma-names = "rx", "tx"; > + > + iommus = <&apps_smmu 0x480 0>, > + <&apps_smmu 0x481 0>; > + }; > + > + ufs_mem_phy: phy@1d80000 { > + compatible = "qcom,sm8650-qmp-ufs-phy"; > + reg = <0 0x01d80000 0 0x2000>; > + > + clocks = <&tcsr TCSR_UFS_CLKREF_EN>, > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; > + clock-names = "ref", > + "ref_aux"; > + > + resets = <&ufs_mem_hc 0>; > + reset-names = "ufsphy"; > + > + power-domains = <&gcc UFS_MEM_PHY_GDSC>; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + ufs_mem_hc: ufs@1d84000 { > + compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; > + reg = <0 0x01d84000 0 0x3000>; > + > + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, > + <&gcc GCC_UFS_PHY_AHB_CLK>, > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, > + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, > + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; > + clock-names = "core_clk", > + "bus_aggr_clk", > + "iface_clk", > + "core_clk_unipro", > + "ref_clk", > + "tx_lane0_sync_clk", > + "rx_lane0_sync_clk", > + "rx_lane1_sync_clk"; > + freq-table-hz = <100000000 403000000>, > + <0 0>, > + <0 0>, > + <100000000 403000000>, > + <100000000 403000000>, > + <0 0>, > + <0 0>, > + <0 0>; > + > + resets = <&gcc GCC_UFS_PHY_BCR>; > + reset-names = "rst"; > + > + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "ufs-ddr", > + "cpu-ufs"; > + > + power-domains = <&gcc UFS_PHY_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + iommus = <&apps_smmu 0x60 0>; > + > + lanes-per-direction = <2>; > + qcom,ice = <&ice>; > + > + phys = <&ufs_mem_phy>; > + phy-names = "ufsphy"; > + > + #reset-cells = <1>; > + > + status = "disabled"; > + }; > + > + ice: crypto@1d88000 { > + compatible = "qcom,sm8650-inline-crypto-engine", > + "qcom,inline-crypto-engine"; > + reg = <0 0x01d88000 0 0x8000>; > + > + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; > + }; > + > + tcsr_mutex: hwlock@1f40000 { > + compatible = "qcom,tcsr-mutex"; > + reg = <0 0x01f40000 0 0x20000>; > + > + #hwlock-cells = <1>; > + }; > + > + tcsr: clock-controller@1fc0000 { > + compatible = "qcom,sm8650-tcsr", "syscon"; > + reg = <0 0x01fc0000 0 0xa0000>; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + }; > + > + gpucc: clock-controller@3d90000 { > + compatible = "qcom,sm8650-gpucc"; > + reg = <0 0x03d90000 0 0xa000>; > + > + clocks = <&bi_tcxo_div2>, > + <&gcc GCC_GPU_GPLL0_CLK_SRC>, > + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + }; > + > + remoteproc_mpss: remoteproc@4080000 { > + compatible = "qcom,sm8650-mpss-pas"; > + reg = <0 0x04080000 0 0x4040>; > + > + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", > + "fatal", > + "ready", > + "handover", > + "stop-ack", > + "shutdown-ack"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "xo"; > + > + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + > + power-domains = <&rpmhpd RPMHPD_CX>, > + <&rpmhpd RPMHPD_MSS>; > + power-domain-names = "cx", > + "mss"; > + > + memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, > + <&mpss_dsm_mem>, <&mpss_dsm_mem_2>; > + > + qcom,qmp = <&aoss_qmp>; > + > + qcom,smem-states = <&smp2p_modem_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_MPSS > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + qcom,remote-pid = <1>; > + > + label = "mpss"; > + }; > + }; > + > + lpass_lpiaon_noc: interconnect@7400000 { > + compatible = "qcom,sm8650-lpass-lpiaon-noc"; > + reg = <0 0x07400000 0 0x19080>; > + > + #interconnect-cells = <2>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + lpass_lpicx_noc: interconnect@7430000 { > + compatible = "qcom,sm8650-lpass-lpicx-noc"; > + reg = <0 0x07430000 0 0x3a200>; > + > + #interconnect-cells = <2>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + lpass_ag_noc: interconnect@7e40000 { > + compatible = "qcom,sm8650-lpass-ag-noc"; > + reg = <0 0x07e40000 0 0xe080>; > + > + #interconnect-cells = <2>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + }; > + > + sdhc_2: mmc@8804000 { > + compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; > + reg = <0 0x08804000 0 0x1000>; > + > + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "hc_irq", > + "pwr_irq"; > + > + clocks = <&gcc GCC_SDCC2_AHB_CLK>, > + <&gcc GCC_SDCC2_APPS_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", > + "core", > + "xo"; > + > + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "sdhc-ddr", > + "cpu-sdhc"; > + > + power-domains = <&rpmhpd RPMHPD_CX>; > + operating-points-v2 = <&sdhc2_opp_table>; > + > + iommus = <&apps_smmu 0x540 0>; > + > + bus-width = <4>; > + > + /* Forbid SDR104/SDR50 - broken hw! */ > + sdhci-caps-mask = <0x3 0>; > + > + qcom,dll-config = <0x0007642c>; > + qcom,ddr-config = <0x80040868>; > + > + dma-coherent; > + > + status = "disabled"; > + > + sdhc2_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-19200000 { > + opp-hz = /bits/ 64 <19200000>; > + required-opps = <&rpmhpd_opp_min_svs>; > + }; > + > + opp-50000000 { > + opp-hz = /bits/ 64 <50000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-100000000 { > + opp-hz = /bits/ 64 <100000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-202000000 { > + opp-hz = /bits/ 64 <202000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + > + mdss: display-subsystem@ae00000 { > + compatible = "qcom,sm8650-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; > + reg-names = "mdss"; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, > + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "mdp0-mem", > + "mdp1-mem"; > + > + power-domains = <&dispcc MDSS_GDSC>; > + > + iommus = <&apps_smmu 0x1c00 0x2>; > + > + interrupt-controller; > + #interrupt-cells = <1>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8650-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", > + "vbif"; > + > + interrupts-extended = <&mdss 0>; > + > + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + dpu_intf2_out: endpoint { > + remote-endpoint = <&mdss_dsi1_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-325000000 { > + opp-hz = /bits/ 64 <325000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-514000000 { > + opp-hz = /bits/ 64 <514000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss_dsi0: dsi@ae94000 { > + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupts-extended = <&mdss 4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>; > + > + operating-points-v2 = <&mdss_dsi_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + phys = <&mdss_dsi0_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + mdss_dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + mdss_dsi0_out: endpoint { > + }; > + }; > + }; > + > + mdss_dsi_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + > + mdss_dsi0_phy: phy@ae95000 { > + compatible = "qcom,sm8650-dsi-phy-4nm"; > + reg = <0 0x0ae95000 0 0x200>, > + <0 0x0ae95200 0 0x280>, > + <0 0x0ae95500 0 0x400>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", > + "ref"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + mdss_dsi1: dsi@ae96000 { > + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae96000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupts-extended = <&mdss 5>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, > + <&dispcc DISP_CC_MDSS_ESC1_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, > + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi1_phy 0>, > + <&mdss_dsi1_phy 1>; > + > + operating-points-v2 = <&mdss_dsi_opp_table>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + > + phys = <&mdss_dsi1_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + > + mdss_dsi1_in: endpoint { > + remote-endpoint = <&dpu_intf2_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + > + mdss_dsi1_out: endpoint { > + }; > + }; > + }; > + }; > + > + mdss_dsi1_phy: phy@ae97000 { > + compatible = "qcom,sm8650-dsi-phy-4nm"; > + reg = <0 0x0ae97000 0 0x200>, > + <0 0x0ae97200 0 0x280>, > + <0 0x0ae97500 0 0x400>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", > + "ref"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + }; > + > + dispcc: clock-controller@af00000 { > + compatible = "qcom,sm8650-dispcc"; > + reg = <0 0x0af00000 0 0x20000>; > + > + clocks = <&bi_tcxo_div2>, > + <&bi_tcxo_ao_div2>, > + <&gcc GCC_DISP_AHB_CLK>, > + <&sleep_clk>, > + <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>, > + <&mdss_dsi1_phy 0>, > + <&mdss_dsi1_phy 1>, > + <0>, /* dp0 */ > + <0>, > + <0>, /* dp1 */ > + <0>, > + <0>, /* dp2 */ > + <0>, > + <0>, /* dp3 */ > + <0>; > + > + power-domains = <&rpmhpd RPMHPD_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > + > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + status = "disabled"; > + }; > + > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sm8650-snps-eusb2-phy", > + "qcom,sm8550-snps-eusb2-phy"; > + reg = <0 0x088e3000 0 0x154>; > + > + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; > + clock-names = "ref"; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + > + #phy-cells = <0>; > + > + status = "disabled"; > + }; > + > + usb_dp_qmpphy: phy@88e8000 { > + compatible = "qcom,sm8650-qmp-usb3-dp-phy"; > + reg = <0 0x088e8000 0 0x3000>; > + > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, > + <&rpmhcc RPMH_CXO_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; > + clock-names = "aux", > + "ref", > + "com_aux", > + "usb3_pipe"; > + > + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, > + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; > + reset-names = "phy", > + "common"; > + > + power-domains = <&gcc USB3_PHY_GDSC>; > + > + #clock-cells = <1>; > + #phy-cells = <1>; > + > + status = "disabled"; > + }; > + > + usb_1: usb@a6f8800 { > + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; > + reg = <0 0x0a6f8800 0 0x400>; > + > + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, > + <&pdc 15 IRQ_TYPE_EDGE_RISING>, > + <&pdc 14 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "hs_phy_irq", > + "ss_phy_irq", > + "dm_hs_phy_irq", > + "dp_hs_phy_irq"; > + > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>, > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&tcsr TCSR_USB3_CLKREF_EN>; > + clock-names = "cfg_noc", > + "core", > + "iface", > + "sleep", > + "mock_utmi", > + "xo"; > + > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, > + <&gcc GCC_USB30_PRIM_MASTER_CLK>; > + assigned-clock-rates = <19200000>, <200000000>; > + > + resets = <&gcc GCC_USB30_PRIM_BCR>; > + > + power-domains = <&gcc USB30_PRIM_GDSC>; > + required-opps = <&rpmhpd_opp_nom>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + status = "disabled"; > + > + usb_1_dwc3: usb@a600000 { > + compatible = "snps,dwc3"; > + reg = <0 0x0a600000 0 0xcd00>; > + > + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; > + > + iommus = <&apps_smmu 0x40 0>; > + > + phys = <&usb_1_hsphy>, > + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; > + phy-names = "usb2-phy", > + "usb3-phy"; > + > + snps,hird-threshold = /bits/ 8 <0x0>; > + snps,usb2-gadget-lpm-disable; > + snps,dis_u2_susphy_quirk; > + snps,dis_enblslpm_quirk; > + snps,dis-u1-entry-quirk; > + snps,dis-u2-entry-quirk; > + snps,is-utmi-l1-suspend; > + snps,usb3_lpm_capable; > + snps,usb2-lpm-disable; > + snps,has-lpm-erratum; > + tx-fifo-resize; > + > + dma-coherent; > + > + ports { > + #address-cells = <1>; > #size-cells = <0>; > > port@0 { > @@ -969,115 +3155,602 @@ pdc: interrupt-controller@b220000 { > <125 63 1>, <126 716 12>, > <138 251 5>, <143 244 4>; > > - #interrupt-cells = <2>; > - interrupt-controller; > - }; > + #interrupt-cells = <2>; > + interrupt-controller; > + }; > + > + tsens0: thermal-sensor@c228000 { > + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c228000 0 0x1000>, /* TM */ > + <0 0x0c222000 0 0x1000>; /* SROT */ > + > + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", > + "critical"; > + > + #qcom,sensors = <15>; > + > + #thermal-sensor-cells = <1>; > + }; > + > + tsens1: thermal-sensor@c229000 { > + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c229000 0 0x1000>, /* TM */ > + <0 0x0c223000 0 0x1000>; /* SROT */ > + > + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", > + "critical"; > + > + #qcom,sensors = <16>; > + > + #thermal-sensor-cells = <1>; > + }; > + > + tsens2: thermal-sensor@c22a000 { > + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; > + reg = <0 0x0c22a000 0 0x1000>, /* TM */ > + <0 0x0c224000 0 0x1000>; /* SROT */ > + > + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "uplow", > + "critical"; > + > + #qcom,sensors = <13>; > + > + #thermal-sensor-cells = <1>; > + }; > + > + aoss_qmp: power-management@c300000 { > + compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; > + reg = <0 0x0c300000 0 0x400>; > + > + interrupt-parent = <&ipcc>; > + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + #clock-cells = <0>; > + }; > + > + sram@c3f0000 { > + compatible = "qcom,rpmh-stats"; > + reg = <0 0x0c3f0000 0 0x400>; > + }; > + > + spmi_bus: spmi@c400000 { > + compatible = "qcom,spmi-pmic-arb"; > + reg = <0 0x0c400000 0 0x3000>, > + <0 0x0c500000 0 0x4000000>, > + <0 0x0c440000 0 0x80000>, > + <0 0x0c4c0000 0 0x20000>, > + <0 0x0c42d000 0 0x4000>; > + reg-names = "core", > + "chnls", > + "obsrvr", > + "intr", > + "cnfg"; > + > + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "periph_irq"; > + > + qcom,ee = <0>; > + qcom,channel = <0>; > + qcom,bus-id = <0>; > + > + interrupt-controller; > + #interrupt-cells = <4>; > + > + #address-cells = <2>; > + #size-cells = <0>; > + }; > + > + tlmm: pinctrl@f100000 { > + compatible = "qcom,sm8650-tlmm"; > + reg = <0 0x0f100000 0 0x300000>; > + > + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + > + gpio-controller; > + #gpio-cells = <2>; > + > + interrupt-controller; > + #interrupt-cells = <2>; > + > + gpio-ranges = <&tlmm 0 0 211>; > + > + wakeup-parent = <&pdc>; > + > + hub_i2c0_data_clk: hub-i2c0-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio64", "gpio65"; > + function = "i2chub0_se0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c1_data_clk: hub-i2c1-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio66", "gpio67"; > + function = "i2chub0_se1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c2_data_clk: hub-i2c2-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio68", "gpio69"; > + function = "i2chub0_se2"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c3_data_clk: hub-i2c3-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio70", "gpio71"; > + function = "i2chub0_se3"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c4_data_clk: hub-i2c4-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio72", "gpio73"; > + function = "i2chub0_se4"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c5_data_clk: hub-i2c5-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio74", "gpio75"; > + function = "i2chub0_se5"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c6_data_clk: hub-i2c6-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio76", "gpio77"; > + function = "i2chub0_se6"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c7_data_clk: hub-i2c7-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio78", "gpio79"; > + function = "i2chub0_se7"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c8_data_clk: hub-i2c8-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio206", "gpio207"; > + function = "i2chub0_se8"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + hub_i2c9_data_clk: hub-i2c9-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio80", "gpio81"; > + function = "i2chub0_se9"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + pcie0_default_state: pcie0-default-state { > + perst-pins { > + pins = "gpio94"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + clkreq-pins { > + pins = "gpio95"; > + function = "pcie0_clk_req_n"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + wake-pins { > + pins = "gpio96"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + pcie1_default_state: pcie1-default-state { > + perst-pins { > + pins = "gpio97"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-down; > + }; > + > + clkreq-pins { > + pins = "gpio98"; > + function = "pcie1_clk_req_n"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + wake-pins { > + pins = "gpio99"; > + function = "gpio"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + qup_i2c0_data_clk: qup-i2c0-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio32", "gpio33"; > + function = "qup1_se0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c1_data_clk: qup-i2c1-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio36", "gpio37"; > + function = "qup1_se1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c2_data_clk: qup-i2c2-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio40", "gpio41"; > + function = "qup1_se2"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c3_data_clk: qup-i2c3-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio44", "gpio45"; > + function = "qup1_se3"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c4_data_clk: qup-i2c4-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio48", "gpio49"; > + function = "qup1_se4"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c5_data_clk: qup-i2c5-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio52", "gpio53"; > + function = "qup1_se5"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c6_data_clk: qup-i2c6-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio56", "gpio57"; > + function = "qup1_se6"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c7_data_clk: qup-i2c7-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio60", "gpio61"; > + function = "qup1_se7"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c8_data_clk: qup-i2c8-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio0", "gpio1"; > + function = "qup2_se0"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c9_data_clk: qup-i2c9-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio4", "gpio5"; > + function = "qup2_se1"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c10_data_clk: qup-i2c10-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio8", "gpio9"; > + function = "qup2_se2"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c11_data_clk: qup-i2c11-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio12", "gpio13"; > + function = "qup2_se3"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c12_data_clk: qup-i2c12-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio16", "gpio17"; > + function = "qup2_se4"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c13_data_clk: qup-i2c13-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio20", "gpio21"; > + function = "qup2_se5"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_i2c14_data_clk: qup-i2c14-data-clk-state { > + /* SDA, SCL */ > + pins = "gpio24", "gpio25"; > + function = "qup2_se6"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + qup_spi0_cs: qup-spi0-cs-state { > + pins = "gpio35"; > + function = "qup1_se0"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi0_data_clk: qup-spi0-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio32", "gpio33", "gpio34"; > + function = "qup1_se0"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi1_cs: qup-spi1-cs-state { > + pins = "gpio39"; > + function = "qup1_se1"; > + drive-strength = <6>; > + bias-disable; > + }; > + > + qup_spi1_data_clk: qup-spi1-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio36", "gpio37", "gpio38"; > + function = "qup1_se1"; > + drive-strength = <6>; > + bias-disable; > + }; > > - tsens0: thermal-sensor@c228000 { > - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; > - reg = <0 0x0c228000 0 0x1000>, /* TM */ > - <0 0x0c222000 0 0x1000>; /* SROT */ > + qup_spi2_cs: qup-spi2-cs-state { > + pins = "gpio43"; > + function = "qup1_se2"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "uplow", > - "critical"; > + qup_spi2_data_clk: qup-spi2-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio40", "gpio41", "gpio42"; > + function = "qup1_se2"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #qcom,sensors = <15>; > + qup_spi3_cs: qup-spi3-cs-state { > + pins = "gpio47"; > + function = "qup1_se3"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #thermal-sensor-cells = <1>; > - }; > + qup_spi3_data_clk: qup-spi3-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio44", "gpio45", "gpio46"; > + function = "qup1_se3"; > + drive-strength = <6>; > + bias-disable; > + }; > > - tsens1: thermal-sensor@c229000 { > - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; > - reg = <0 0x0c229000 0 0x1000>, /* TM */ > - <0 0x0c223000 0 0x1000>; /* SROT */ > + qup_spi4_cs: qup-spi4-cs-state { > + pins = "gpio51"; > + function = "qup1_se4"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "uplow", > - "critical"; > + qup_spi4_data_clk: qup-spi4-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio48", "gpio49", "gpio50"; > + function = "qup1_se4"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #qcom,sensors = <16>; > + qup_spi5_cs: qup-spi5-cs-state { > + pins = "gpio55"; > + function = "qup1_se5"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #thermal-sensor-cells = <1>; > - }; > + qup_spi5_data_clk: qup-spi5-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio52", "gpio53", "gpio54"; > + function = "qup1_se5"; > + drive-strength = <6>; > + bias-disable; > + }; > > - tsens2: thermal-sensor@c22a000 { > - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; > - reg = <0 0x0c22a000 0 0x1000>, /* TM */ > - <0 0x0c224000 0 0x1000>; /* SROT */ > + qup_spi6_cs: qup-spi6-cs-state { > + pins = "gpio59"; > + function = "qup1_se6"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, > - <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "uplow", > - "critical"; > + qup_spi6_data_clk: qup-spi6-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio56", "gpio57", "gpio58"; > + function = "qup1_se6"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #qcom,sensors = <13>; > + qup_spi7_cs: qup-spi7-cs-state { > + pins = "gpio63"; > + function = "qup1_se7"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #thermal-sensor-cells = <1>; > - }; > + qup_spi7_data_clk: qup-spi7-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio60", "gpio61", "gpio62"; > + function = "qup1_se7"; > + drive-strength = <6>; > + bias-disable; > + }; > > - aoss_qmp: power-management@c300000 { > - compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; > - reg = <0 0x0c300000 0 0x400>; > + qup_spi8_cs: qup-spi8-cs-state { > + pins = "gpio3"; > + function = "qup2_se0"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupt-parent = <&ipcc>; > - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP > - IRQ_TYPE_EDGE_RISING>; > + qup_spi8_data_clk: qup-spi8-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio0", "gpio1", "gpio2"; > + function = "qup2_se0"; > + drive-strength = <6>; > + bias-disable; > + }; > > - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; > + qup_spi9_cs: qup-spi9-cs-state { > + pins = "gpio7"; > + function = "qup2_se1"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #clock-cells = <0>; > - }; > + qup_spi9_data_clk: qup-spi9-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio4", "gpio5", "gpio6"; > + function = "qup2_se1"; > + drive-strength = <6>; > + bias-disable; > + }; > > - sram@c3f0000 { > - compatible = "qcom,rpmh-stats"; > - reg = <0 0x0c3f0000 0 0x400>; > - }; > + qup_spi10_cs: qup-spi10-cs-state { > + pins = "gpio11"; > + function = "qup2_se2"; > + drive-strength = <6>; > + bias-disable; > + }; > > - spmi_bus: spmi@c400000 { > - compatible = "qcom,spmi-pmic-arb"; > - reg = <0 0x0c400000 0 0x3000>, > - <0 0x0c500000 0 0x4000000>, > - <0 0x0c440000 0 0x80000>, > - <0 0x0c4c0000 0 0x20000>, > - <0 0x0c42d000 0 0x4000>; > - reg-names = "core", > - "chnls", > - "obsrvr", > - "intr", > - "cnfg"; > + qup_spi10_data_clk: qup-spi10-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio8", "gpio9", "gpio10"; > + function = "qup2_se2"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; > - interrupt-names = "periph_irq"; > + qup_spi11_cs: qup-spi11-cs-state { > + pins = "gpio15"; > + function = "qup2_se3"; > + drive-strength = <6>; > + bias-disable; > + }; > > - qcom,ee = <0>; > - qcom,channel = <0>; > - qcom,bus-id = <0>; > + qup_spi11_data_clk: qup-spi11-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio12", "gpio13", "gpio14"; > + function = "qup2_se3"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupt-controller; > - #interrupt-cells = <4>; > + qup_spi12_cs: qup-spi12-cs-state { > + pins = "gpio19"; > + function = "qup2_se4"; > + drive-strength = <6>; > + bias-disable; > + }; > > - #address-cells = <2>; > - #size-cells = <0>; > - }; > + qup_spi12_data_clk: qup-spi12-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio16", "gpio17", "gpio18"; > + function = "qup2_se4"; > + drive-strength = <6>; > + bias-disable; > + }; > > - tlmm: pinctrl@f100000 { > - compatible = "qcom,sm8650-tlmm"; > - reg = <0 0x0f100000 0 0x300000>; > + qup_spi13_cs: qup-spi13-cs-state { > + pins = "gpio23"; > + function = "qup2_se5"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; > + qup_spi13_data_clk: qup-spi13-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio20", "gpio21", "gpio22"; > + function = "qup2_se5"; > + drive-strength = <6>; > + bias-disable; > + }; > > - gpio-controller; > - #gpio-cells = <2>; > + qup_spi14_cs: qup-spi14-cs-state { > + pins = "gpio27"; > + function = "qup2_se6"; > + drive-strength = <6>; > + bias-disable; > + }; > > - interrupt-controller; > - #interrupt-cells = <2>; > + qup_spi14_data_clk: qup-spi14-data-clk-state { > + /* MISO, MOSI, CLK */ > + pins = "gpio24", "gpio25", "gpio26"; > + function = "qup2_se6"; > + drive-strength = <6>; > + bias-disable; > + }; > > - gpio-ranges = <&tlmm 0 0 211>; > + qup_uart14_default: qup-uart14-default-state { > + /* TX, RX */ > + pins = "gpio26", "gpio27"; > + function = "qup2_se6"; > + drive-strength = <2>; > + bias-pull-up; > + }; > > - wakeup-parent = <&pdc>; > + qup_uart14_cts_rts: qup-uart14-cts-rts-state { > + /* CTS, RTS */ > + pins = "gpio24", "gpio25"; > + function = "qup2_se6"; > + drive-strength = <2>; > + bias-pull-down; > + }; > > qup_uart15_default: qup-uart15-default-state { > /* TX, RX */ > @@ -1086,6 +3759,46 @@ qup_uart15_default: qup-uart15-default-state { > drive-strength = <2>; > bias-disable; > }; > + > + sdc2_sleep: sdc2-sleep-state { > + clk-pins { > + pins = "sdc2_clk"; > + drive-strength = <2>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + drive-strength = <2>; > + bias-pull-up; > + }; > + }; > + > + sdc2_default: sdc2-default-state { > + clk-pins { > + pins = "sdc2_clk"; > + drive-strength = <16>; > + bias-disable; > + }; > + > + cmd-pins { > + pins = "sdc2_cmd"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + > + data-pins { > + pins = "sdc2_data"; > + drive-strength = <10>; > + bias-pull-up; > + }; > + }; > }; > > apps_smmu: iommu@15000000 { > @@ -1437,6 +4150,107 @@ cpufreq_hw: cpufreq@17d91000 { > #clock-cells = <1>; > }; > > + pmu@24091000 { > + compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; > + reg = <0 0x24091000 0 0x1000>; > + > + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; > + > + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; > + > + operating-points-v2 = <&llcc_bwmon_opp_table>; > + > + llcc_bwmon_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-0 { > + opp-peak-kBps = <2086000>; > + }; > + > + opp-1 { > + opp-peak-kBps = <2929000>; > + }; > + > + opp-2 { > + opp-peak-kBps = <5931000>; > + }; > + > + opp-3 { > + opp-peak-kBps = <6515000>; > + }; > + > + opp-4 { > + opp-peak-kBps = <7980000>; > + }; > + > + opp-5 { > + opp-peak-kBps = <10437000>; > + }; > + > + opp-6 { > + opp-peak-kBps = <12157000>; > + }; > + > + opp-7 { > + opp-peak-kBps = <14060000>; > + }; > + > + opp-8 { > + opp-peak-kBps = <16113000>; > + }; > + }; > + }; > + > + pmu@240b7400 { > + compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; > + reg = <0 0x240b7400 0 0x600>; > + > + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; > + > + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY > + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; > + > + operating-points-v2 = <&cpu_bwmon_opp_table>; > + > + cpu_bwmon_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-0 { > + opp-peak-kBps = <4577000>; > + }; > + > + opp-1 { > + opp-peak-kBps = <7110000>; > + }; > + > + opp-2 { > + opp-peak-kBps = <9155000>; > + }; > + > + opp-3 { > + opp-peak-kBps = <12298000>; > + }; > + > + opp-4 { > + opp-peak-kBps = <14236000>; > + }; > + > + opp-5 { > + opp-peak-kBps = <16265000>; > + }; > + }; > + }; > + > + gem_noc: interconnect@24100000 { > + compatible = "qcom,sm8650-gem-noc"; > + reg = <0 0x24100000 0 0xc5080>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > system-cache-controller@25000000 { > compatible = "qcom,sm8650-llcc"; > reg = <0 0x25000000 0 0x200000>, > @@ -1452,6 +4266,137 @@ system-cache-controller@25000000 { > > interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; > }; > + > + remoteproc_adsp: remoteproc@30000000 { > + compatible = "qcom,sm8650-adsp-pas"; > + reg = <0 0x30000000 0 0x100>; > + > + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", > + "fatal", > + "ready", > + "handover", > + "stop-ack"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "xo"; > + > + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + > + power-domains = <&rpmhpd RPMHPD_LCX>, > + <&rpmhpd RPMHPD_LMX>; > + power-domain-names = "lcx", > + "lmx"; > + > + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; > + > + qcom,qmp = <&aoss_qmp>; > + > + qcom,smem-states = <&smp2p_adsp_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + remoteproc_adsp_glink: glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_LPASS > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + qcom,remote-pid = <2>; > + > + label = "lpass"; > + > + fastrpc { > + compatible = "qcom,fastrpc"; > + > + qcom,glink-channels = "fastrpcglink-apps-dsp"; > + > + label = "adsp"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > + > + nsp_noc: interconnect@320c0000 { > + compatible = "qcom,sm8650-nsp-noc"; > + reg = <0 0x320c0000 0 0xf080>; > + > + qcom,bcm-voters = <&apps_bcm_voter>; > + > + #interconnect-cells = <2>; > + }; > + > + remoteproc_cdsp: remoteproc@32300000 { > + compatible = "qcom,sm8650-cdsp-pas"; > + reg = <0 0x32300000 0 0x1400000>; > + > + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, > + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; > + interrupt-names = "wdog", > + "fatal", > + "ready", > + "handover", > + "stop-ack"; > + > + clocks = <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "xo"; > + > + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; > + > + power-domains = <&rpmhpd RPMHPD_CX>, > + <&rpmhpd RPMHPD_MXC>, > + <&rpmhpd RPMHPD_NSP>; > + power-domain-names = "cx", > + "mxc", > + "nsp"; > + > + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; > + > + qcom,qmp = <&aoss_qmp>; > + > + qcom,smem-states = <&smp2p_cdsp_out 0>; > + qcom,smem-state-names = "stop"; > + > + status = "disabled"; > + > + glink-edge { > + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP > + IPCC_MPROC_SIGNAL_GLINK_QMP > + IRQ_TYPE_EDGE_RISING>; > + > + mboxes = <&ipcc IPCC_CLIENT_CDSP > + IPCC_MPROC_SIGNAL_GLINK_QMP>; > + > + qcom,remote-pid = <5>; > + > + label = "cdsp"; > + > + fastrpc { > + compatible = "qcom,fastrpc"; > + > + qcom,glink-channels = "fastrpcglink-apps-dsp"; > + > + label = "cdsp"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + }; > + }; > + }; > }; > > thermal-zones { > > -- > 2.34.1 > > -- With best wishes Dmitry ^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH v3 6/8] arm64: dts: qcom: sm8650: add interconnect dependent device nodes 2023-11-21 11:24 ` Dmitry Baryshkov @ 2023-11-21 13:40 ` Neil Armstrong 0 siblings, 0 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 13:40 UTC (permalink / raw) To: Dmitry Baryshkov Cc: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley, linux-arm-msm, devicetree, linux-kernel On 21/11/2023 12:24, Dmitry Baryshkov wrote: > On Tue, 21 Nov 2023 at 13:00, Neil Armstrong <neil.armstrong@linaro.org> wrote: >> >> Add Hardware nodes that depends on an interconnect property to >> be valid. >> >> The includes: >> - all QUP i2s/spi nodes >> - PCIe >> - UFS >> - SDHCI >> - Display >> - HWMON >> >> Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8650.dtsi | 3467 +++++++++++++++++++++++++++++++--- >> 1 file changed, 3206 insertions(+), 261 deletions(-) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8650.dtsi b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> index e6a862230c30..8e21335073bc 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8650.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8650.dtsi >> @@ -11,6 +11,8 @@ >> #include <dt-bindings/dma/qcom-gpi.h> >> #include <dt-bindings/firmware/qcom,scm.h> >> #include <dt-bindings/gpio/gpio.h> >> +#include <dt-bindings/interconnect/qcom,icc.h> >> +#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h> >> #include <dt-bindings/interrupt-controller/arm-gic.h> >> #include <dt-bindings/mailbox/qcom-ipcc.h> >> #include <dt-bindings/phy/phy-qcom-qmp.h> >> @@ -57,6 +59,11 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk { >> clock-mult = <1>; >> clock-div = <2>; >> }; >> + >> + pcie_1_phy_aux_clk: pcie-1-phy-aux-clk { >> + compatible = "fixed-clock"; >> + #clock-cells = <0>; >> + }; > > I think this clock is provided by the PHY. Let's attribute it this way. this is different from the pcie1_phy clock, and was already defined like this from sm8550 & sm8450, this is the same for sm8650. > >> }; >> >> cpus { >> @@ -363,9 +370,23 @@ CLUSTER_SLEEP_1: cluster-sleep-1 { >> firmware { >> scm: scm { >> compatible = "qcom,scm-sm8650", "qcom,scm"; >> + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> }; >> }; >> >> + clk_virt: interconnect-0 { >> + compatible = "qcom,sm8650-clk-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + mc_virt: interconnect-1 { >> + compatible = "qcom,sm8650-mc-virt"; >> + #interconnect-cells = <2>; >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> memory@a0000000 { >> device_type = "memory"; >> /* We expect the bootloader to fill in the size */ >> @@ -626,6 +647,95 @@ llcc_lpi_mem: llcc-lpi@ff800000 { >> }; >> }; >> >> + smp2p-adsp { >> + compatible = "qcom,smp2p"; >> + >> + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS >> + IPCC_MPROC_SIGNAL_SMP2P >> + IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&ipcc IPCC_CLIENT_LPASS >> + IPCC_MPROC_SIGNAL_SMP2P>; >> + >> + qcom,smem = <443>, <429>; >> + qcom,local-pid = <0>; >> + qcom,remote-pid = <2>; >> + >> + smp2p_adsp_out: master-kernel { >> + qcom,entry-name = "master-kernel"; >> + #qcom,smem-state-cells = <1>; >> + }; >> + >> + smp2p_adsp_in: slave-kernel { >> + qcom,entry-name = "slave-kernel"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + }; >> + >> + smp2p-cdsp { >> + compatible = "qcom,smp2p"; >> + >> + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP >> + IPCC_MPROC_SIGNAL_SMP2P >> + IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&ipcc IPCC_CLIENT_CDSP >> + IPCC_MPROC_SIGNAL_SMP2P>; >> + >> + qcom,smem = <94>, <432>; >> + qcom,local-pid = <0>; >> + qcom,remote-pid = <5>; >> + >> + smp2p_cdsp_out: master-kernel { >> + qcom,entry-name = "master-kernel"; >> + #qcom,smem-state-cells = <1>; >> + }; >> + >> + smp2p_cdsp_in: slave-kernel { >> + qcom,entry-name = "slave-kernel"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + }; >> + >> + smp2p-modem { >> + compatible = "qcom,smp2p"; >> + >> + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS >> + IPCC_MPROC_SIGNAL_SMP2P >> + IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&ipcc IPCC_CLIENT_MPSS >> + IPCC_MPROC_SIGNAL_SMP2P>; >> + >> + qcom,smem = <435>, <428>; >> + qcom,local-pid = <0>; >> + qcom,remote-pid = <1>; >> + >> + smp2p_modem_out: master-kernel { >> + qcom,entry-name = "master-kernel"; >> + #qcom,smem-state-cells = <1>; >> + }; >> + >> + smp2p_modem_in: slave-kernel { >> + qcom,entry-name = "slave-kernel"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + >> + ipa_smp2p_out: ipa-ap-to-modem { >> + qcom,entry-name = "ipa"; >> + #qcom,smem-state-cells = <1>; >> + }; >> + >> + ipa_smp2p_in: ipa-modem-to-ap { >> + qcom,entry-name = "ipa"; >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + }; >> + }; >> + >> soc: soc@0 { >> compatible = "simple-bus"; >> >> @@ -641,13 +751,13 @@ gcc: clock-controller@100000 { >> clocks = <&bi_tcxo_div2>, >> <&bi_tcxo_ao_div2>, >> <&sleep_clk>, >> - <0>, >> - <0>, >> - <0>, >> - <0>, >> - <0>, >> - <0>, >> - <0>; >> + <&pcie0_phy>, >> + <&pcie1_phy>, >> + <&pcie_1_phy_aux_clk>, >> + <&ufs_mem_phy 0>, >> + <&ufs_mem_phy 1>, >> + <&ufs_mem_phy 2>, >> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; >> >> #clock-cells = <1>; >> #reset-cells = <1>; >> @@ -712,234 +822,2310 @@ qupv3_id_1: geniqup@8c0000 { >> >> status = "disabled"; >> >> - uart15: serial@89c000 { >> - compatible = "qcom,geni-debug-uart"; >> - reg = <0 0x0089c000 0 0x4000>; > > I think, git diff got it wrong here. Is there any chance we can help it? I can with git format-patch and --minimal but b4 doesn't implement such thing... I'll investigate to see if it's possible. > >> + i2c8: i2c@880000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00880000 0 0x4000>; >> >> - interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; >> + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; >> >> - clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; >> clock-names = "se"; >> >> - pinctrl-0 = <&qup_uart15_default>; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, >> + <&gpi_dma2 1 0 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c8_data_clk>; >> pinctrl-names = "default"; >> >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> status = "disabled"; >> }; >> - }; >> >> - gpi_dma1: dma-controller@a00000 { >> - compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; >> - reg = <0 0x00a00000 0 0x60000>; >> + spi8: spi@880000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00880000 0 0x4000>; >> >> - interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >> + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; >> >> - dma-channels = <12>; >> - dma-channel-mask = <0xc>; >> - #dma-cells = <3>; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; >> + clock-names = "se"; >> >> - iommus = <&apps_smmu 0xb6 0>; >> - dma-coherent; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, >> + <&gpi_dma2 1 0 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; >> + pinctrl-names = "default"; >> >> - status = "disabled"; >> - }; >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - rng: rng@10c3000 { >> - compatible = "qcom,sm8650-trng", "qcom,trng"; >> - reg = <0 0x010c3000 0 0x1000>; >> - }; >> + status = "disabled"; >> + }; >> >> - ice: crypto@1d88000 { >> - compatible = "qcom,sm8650-inline-crypto-engine", >> - "qcom,inline-crypto-engine"; >> - reg = <0 0x01d88000 0 0x8000>; >> + i2c9: i2c@884000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00884000 0 0x4000>; >> >> - clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >> - }; >> + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; >> >> - tcsr_mutex: hwlock@1f40000 { >> - compatible = "qcom,tcsr-mutex"; >> - reg = <0 0x01f40000 0 0x20000>; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; >> + clock-names = "se"; >> >> - #hwlock-cells = <1>; >> - }; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, >> + <&gpi_dma2 1 1 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c9_data_clk>; >> + pinctrl-names = "default"; >> >> - tcsr: clock-controller@1fc0000 { >> - compatible = "qcom,sm8650-tcsr", "syscon"; >> - reg = <0 0x01fc0000 0 0xa0000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - clocks = <&rpmhcc RPMH_CXO_CLK>; >> + status = "disabled"; >> + }; >> >> - #clock-cells = <1>; >> - #reset-cells = <1>; >> - }; >> + spi9: spi@884000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00884000 0 0x4000>; >> >> - gpucc: clock-controller@3d90000 { >> - compatible = "qcom,sm8650-gpucc"; >> - reg = <0 0x03d90000 0 0xa000>; >> + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; >> >> - clocks = <&bi_tcxo_div2>, >> - <&gcc GCC_GPU_GPLL0_CLK_SRC>, >> - <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; >> + clock-names = "se"; >> >> - #clock-cells = <1>; >> - #reset-cells = <1>; >> - #power-domain-cells = <1>; >> - }; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, >> + <&gpi_dma2 1 1 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; >> + pinctrl-names = "default"; >> >> - dispcc: clock-controller@af00000 { >> - compatible = "qcom,sm8650-dispcc"; >> - reg = <0 0x0af00000 0 0x20000>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - clocks = <&bi_tcxo_div2>, >> - <&bi_tcxo_ao_div2>, >> - <&gcc GCC_DISP_AHB_CLK>, >> - <&sleep_clk>, >> - <0>, /* dsi0 */ >> - <0>, >> - <0>, /* dsi1 */ >> - <0>, >> - <0>, /* dp0 */ >> - <0>, >> - <0>, /* dp1 */ >> - <0>, >> - <0>, /* dp2 */ >> - <0>, >> - <0>, /* dp3 */ >> - <0>; >> + status = "disabled"; >> + }; >> >> - power-domains = <&rpmhpd RPMHPD_MMCX>; >> - required-opps = <&rpmhpd_opp_low_svs>; >> + i2c10: i2c@888000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00888000 0 0x4000>; >> >> - #clock-cells = <1>; >> - #reset-cells = <1>; >> - #power-domain-cells = <1>; >> + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; >> >> - status = "disabled"; >> - }; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; >> + clock-names = "se"; >> >> - usb_1_hsphy: phy@88e3000 { >> - compatible = "qcom,sm8650-snps-eusb2-phy", >> - "qcom,sm8550-snps-eusb2-phy"; >> - reg = <0 0x088e3000 0 0x154>; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, >> + <&gpi_dma2 1 2 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c10_data_clk>; >> + pinctrl-names = "default"; >> >> - clocks = <&tcsr TCSR_USB2_CLKREF_EN>; >> - clock-names = "ref"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; >> + status = "disabled"; >> + }; >> >> - #phy-cells = <0>; >> + spi10: spi@888000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00888000 0 0x4000>; >> >> - status = "disabled"; >> - }; >> + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; >> >> - usb_dp_qmpphy: phy@88e8000 { >> - compatible = "qcom,sm8650-qmp-usb3-dp-phy"; >> - reg = <0 0x088e8000 0 0x3000>; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; >> + clock-names = "se"; >> >> - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, >> - <&rpmhcc RPMH_CXO_CLK>, >> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, >> - <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >> - clock-names = "aux", >> - "ref", >> - "com_aux", >> - "usb3_pipe"; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, >> + <&gpi_dma2 1 2 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; >> + pinctrl-names = "default"; >> >> - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, >> - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; >> - reset-names = "phy", >> - "common"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - power-domains = <&gcc USB3_PHY_GDSC>; >> + status = "disabled"; >> + }; >> >> - #clock-cells = <1>; >> - #phy-cells = <1>; >> + i2c11: i2c@88c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x0088c000 0 0x4000>; >> >> - status = "disabled"; >> - }; >> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; >> >> - usb_1: usb@a6f8800 { >> - compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; >> - reg = <0 0x0a6f8800 0 0x400>; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; >> + clock-names = "se"; >> >> - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >> - <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, >> - <&pdc 15 IRQ_TYPE_EDGE_RISING>, >> - <&pdc 14 IRQ_TYPE_EDGE_RISING>; >> - interrupt-names = "hs_phy_irq", >> - "ss_phy_irq", >> - "dm_hs_phy_irq", >> - "dp_hs_phy_irq"; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, >> + <&gpi_dma2 1 3 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c11_data_clk>; >> + pinctrl-names = "default"; >> >> - clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, >> - <&gcc GCC_USB30_PRIM_MASTER_CLK>, >> - <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, >> - <&gcc GCC_USB30_PRIM_SLEEP_CLK>, >> - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> - <&tcsr TCSR_USB3_CLKREF_EN>; >> - clock-names = "cfg_noc", >> - "core", >> - "iface", >> - "sleep", >> - "mock_utmi", >> - "xo"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> - <&gcc GCC_USB30_PRIM_MASTER_CLK>; >> - assigned-clock-rates = <19200000>, <200000000>; >> + status = "disabled"; >> + }; >> >> - resets = <&gcc GCC_USB30_PRIM_BCR>; >> + spi11: spi@88c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x0088c000 0 0x4000>; >> >> - power-domains = <&gcc USB30_PRIM_GDSC>; >> - required-opps = <&rpmhpd_opp_nom>; >> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; >> >> - #address-cells = <2>; >> - #size-cells = <2>; >> - ranges; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; >> + clock-names = "se"; >> >> - status = "disabled"; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, >> + <&gpi_dma2 1 3 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; >> + pinctrl-names = "default"; >> >> - usb_1_dwc3: usb@a600000 { >> - compatible = "snps,dwc3"; >> - reg = <0 0x0a600000 0 0xcd00>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> >> - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >> + status = "disabled"; >> + }; >> >> - iommus = <&apps_smmu 0x40 0>; >> + i2c12: i2c@890000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00890000 0 0x4000>; >> >> - phys = <&usb_1_hsphy>, >> - <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; >> - phy-names = "usb2-phy", >> - "usb3-phy"; >> + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; >> >> - snps,hird-threshold = /bits/ 8 <0x0>; >> - snps,usb2-gadget-lpm-disable; >> - snps,dis_u2_susphy_quirk; >> - snps,dis_enblslpm_quirk; >> - snps,dis-u1-entry-quirk; >> - snps,dis-u2-entry-quirk; >> - snps,is-utmi-l1-suspend; >> - snps,usb3_lpm_capable; >> - snps,usb2-lpm-disable; >> - snps,has-lpm-erratum; >> - tx-fifo-resize; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; >> + clock-names = "se"; >> >> - dma-coherent; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, >> + <&gpi_dma2 1 4 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c12_data_clk>; >> + pinctrl-names = "default"; >> >> - ports { >> - #address-cells = <1>; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi12: spi@890000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00890000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 4 QCOM_GPI_SPI>, >> + <&gpi_dma2 1 4 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c13: i2c@894000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00894000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>, >> + <&gpi_dma2 1 5 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c13_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi13: spi@894000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00894000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma2 0 5 QCOM_GPI_SPI>, >> + <&gpi_dma2 1 5 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + uart14: serial@898000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0 0x00898000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&qup_uart14_default>, <&qup_uart14_cts_rts>; >> + pinctrl-names = "default"; >> + >> + status = "disabled"; >> + }; >> + >> + uart15: serial@89c000 { >> + compatible = "qcom,geni-debug-uart"; >> + reg = <0 0x0089c000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&qup_uart15_default>; >> + pinctrl-names = "default"; >> + >> + status = "disabled"; >> + }; >> + }; >> + >> + i2c_master_hub_0: geniqup@9c0000 { >> + compatible = "qcom,geni-se-i2c-master-hub"; >> + reg = <0 0x009c0000 0 0x2000>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; >> + clock-names = "s-ahb"; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + status = "disabled"; >> + >> + i2c_hub_0: i2c@980000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x00980000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c0_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_1: i2c@984000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x00984000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c1_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_2: i2c@988000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x00988000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c2_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_3: i2c@98c000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x0098c000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c3_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_4: i2c@990000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x00990000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c4_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_5: i2c@994000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x00994000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S5_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c5_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_6: i2c@998000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x00998000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S6_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c6_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_7: i2c@99c000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x0099c000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S7_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c7_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_8: i2c@9a0000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x009a0000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S8_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c8_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c_hub_9: i2c@9a4000 { >> + compatible = "qcom,geni-i2c-master-hub"; >> + reg = <0 0x009a4000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_I2C_S9_CLK>, >> + <&gcc GCC_QUPV3_I2C_CORE_CLK>; >> + clock-names = "se", >> + "core"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config"; >> + >> + pinctrl-0 = <&hub_i2c9_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + }; >> + >> + gpi_dma1: dma-controller@a00000 { >> + compatible = "qcom,sm8650-gpi-dma", "qcom,sm6350-gpi-dma"; >> + reg = <0 0x00a00000 0 0x60000>; >> + >> + interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; >> + >> + dma-channels = <12>; >> + dma-channel-mask = <0xc>; >> + #dma-cells = <3>; >> + >> + iommus = <&apps_smmu 0xb6 0>; >> + dma-coherent; >> + >> + status = "disabled"; >> + }; >> + >> + qupv3_id_0: geniqup@ac0000 { >> + compatible = "qcom,geni-se-qup"; >> + reg = <0 0x00ac0000 0 0x2000>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, >> + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; >> + clock-names = "m-ahb", >> + "s-ahb"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core"; >> + >> + iommus = <&apps_smmu 0xa3 0>; >> + >> + dma-coherent; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + status = "disabled"; >> + >> + i2c0: i2c@a80000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a80000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 0 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c0_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi0: spi@a80000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a80000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 0 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c1: i2c@a84000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a84000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 1 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c1_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi1: spi@a84000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a84000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 1 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c2: i2c@a88000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a88000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 2 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c2_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi2: spi@a88000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a88000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 2 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c3: i2c@a8c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a8c000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 3 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c3_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi3: spi@a8c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a8c000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 3 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c4: i2c@a90000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a90000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 4 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c4_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi4: spi@a90000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a90000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 4 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c5: i2c@a94000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a94000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 5 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c5_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi5: spi@a94000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a94000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 5 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c6: i2c@a98000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a98000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 6 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c6_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi6: spi@a98000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a98000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 6 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + i2c7: i2c@a9c000 { >> + compatible = "qcom,geni-i2c"; >> + reg = <0 0x00a9c000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, >> + <&gpi_dma1 1 7 QCOM_GPI_I2C>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_i2c7_data_clk>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + spi7: spi@a9c000 { >> + compatible = "qcom,geni-spi"; >> + reg = <0 0x00a9c000 0 0x4000>; >> + >> + interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; >> + clock-names = "se"; >> + >> + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, >> + <&aggre1_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", >> + "qup-config", >> + "qup-memory"; >> + >> + dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, >> + <&gpi_dma1 1 7 QCOM_GPI_SPI>; >> + dma-names = "tx", >> + "rx"; >> + >> + pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; >> + pinctrl-names = "default"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + }; >> + >> + cnoc_main: interconnect@1500000 { >> + compatible = "qcom,sm8650-cnoc-main"; >> + reg = <0 0x01500000 0 0x14080>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + config_noc: interconnect@1600000 { >> + compatible = "qcom,sm8650-config-noc"; >> + reg = <0 0x01600000 0 0x6200>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + system_noc: interconnect@1680000 { >> + compatible = "qcom,sm8650-system-noc"; >> + reg = <0 0x01680000 0 0x1d080>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + pcie_noc: interconnect@16c0000 { >> + compatible = "qcom,sm8650-pcie-anoc"; >> + reg = <0 0x016c0000 0 0x12200>; >> + >> + clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, >> + <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + aggre1_noc: interconnect@16e0000 { >> + compatible = "qcom,sm8650-aggre1-noc"; >> + reg = <0 0x016e0000 0 0x16400>; >> + >> + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + aggre2_noc: interconnect@1700000 { >> + compatible = "qcom,sm8650-aggre2-noc"; >> + reg = <0 0x01700000 0 0x1e400>; >> + >> + clocks = <&rpmhcc RPMH_IPA_CLK>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + mmss_noc: interconnect@1780000 { >> + compatible = "qcom,sm8650-mmss-noc"; >> + reg = <0 0x01780000 0 0x5b800>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + rng: rng@10c3000 { >> + compatible = "qcom,sm8650-trng", "qcom,trng"; >> + reg = <0 0x010c3000 0 0x1000>; >> + }; >> + >> + pcie0: pci@1c00000 { >> + device_type = "pci"; >> + compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; >> + reg = <0 0x01c00000 0 0x3000>, >> + <0 0x60000000 0 0xf1d>, >> + <0 0x60000f20 0 0xa8>, >> + <0 0x60001000 0 0x1000>, >> + <0 0x60100000 0 0x100000>; >> + reg-names = "parf", "dbi", "elbi", "atu", "config"; >> + >> + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "msi"; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, >> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, >> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, >> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a", >> + "ddrss_sf_tbu", >> + "noc_aggr", >> + "cnoc_sf_axi"; >> + >> + resets = <&gcc GCC_PCIE_0_BCR>; >> + reset-names = "pci"; >> + >> + interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "pcie-mem", >> + "cpu-pcie"; >> + >> + power-domains = <&gcc PCIE_0_GDSC>; >> + >> + iommu-map = <0 &apps_smmu 0x1400 0x1>, >> + <0x100 &apps_smmu 0x1401 0x1>; >> + >> + interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + #interrupt-cells = <1>; >> + >> + linux,pci-domain = <0>; >> + num-lanes = <2>; >> + bus-range = <0 0xff>; >> + >> + phys = <&pcie0_phy>; >> + phy-names = "pciephy"; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0 0x00000000 0 0x60200000 0 0x100000>, >> + <0x02000000 0 0x60300000 0 0x60300000 0 0x3d00000>; >> + >> + dma-coherent; >> + >> + status = "disabled"; >> + }; >> + >> + pcie0_phy: phy@1c06000 { >> + compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy"; >> + reg = <0 0x01c06000 0 0x2000>; >> + >> + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, >> + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, >> + <&tcsr TCSR_PCIE_0_CLKREF_EN>, >> + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, >> + <&gcc GCC_PCIE_0_PIPE_CLK>; >> + clock-names = "aux", >> + "cfg_ahb", >> + "ref", >> + "rchng", >> + "pipe"; >> + >> + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; >> + assigned-clock-rates = <100000000>; >> + >> + resets = <&gcc GCC_PCIE_0_PHY_BCR>; >> + reset-names = "phy"; >> + >> + power-domains = <&gcc PCIE_0_PHY_GDSC>; >> + >> + #clock-cells = <0>; >> + clock-output-names = "pcie0_pipe_clk"; >> + >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + pcie1: pci@1c08000 { >> + device_type = "pci"; >> + compatible = "qcom,pcie-sm8650", "qcom,pcie-sm8550"; >> + reg = <0 0x01c08000 0 0x3000>, >> + <0 0x40000000 0 0xf1d>, >> + <0 0x40000f20 0 0xa8>, >> + <0 0x40001000 0 0x1000>, >> + <0 0x40100000 0 0x100000>; >> + reg-names = "parf", >> + "dbi", >> + "elbi", >> + "atu", >> + "config"; >> + >> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "msi"; >> + >> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>, >> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, >> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, >> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, >> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, >> + <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, >> + <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, >> + <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; >> + clock-names = "aux", >> + "cfg", >> + "bus_master", >> + "bus_slave", >> + "slave_q2a", >> + "ddrss_sf_tbu", >> + "noc_aggr", >> + "cnoc_sf_axi"; >> + >> + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; >> + assigned-clock-rates = <19200000>; >> + >> + resets = <&gcc GCC_PCIE_1_BCR>, >> + <&gcc GCC_PCIE_1_LINK_DOWN_BCR>; >> + reset-names = "pci", >> + "link_down"; >> + >> + interconnects = <&pcie_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &cnoc_main SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "pcie-mem", >> + "cpu-pcie"; >> + >> + power-domains = <&gcc PCIE_1_GDSC>; >> + >> + iommu-map = <0 &apps_smmu 0x1480 0x1>, >> + <0x100 &apps_smmu 0x1481 0x1>; >> + >> + interrupt-map = <0 0 0 1 &intc 0 0 0 434 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 2 &intc 0 0 0 435 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 3 &intc 0 0 0 438 IRQ_TYPE_LEVEL_HIGH>, >> + <0 0 0 4 &intc 0 0 0 439 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-map-mask = <0 0 0 0x7>; >> + #interrupt-cells = <1>; >> + >> + linux,pci-domain = <1>; >> + num-lanes = <2>; >> + bus-range = <0 0xff>; >> + >> + phys = <&pcie1_phy>; >> + phy-names = "pciephy"; >> + >> + dma-coherent; >> + >> + #address-cells = <3>; >> + #size-cells = <2>; >> + ranges = <0x01000000 0 0x00000000 0 0x40200000 0 0x100000>, >> + <0x02000000 0 0x40300000 0 0x40300000 0 0x1fd00000>; >> + >> + status = "disabled"; >> + }; >> + >> + pcie1_phy: phy@1c0e000 { >> + compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy"; >> + reg = <0 0x01c0e000 0 0x2000>; >> + >> + clocks = <&gcc GCC_PCIE_1_PHY_AUX_CLK>, >> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, >> + <&tcsr TCSR_PCIE_1_CLKREF_EN>, >> + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, >> + <&gcc GCC_PCIE_1_PIPE_CLK>; >> + clock-names = "aux", >> + "cfg_ahb", >> + "ref", >> + "rchng", >> + "pipe"; >> + >> + assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>; >> + assigned-clock-rates = <100000000>; >> + >> + resets = <&gcc GCC_PCIE_1_PHY_BCR>, >> + <&gcc GCC_PCIE_1_NOCSR_COM_PHY_BCR>; >> + reset-names = "phy", >> + "phy_nocsr"; >> + >> + power-domains = <&gcc PCIE_1_PHY_GDSC>; >> + >> + #clock-cells = <0>; >> + clock-output-names = "pcie1_pipe_clk"; >> + >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + cryptobam: dma-controller@1dc4000 { >> + compatible = "qcom,bam-v1.7.0"; >> + reg = <0 0x01dc4000 0 0x28000>; >> + >> + interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; >> + >> + #dma-cells = <1>; >> + >> + iommus = <&apps_smmu 0x480 0>, >> + <&apps_smmu 0x481 0>; >> + >> + qcom,ee = <0>; >> + qcom,controlled-remotely; >> + }; >> + >> + crypto: crypto@1dfa000 { >> + compatible = "qcom,sm8650-qce", "qcom,sm8150-qce", "qcom,qce"; >> + reg = <0 0x01dfa000 0 0x6000>; >> + >> + interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "memory"; >> + >> + dmas = <&cryptobam 4>, <&cryptobam 5>; >> + dma-names = "rx", "tx"; >> + >> + iommus = <&apps_smmu 0x480 0>, >> + <&apps_smmu 0x481 0>; >> + }; >> + >> + ufs_mem_phy: phy@1d80000 { >> + compatible = "qcom,sm8650-qmp-ufs-phy"; >> + reg = <0 0x01d80000 0 0x2000>; >> + >> + clocks = <&tcsr TCSR_UFS_CLKREF_EN>, >> + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>; >> + clock-names = "ref", >> + "ref_aux"; >> + >> + resets = <&ufs_mem_hc 0>; >> + reset-names = "ufsphy"; >> + >> + power-domains = <&gcc UFS_MEM_PHY_GDSC>; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + ufs_mem_hc: ufs@1d84000 { >> + compatible = "qcom,sm8650-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; >> + reg = <0 0x01d84000 0 0x3000>; >> + >> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> + <&gcc GCC_UFS_PHY_AHB_CLK>, >> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> + <&tcsr TCSR_UFS_PAD_CLKREF_EN>, >> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, >> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; >> + clock-names = "core_clk", >> + "bus_aggr_clk", >> + "iface_clk", >> + "core_clk_unipro", >> + "ref_clk", >> + "tx_lane0_sync_clk", >> + "rx_lane0_sync_clk", >> + "rx_lane1_sync_clk"; >> + freq-table-hz = <100000000 403000000>, >> + <0 0>, >> + <0 0>, >> + <100000000 403000000>, >> + <100000000 403000000>, >> + <0 0>, >> + <0 0>, >> + <0 0>; >> + >> + resets = <&gcc GCC_UFS_PHY_BCR>; >> + reset-names = "rst"; >> + >> + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "ufs-ddr", >> + "cpu-ufs"; >> + >> + power-domains = <&gcc UFS_PHY_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + iommus = <&apps_smmu 0x60 0>; >> + >> + lanes-per-direction = <2>; >> + qcom,ice = <&ice>; >> + >> + phys = <&ufs_mem_phy>; >> + phy-names = "ufsphy"; >> + >> + #reset-cells = <1>; >> + >> + status = "disabled"; >> + }; >> + >> + ice: crypto@1d88000 { >> + compatible = "qcom,sm8650-inline-crypto-engine", >> + "qcom,inline-crypto-engine"; >> + reg = <0 0x01d88000 0 0x8000>; >> + >> + clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; >> + }; >> + >> + tcsr_mutex: hwlock@1f40000 { >> + compatible = "qcom,tcsr-mutex"; >> + reg = <0 0x01f40000 0 0x20000>; >> + >> + #hwlock-cells = <1>; >> + }; >> + >> + tcsr: clock-controller@1fc0000 { >> + compatible = "qcom,sm8650-tcsr", "syscon"; >> + reg = <0 0x01fc0000 0 0xa0000>; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>; >> + >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + }; >> + >> + gpucc: clock-controller@3d90000 { >> + compatible = "qcom,sm8650-gpucc"; >> + reg = <0 0x03d90000 0 0xa000>; >> + >> + clocks = <&bi_tcxo_div2>, >> + <&gcc GCC_GPU_GPLL0_CLK_SRC>, >> + <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; >> + >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + }; >> + >> + remoteproc_mpss: remoteproc@4080000 { >> + compatible = "qcom,sm8650-mpss-pas"; >> + reg = <0 0x04080000 0 0x4040>; >> + >> + interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_modem_in 0 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_modem_in 1 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_modem_in 2 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_modem_in 3 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_modem_in 7 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "wdog", >> + "fatal", >> + "ready", >> + "handover", >> + "stop-ack", >> + "shutdown-ack"; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "xo"; >> + >> + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + >> + power-domains = <&rpmhpd RPMHPD_CX>, >> + <&rpmhpd RPMHPD_MSS>; >> + power-domain-names = "cx", >> + "mss"; >> + >> + memory-region = <&mpss_mem>, <&q6_mpss_dtb_mem>, >> + <&mpss_dsm_mem>, <&mpss_dsm_mem_2>; >> + >> + qcom,qmp = <&aoss_qmp>; >> + >> + qcom,smem-states = <&smp2p_modem_out 0>; >> + qcom,smem-state-names = "stop"; >> + >> + status = "disabled"; >> + >> + glink-edge { >> + interrupts-extended = <&ipcc IPCC_CLIENT_MPSS >> + IPCC_MPROC_SIGNAL_GLINK_QMP >> + IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&ipcc IPCC_CLIENT_MPSS >> + IPCC_MPROC_SIGNAL_GLINK_QMP>; >> + >> + qcom,remote-pid = <1>; >> + >> + label = "mpss"; >> + }; >> + }; >> + >> + lpass_lpiaon_noc: interconnect@7400000 { >> + compatible = "qcom,sm8650-lpass-lpiaon-noc"; >> + reg = <0 0x07400000 0 0x19080>; >> + >> + #interconnect-cells = <2>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + lpass_lpicx_noc: interconnect@7430000 { >> + compatible = "qcom,sm8650-lpass-lpicx-noc"; >> + reg = <0 0x07430000 0 0x3a200>; >> + >> + #interconnect-cells = <2>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + lpass_ag_noc: interconnect@7e40000 { >> + compatible = "qcom,sm8650-lpass-ag-noc"; >> + reg = <0 0x07e40000 0 0xe080>; >> + >> + #interconnect-cells = <2>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + }; >> + >> + sdhc_2: mmc@8804000 { >> + compatible = "qcom,sm8650-sdhci", "qcom,sdhci-msm-v5"; >> + reg = <0 0x08804000 0 0x1000>; >> + >> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "hc_irq", >> + "pwr_irq"; >> + >> + clocks = <&gcc GCC_SDCC2_AHB_CLK>, >> + <&gcc GCC_SDCC2_APPS_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", >> + "core", >> + "xo"; >> + >> + interconnects = <&aggre2_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "sdhc-ddr", >> + "cpu-sdhc"; >> + >> + power-domains = <&rpmhpd RPMHPD_CX>; >> + operating-points-v2 = <&sdhc2_opp_table>; >> + >> + iommus = <&apps_smmu 0x540 0>; >> + >> + bus-width = <4>; >> + >> + /* Forbid SDR104/SDR50 - broken hw! */ >> + sdhci-caps-mask = <0x3 0>; >> + >> + qcom,dll-config = <0x0007642c>; >> + qcom,ddr-config = <0x80040868>; >> + >> + dma-coherent; >> + >> + status = "disabled"; >> + >> + sdhc2_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-19200000 { >> + opp-hz = /bits/ 64 <19200000>; >> + required-opps = <&rpmhpd_opp_min_svs>; >> + }; >> + >> + opp-50000000 { >> + opp-hz = /bits/ 64 <50000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-100000000 { >> + opp-hz = /bits/ 64 <100000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-202000000 { >> + opp-hz = /bits/ 64 <202000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + }; >> + }; >> + >> + mdss: display-subsystem@ae00000 { >> + compatible = "qcom,sm8650-mdss"; >> + reg = <0 0x0ae00000 0 0x1000>; >> + reg-names = "mdss"; >> + >> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_CLK>; >> + >> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; >> + >> + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS >> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>, >> + <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "mdp0-mem", >> + "mdp1-mem"; >> + >> + power-domains = <&dispcc MDSS_GDSC>; >> + >> + iommus = <&apps_smmu 0x1c00 0x2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + status = "disabled"; >> + >> + mdss_mdp: display-controller@ae01000 { >> + compatible = "qcom,sm8650-dpu"; >> + reg = <0 0x0ae01000 0 0x8f000>, >> + <0 0x0aeb0000 0 0x2008>; >> + reg-names = "mdp", >> + "vbif"; >> + >> + interrupts-extended = <&mdss 0>; >> + >> + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + clock-names = "nrt_bus", >> + "iface", >> + "lut", >> + "core", >> + "vsync"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + assigned-clock-rates = <19200000>; >> + >> + operating-points-v2 = <&mdp_opp_table>; >> + >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + dpu_intf1_out: endpoint { >> + remote-endpoint = <&mdss_dsi0_in>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + dpu_intf2_out: endpoint { >> + remote-endpoint = <&mdss_dsi1_in>; >> + }; >> + }; >> + }; >> + >> + mdp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-200000000 { >> + opp-hz = /bits/ 64 <200000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-325000000 { >> + opp-hz = /bits/ 64 <325000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-375000000 { >> + opp-hz = /bits/ 64 <375000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-514000000 { >> + opp-hz = /bits/ 64 <514000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + }; >> + >> + mdss_dsi0: dsi@ae94000 { >> + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; >> + reg = <0 0x0ae94000 0 0x400>; >> + reg-names = "dsi_ctrl"; >> + >> + interrupts-extended = <&mdss 4>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, >> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, >> + <&dispcc DISP_CC_MDSS_ESC0_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>; >> + clock-names = "byte", >> + "byte_intf", >> + "pixel", >> + "core", >> + "iface", >> + "bus"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; >> + assigned-clock-parents = <&mdss_dsi0_phy 0>, >> + <&mdss_dsi0_phy 1>; >> + >> + operating-points-v2 = <&mdss_dsi_opp_table>; >> + >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + phys = <&mdss_dsi0_phy>; >> + phy-names = "dsi"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + mdss_dsi0_in: endpoint { >> + remote-endpoint = <&dpu_intf1_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + mdss_dsi0_out: endpoint { >> + }; >> + }; >> + }; >> + >> + mdss_dsi_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-187500000 { >> + opp-hz = /bits/ 64 <187500000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-300000000 { >> + opp-hz = /bits/ 64 <300000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-358000000 { >> + opp-hz = /bits/ 64 <358000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + }; >> + }; >> + >> + mdss_dsi0_phy: phy@ae95000 { >> + compatible = "qcom,sm8650-dsi-phy-4nm"; >> + reg = <0 0x0ae95000 0 0x200>, >> + <0 0x0ae95200 0 0x280>, >> + <0 0x0ae95500 0 0x400>; >> + reg-names = "dsi_phy", >> + "dsi_phy_lane", >> + "dsi_pll"; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", >> + "ref"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + mdss_dsi1: dsi@ae96000 { >> + compatible = "qcom,sm8650-dsi-ctrl", "qcom,mdss-dsi-ctrl"; >> + reg = <0 0x0ae96000 0 0x400>; >> + reg-names = "dsi_ctrl"; >> + >> + interrupts-extended = <&mdss 5>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, >> + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, >> + <&dispcc DISP_CC_MDSS_ESC1_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>; >> + clock-names = "byte", >> + "byte_intf", >> + "pixel", >> + "core", >> + "iface", >> + "bus"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, >> + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; >> + assigned-clock-parents = <&mdss_dsi1_phy 0>, >> + <&mdss_dsi1_phy 1>; >> + >> + operating-points-v2 = <&mdss_dsi_opp_table>; >> + >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + >> + phys = <&mdss_dsi1_phy>; >> + phy-names = "dsi"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + >> + mdss_dsi1_in: endpoint { >> + remote-endpoint = <&dpu_intf2_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + >> + mdss_dsi1_out: endpoint { >> + }; >> + }; >> + }; >> + }; >> + >> + mdss_dsi1_phy: phy@ae97000 { >> + compatible = "qcom,sm8650-dsi-phy-4nm"; >> + reg = <0 0x0ae97000 0 0x200>, >> + <0 0x0ae97200 0 0x280>, >> + <0 0x0ae97500 0 0x400>; >> + reg-names = "dsi_phy", >> + "dsi_phy_lane", >> + "dsi_pll"; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", >> + "ref"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + }; >> + >> + dispcc: clock-controller@af00000 { >> + compatible = "qcom,sm8650-dispcc"; >> + reg = <0 0x0af00000 0 0x20000>; >> + >> + clocks = <&bi_tcxo_div2>, >> + <&bi_tcxo_ao_div2>, >> + <&gcc GCC_DISP_AHB_CLK>, >> + <&sleep_clk>, >> + <&mdss_dsi0_phy 0>, >> + <&mdss_dsi0_phy 1>, >> + <&mdss_dsi1_phy 0>, >> + <&mdss_dsi1_phy 1>, >> + <0>, /* dp0 */ >> + <0>, >> + <0>, /* dp1 */ >> + <0>, >> + <0>, /* dp2 */ >> + <0>, >> + <0>, /* dp3 */ >> + <0>; >> + >> + power-domains = <&rpmhpd RPMHPD_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + >> + status = "disabled"; >> + }; >> + >> + usb_1_hsphy: phy@88e3000 { >> + compatible = "qcom,sm8650-snps-eusb2-phy", >> + "qcom,sm8550-snps-eusb2-phy"; >> + reg = <0 0x088e3000 0 0x154>; >> + >> + clocks = <&tcsr TCSR_USB2_CLKREF_EN>; >> + clock-names = "ref"; >> + >> + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; >> + >> + #phy-cells = <0>; >> + >> + status = "disabled"; >> + }; >> + >> + usb_dp_qmpphy: phy@88e8000 { >> + compatible = "qcom,sm8650-qmp-usb3-dp-phy"; >> + reg = <0 0x088e8000 0 0x3000>; >> + >> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>, >> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, >> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; >> + clock-names = "aux", >> + "ref", >> + "com_aux", >> + "usb3_pipe"; >> + >> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, >> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; >> + reset-names = "phy", >> + "common"; >> + >> + power-domains = <&gcc USB3_PHY_GDSC>; >> + >> + #clock-cells = <1>; >> + #phy-cells = <1>; >> + >> + status = "disabled"; >> + }; >> + >> + usb_1: usb@a6f8800 { >> + compatible = "qcom,sm8650-dwc3", "qcom,dwc3"; >> + reg = <0 0x0a6f8800 0 0x400>; >> + >> + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, >> + <&pdc 15 IRQ_TYPE_EDGE_RISING>, >> + <&pdc 14 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "hs_phy_irq", >> + "ss_phy_irq", >> + "dm_hs_phy_irq", >> + "dp_hs_phy_irq"; >> + >> + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>, >> + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, >> + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, >> + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&tcsr TCSR_USB3_CLKREF_EN>; >> + clock-names = "cfg_noc", >> + "core", >> + "iface", >> + "sleep", >> + "mock_utmi", >> + "xo"; >> + >> + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, >> + <&gcc GCC_USB30_PRIM_MASTER_CLK>; >> + assigned-clock-rates = <19200000>, <200000000>; >> + >> + resets = <&gcc GCC_USB30_PRIM_BCR>; >> + >> + power-domains = <&gcc USB30_PRIM_GDSC>; >> + required-opps = <&rpmhpd_opp_nom>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; >> + >> + status = "disabled"; >> + >> + usb_1_dwc3: usb@a600000 { >> + compatible = "snps,dwc3"; >> + reg = <0 0x0a600000 0 0xcd00>; >> + >> + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; >> + >> + iommus = <&apps_smmu 0x40 0>; >> + >> + phys = <&usb_1_hsphy>, >> + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; >> + phy-names = "usb2-phy", >> + "usb3-phy"; >> + >> + snps,hird-threshold = /bits/ 8 <0x0>; >> + snps,usb2-gadget-lpm-disable; >> + snps,dis_u2_susphy_quirk; >> + snps,dis_enblslpm_quirk; >> + snps,dis-u1-entry-quirk; >> + snps,dis-u2-entry-quirk; >> + snps,is-utmi-l1-suspend; >> + snps,usb3_lpm_capable; >> + snps,usb2-lpm-disable; >> + snps,has-lpm-erratum; >> + tx-fifo-resize; >> + >> + dma-coherent; >> + >> + ports { >> + #address-cells = <1>; >> #size-cells = <0>; >> >> port@0 { >> @@ -969,115 +3155,602 @@ pdc: interrupt-controller@b220000 { >> <125 63 1>, <126 716 12>, >> <138 251 5>, <143 244 4>; >> >> - #interrupt-cells = <2>; >> - interrupt-controller; >> - }; >> + #interrupt-cells = <2>; >> + interrupt-controller; >> + }; >> + >> + tsens0: thermal-sensor@c228000 { >> + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; >> + reg = <0 0x0c228000 0 0x1000>, /* TM */ >> + <0 0x0c222000 0 0x1000>; /* SROT */ >> + >> + interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "uplow", >> + "critical"; >> + >> + #qcom,sensors = <15>; >> + >> + #thermal-sensor-cells = <1>; >> + }; >> + >> + tsens1: thermal-sensor@c229000 { >> + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; >> + reg = <0 0x0c229000 0 0x1000>, /* TM */ >> + <0 0x0c223000 0 0x1000>; /* SROT */ >> + >> + interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "uplow", >> + "critical"; >> + >> + #qcom,sensors = <16>; >> + >> + #thermal-sensor-cells = <1>; >> + }; >> + >> + tsens2: thermal-sensor@c22a000 { >> + compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; >> + reg = <0 0x0c22a000 0 0x1000>, /* TM */ >> + <0 0x0c224000 0 0x1000>; /* SROT */ >> + >> + interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, >> + <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "uplow", >> + "critical"; >> + >> + #qcom,sensors = <13>; >> + >> + #thermal-sensor-cells = <1>; >> + }; >> + >> + aoss_qmp: power-management@c300000 { >> + compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; >> + reg = <0 0x0c300000 0 0x400>; >> + >> + interrupt-parent = <&ipcc>; >> + interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP >> + IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; >> + >> + #clock-cells = <0>; >> + }; >> + >> + sram@c3f0000 { >> + compatible = "qcom,rpmh-stats"; >> + reg = <0 0x0c3f0000 0 0x400>; >> + }; >> + >> + spmi_bus: spmi@c400000 { >> + compatible = "qcom,spmi-pmic-arb"; >> + reg = <0 0x0c400000 0 0x3000>, >> + <0 0x0c500000 0 0x4000000>, >> + <0 0x0c440000 0 0x80000>, >> + <0 0x0c4c0000 0 0x20000>, >> + <0 0x0c42d000 0 0x4000>; >> + reg-names = "core", >> + "chnls", >> + "obsrvr", >> + "intr", >> + "cnfg"; >> + >> + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-names = "periph_irq"; >> + >> + qcom,ee = <0>; >> + qcom,channel = <0>; >> + qcom,bus-id = <0>; >> + >> + interrupt-controller; >> + #interrupt-cells = <4>; >> + >> + #address-cells = <2>; >> + #size-cells = <0>; >> + }; >> + >> + tlmm: pinctrl@f100000 { >> + compatible = "qcom,sm8650-tlmm"; >> + reg = <0 0x0f100000 0 0x300000>; >> + >> + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + >> + gpio-controller; >> + #gpio-cells = <2>; >> + >> + interrupt-controller; >> + #interrupt-cells = <2>; >> + >> + gpio-ranges = <&tlmm 0 0 211>; >> + >> + wakeup-parent = <&pdc>; >> + >> + hub_i2c0_data_clk: hub-i2c0-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio64", "gpio65"; >> + function = "i2chub0_se0"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c1_data_clk: hub-i2c1-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio66", "gpio67"; >> + function = "i2chub0_se1"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c2_data_clk: hub-i2c2-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio68", "gpio69"; >> + function = "i2chub0_se2"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c3_data_clk: hub-i2c3-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio70", "gpio71"; >> + function = "i2chub0_se3"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c4_data_clk: hub-i2c4-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio72", "gpio73"; >> + function = "i2chub0_se4"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c5_data_clk: hub-i2c5-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio74", "gpio75"; >> + function = "i2chub0_se5"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c6_data_clk: hub-i2c6-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio76", "gpio77"; >> + function = "i2chub0_se6"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c7_data_clk: hub-i2c7-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio78", "gpio79"; >> + function = "i2chub0_se7"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c8_data_clk: hub-i2c8-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio206", "gpio207"; >> + function = "i2chub0_se8"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + hub_i2c9_data_clk: hub-i2c9-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio80", "gpio81"; >> + function = "i2chub0_se9"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + pcie0_default_state: pcie0-default-state { >> + perst-pins { >> + pins = "gpio94"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> + >> + clkreq-pins { >> + pins = "gpio95"; >> + function = "pcie0_clk_req_n"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + wake-pins { >> + pins = "gpio96"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + }; >> + >> + pcie1_default_state: pcie1-default-state { >> + perst-pins { >> + pins = "gpio97"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> + >> + clkreq-pins { >> + pins = "gpio98"; >> + function = "pcie1_clk_req_n"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + wake-pins { >> + pins = "gpio99"; >> + function = "gpio"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + }; >> + >> + qup_i2c0_data_clk: qup-i2c0-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio32", "gpio33"; >> + function = "qup1_se0"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c1_data_clk: qup-i2c1-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio36", "gpio37"; >> + function = "qup1_se1"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c2_data_clk: qup-i2c2-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio40", "gpio41"; >> + function = "qup1_se2"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c3_data_clk: qup-i2c3-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio44", "gpio45"; >> + function = "qup1_se3"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c4_data_clk: qup-i2c4-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio48", "gpio49"; >> + function = "qup1_se4"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c5_data_clk: qup-i2c5-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio52", "gpio53"; >> + function = "qup1_se5"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c6_data_clk: qup-i2c6-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio56", "gpio57"; >> + function = "qup1_se6"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c7_data_clk: qup-i2c7-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio60", "gpio61"; >> + function = "qup1_se7"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c8_data_clk: qup-i2c8-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio0", "gpio1"; >> + function = "qup2_se0"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c9_data_clk: qup-i2c9-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio4", "gpio5"; >> + function = "qup2_se1"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c10_data_clk: qup-i2c10-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio8", "gpio9"; >> + function = "qup2_se2"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c11_data_clk: qup-i2c11-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio12", "gpio13"; >> + function = "qup2_se3"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c12_data_clk: qup-i2c12-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio16", "gpio17"; >> + function = "qup2_se4"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c13_data_clk: qup-i2c13-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio20", "gpio21"; >> + function = "qup2_se5"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_i2c14_data_clk: qup-i2c14-data-clk-state { >> + /* SDA, SCL */ >> + pins = "gpio24", "gpio25"; >> + function = "qup2_se6"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + qup_spi0_cs: qup-spi0-cs-state { >> + pins = "gpio35"; >> + function = "qup1_se0"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi0_data_clk: qup-spi0-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio32", "gpio33", "gpio34"; >> + function = "qup1_se0"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi1_cs: qup-spi1-cs-state { >> + pins = "gpio39"; >> + function = "qup1_se1"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> + >> + qup_spi1_data_clk: qup-spi1-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio36", "gpio37", "gpio38"; >> + function = "qup1_se1"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - tsens0: thermal-sensor@c228000 { >> - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; >> - reg = <0 0x0c228000 0 0x1000>, /* TM */ >> - <0 0x0c222000 0 0x1000>; /* SROT */ >> + qup_spi2_cs: qup-spi2-cs-state { >> + pins = "gpio43"; >> + function = "qup1_se2"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH>; >> - interrupt-names = "uplow", >> - "critical"; >> + qup_spi2_data_clk: qup-spi2-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio40", "gpio41", "gpio42"; >> + function = "qup1_se2"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #qcom,sensors = <15>; >> + qup_spi3_cs: qup-spi3-cs-state { >> + pins = "gpio47"; >> + function = "qup1_se3"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #thermal-sensor-cells = <1>; >> - }; >> + qup_spi3_data_clk: qup-spi3-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio44", "gpio45", "gpio46"; >> + function = "qup1_se3"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - tsens1: thermal-sensor@c229000 { >> - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; >> - reg = <0 0x0c229000 0 0x1000>, /* TM */ >> - <0 0x0c223000 0 0x1000>; /* SROT */ >> + qup_spi4_cs: qup-spi4-cs-state { >> + pins = "gpio51"; >> + function = "qup1_se4"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>; >> - interrupt-names = "uplow", >> - "critical"; >> + qup_spi4_data_clk: qup-spi4-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio48", "gpio49", "gpio50"; >> + function = "qup1_se4"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #qcom,sensors = <16>; >> + qup_spi5_cs: qup-spi5-cs-state { >> + pins = "gpio55"; >> + function = "qup1_se5"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #thermal-sensor-cells = <1>; >> - }; >> + qup_spi5_data_clk: qup-spi5-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio52", "gpio53", "gpio54"; >> + function = "qup1_se5"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - tsens2: thermal-sensor@c22a000 { >> - compatible = "qcom,sm8650-tsens", "qcom,tsens-v2"; >> - reg = <0 0x0c22a000 0 0x1000>, /* TM */ >> - <0 0x0c224000 0 0x1000>; /* SROT */ >> + qup_spi6_cs: qup-spi6-cs-state { >> + pins = "gpio59"; >> + function = "qup1_se6"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, >> - <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>; >> - interrupt-names = "uplow", >> - "critical"; >> + qup_spi6_data_clk: qup-spi6-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio56", "gpio57", "gpio58"; >> + function = "qup1_se6"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #qcom,sensors = <13>; >> + qup_spi7_cs: qup-spi7-cs-state { >> + pins = "gpio63"; >> + function = "qup1_se7"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #thermal-sensor-cells = <1>; >> - }; >> + qup_spi7_data_clk: qup-spi7-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio60", "gpio61", "gpio62"; >> + function = "qup1_se7"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - aoss_qmp: power-management@c300000 { >> - compatible = "qcom,sm8650-aoss-qmp", "qcom,aoss-qmp"; >> - reg = <0 0x0c300000 0 0x400>; >> + qup_spi8_cs: qup-spi8-cs-state { >> + pins = "gpio3"; >> + function = "qup2_se0"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupt-parent = <&ipcc>; >> - interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP >> - IRQ_TYPE_EDGE_RISING>; >> + qup_spi8_data_clk: qup-spi8-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio0", "gpio1", "gpio2"; >> + function = "qup2_se0"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>; >> + qup_spi9_cs: qup-spi9-cs-state { >> + pins = "gpio7"; >> + function = "qup2_se1"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #clock-cells = <0>; >> - }; >> + qup_spi9_data_clk: qup-spi9-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio4", "gpio5", "gpio6"; >> + function = "qup2_se1"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - sram@c3f0000 { >> - compatible = "qcom,rpmh-stats"; >> - reg = <0 0x0c3f0000 0 0x400>; >> - }; >> + qup_spi10_cs: qup-spi10-cs-state { >> + pins = "gpio11"; >> + function = "qup2_se2"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - spmi_bus: spmi@c400000 { >> - compatible = "qcom,spmi-pmic-arb"; >> - reg = <0 0x0c400000 0 0x3000>, >> - <0 0x0c500000 0 0x4000000>, >> - <0 0x0c440000 0 0x80000>, >> - <0 0x0c4c0000 0 0x20000>, >> - <0 0x0c42d000 0 0x4000>; >> - reg-names = "core", >> - "chnls", >> - "obsrvr", >> - "intr", >> - "cnfg"; >> + qup_spi10_data_clk: qup-spi10-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio8", "gpio9", "gpio10"; >> + function = "qup2_se2"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; >> - interrupt-names = "periph_irq"; >> + qup_spi11_cs: qup-spi11-cs-state { >> + pins = "gpio15"; >> + function = "qup2_se3"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - qcom,ee = <0>; >> - qcom,channel = <0>; >> - qcom,bus-id = <0>; >> + qup_spi11_data_clk: qup-spi11-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio12", "gpio13", "gpio14"; >> + function = "qup2_se3"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupt-controller; >> - #interrupt-cells = <4>; >> + qup_spi12_cs: qup-spi12-cs-state { >> + pins = "gpio19"; >> + function = "qup2_se4"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - #address-cells = <2>; >> - #size-cells = <0>; >> - }; >> + qup_spi12_data_clk: qup-spi12-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio16", "gpio17", "gpio18"; >> + function = "qup2_se4"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - tlmm: pinctrl@f100000 { >> - compatible = "qcom,sm8650-tlmm"; >> - reg = <0 0x0f100000 0 0x300000>; >> + qup_spi13_cs: qup-spi13-cs-state { >> + pins = "gpio23"; >> + function = "qup2_se5"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; >> + qup_spi13_data_clk: qup-spi13-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio20", "gpio21", "gpio22"; >> + function = "qup2_se5"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - gpio-controller; >> - #gpio-cells = <2>; >> + qup_spi14_cs: qup-spi14-cs-state { >> + pins = "gpio27"; >> + function = "qup2_se6"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - interrupt-controller; >> - #interrupt-cells = <2>; >> + qup_spi14_data_clk: qup-spi14-data-clk-state { >> + /* MISO, MOSI, CLK */ >> + pins = "gpio24", "gpio25", "gpio26"; >> + function = "qup2_se6"; >> + drive-strength = <6>; >> + bias-disable; >> + }; >> >> - gpio-ranges = <&tlmm 0 0 211>; >> + qup_uart14_default: qup-uart14-default-state { >> + /* TX, RX */ >> + pins = "gpio26", "gpio27"; >> + function = "qup2_se6"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> >> - wakeup-parent = <&pdc>; >> + qup_uart14_cts_rts: qup-uart14-cts-rts-state { >> + /* CTS, RTS */ >> + pins = "gpio24", "gpio25"; >> + function = "qup2_se6"; >> + drive-strength = <2>; >> + bias-pull-down; >> + }; >> >> qup_uart15_default: qup-uart15-default-state { >> /* TX, RX */ >> @@ -1086,6 +3759,46 @@ qup_uart15_default: qup-uart15-default-state { >> drive-strength = <2>; >> bias-disable; >> }; >> + >> + sdc2_sleep: sdc2-sleep-state { >> + clk-pins { >> + pins = "sdc2_clk"; >> + drive-strength = <2>; >> + bias-disable; >> + }; >> + >> + cmd-pins { >> + pins = "sdc2_cmd"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + >> + data-pins { >> + pins = "sdc2_data"; >> + drive-strength = <2>; >> + bias-pull-up; >> + }; >> + }; >> + >> + sdc2_default: sdc2-default-state { >> + clk-pins { >> + pins = "sdc2_clk"; >> + drive-strength = <16>; >> + bias-disable; >> + }; >> + >> + cmd-pins { >> + pins = "sdc2_cmd"; >> + drive-strength = <10>; >> + bias-pull-up; >> + }; >> + >> + data-pins { >> + pins = "sdc2_data"; >> + drive-strength = <10>; >> + bias-pull-up; >> + }; >> + }; >> }; >> >> apps_smmu: iommu@15000000 { >> @@ -1437,6 +4150,107 @@ cpufreq_hw: cpufreq@17d91000 { >> #clock-cells = <1>; >> }; >> >> + pmu@24091000 { >> + compatible = "qcom,sm8650-llcc-bwmon", "qcom,sc7280-llcc-bwmon"; >> + reg = <0 0x24091000 0 0x1000>; >> + >> + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; >> + >> + interconnects = <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ACTIVE_ONLY >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; >> + >> + operating-points-v2 = <&llcc_bwmon_opp_table>; >> + >> + llcc_bwmon_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-0 { >> + opp-peak-kBps = <2086000>; >> + }; >> + >> + opp-1 { >> + opp-peak-kBps = <2929000>; >> + }; >> + >> + opp-2 { >> + opp-peak-kBps = <5931000>; >> + }; >> + >> + opp-3 { >> + opp-peak-kBps = <6515000>; >> + }; >> + >> + opp-4 { >> + opp-peak-kBps = <7980000>; >> + }; >> + >> + opp-5 { >> + opp-peak-kBps = <10437000>; >> + }; >> + >> + opp-6 { >> + opp-peak-kBps = <12157000>; >> + }; >> + >> + opp-7 { >> + opp-peak-kBps = <14060000>; >> + }; >> + >> + opp-8 { >> + opp-peak-kBps = <16113000>; >> + }; >> + }; >> + }; >> + >> + pmu@240b7400 { >> + compatible = "qcom,sm8650-cpu-bwmon", "qcom,sdm845-bwmon"; >> + reg = <0 0x240b7400 0 0x600>; >> + >> + interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; >> + >> + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY >> + &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ACTIVE_ONLY>; >> + >> + operating-points-v2 = <&cpu_bwmon_opp_table>; >> + >> + cpu_bwmon_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-0 { >> + opp-peak-kBps = <4577000>; >> + }; >> + >> + opp-1 { >> + opp-peak-kBps = <7110000>; >> + }; >> + >> + opp-2 { >> + opp-peak-kBps = <9155000>; >> + }; >> + >> + opp-3 { >> + opp-peak-kBps = <12298000>; >> + }; >> + >> + opp-4 { >> + opp-peak-kBps = <14236000>; >> + }; >> + >> + opp-5 { >> + opp-peak-kBps = <16265000>; >> + }; >> + }; >> + }; >> + >> + gem_noc: interconnect@24100000 { >> + compatible = "qcom,sm8650-gem-noc"; >> + reg = <0 0x24100000 0 0xc5080>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> system-cache-controller@25000000 { >> compatible = "qcom,sm8650-llcc"; >> reg = <0 0x25000000 0 0x200000>, >> @@ -1452,6 +4266,137 @@ system-cache-controller@25000000 { >> >> interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; >> }; >> + >> + remoteproc_adsp: remoteproc@30000000 { >> + compatible = "qcom,sm8650-adsp-pas"; >> + reg = <0 0x30000000 0 0x100>; >> + >> + interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "wdog", >> + "fatal", >> + "ready", >> + "handover", >> + "stop-ack"; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "xo"; >> + >> + interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + >> + power-domains = <&rpmhpd RPMHPD_LCX>, >> + <&rpmhpd RPMHPD_LMX>; >> + power-domain-names = "lcx", >> + "lmx"; >> + >> + memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; >> + >> + qcom,qmp = <&aoss_qmp>; >> + >> + qcom,smem-states = <&smp2p_adsp_out 0>; >> + qcom,smem-state-names = "stop"; >> + >> + status = "disabled"; >> + >> + remoteproc_adsp_glink: glink-edge { >> + interrupts-extended = <&ipcc IPCC_CLIENT_LPASS >> + IPCC_MPROC_SIGNAL_GLINK_QMP >> + IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&ipcc IPCC_CLIENT_LPASS >> + IPCC_MPROC_SIGNAL_GLINK_QMP>; >> + >> + qcom,remote-pid = <2>; >> + >> + label = "lpass"; >> + >> + fastrpc { >> + compatible = "qcom,fastrpc"; >> + >> + qcom,glink-channels = "fastrpcglink-apps-dsp"; >> + >> + label = "adsp"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + }; >> + >> + nsp_noc: interconnect@320c0000 { >> + compatible = "qcom,sm8650-nsp-noc"; >> + reg = <0 0x320c0000 0 0xf080>; >> + >> + qcom,bcm-voters = <&apps_bcm_voter>; >> + >> + #interconnect-cells = <2>; >> + }; >> + >> + remoteproc_cdsp: remoteproc@32300000 { >> + compatible = "qcom,sm8650-cdsp-pas"; >> + reg = <0 0x32300000 0 0x1400000>; >> + >> + interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, >> + <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>; >> + interrupt-names = "wdog", >> + "fatal", >> + "ready", >> + "handover", >> + "stop-ack"; >> + >> + clocks = <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "xo"; >> + >> + interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS >> + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; >> + >> + power-domains = <&rpmhpd RPMHPD_CX>, >> + <&rpmhpd RPMHPD_MXC>, >> + <&rpmhpd RPMHPD_NSP>; >> + power-domain-names = "cx", >> + "mxc", >> + "nsp"; >> + >> + memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>, <&global_sync_mem>; >> + >> + qcom,qmp = <&aoss_qmp>; >> + >> + qcom,smem-states = <&smp2p_cdsp_out 0>; >> + qcom,smem-state-names = "stop"; >> + >> + status = "disabled"; >> + >> + glink-edge { >> + interrupts-extended = <&ipcc IPCC_CLIENT_CDSP >> + IPCC_MPROC_SIGNAL_GLINK_QMP >> + IRQ_TYPE_EDGE_RISING>; >> + >> + mboxes = <&ipcc IPCC_CLIENT_CDSP >> + IPCC_MPROC_SIGNAL_GLINK_QMP>; >> + >> + qcom,remote-pid = <5>; >> + >> + label = "cdsp"; >> + >> + fastrpc { >> + compatible = "qcom,fastrpc"; >> + >> + qcom,glink-channels = "fastrpcglink-apps-dsp"; >> + >> + label = "cdsp"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + }; >> + }; >> + }; >> }; >> >> thermal-zones { >> >> -- >> 2.34.1 >> >> > > ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 7/8] arm64: dts: qcom: sm8650-mtp: add interconnect dependent device nodes 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong ` (5 preceding siblings ...) 2023-11-21 11:00 ` [PATCH v3 6/8] arm64: dts: qcom: sm8650: add interconnect dependent device nodes Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 2023-11-22 19:41 ` Konrad Dybcio 2023-11-21 11:00 ` [PATCH v3 8/8] arm64: dts: qcom: sm8650-qrd: " Neil Armstrong 7 siblings, 1 reply; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 MTP board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650-mtp.dts | 235 +++++++++++++++++++++++++++++++- 1 file changed, 234 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts index 5738791fea2a..83412d4914b9 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-mtp.dts @@ -28,6 +28,44 @@ chosen { stdout-path = "serial0:115200n8"; }; + pmic-glink { + compatible = "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -77,6 +115,9 @@ vreg_l2b_3p0: ldo2 { regulator-min-microvolt = <3008000>; regulator-max-microvolt = <3008000>; regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>; + regulator-allow-set-load; + regulator-allowed-modes = <RPMH_REGULATOR_MODE_LPM + RPMH_REGULATOR_MODE_HPM>; }; vreg_l5b_3p1: ldo5 { @@ -389,6 +430,106 @@ vreg_l3i_1p2: ldo3 { }; }; +&dispcc { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3i_1p2>; + + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + pinctrl-0 = <&disp0_resetn_active>, <&mdp_vsync_active>; + pinctrl-1 = <&disp0_resetn_suspend>, <&mdp_vsync_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1i_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + +&pcie1 { + wake-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 97 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie1_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie1_phy { + vdda-phy-supply = <&vreg_l3e_0p9>; + vdda-pll-supply = <&vreg_l3i_1p2>; + vdda-qref-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&pm8550_gpios { + sdc2_card_det_n: sdc2-card-det-state { + pins = "gpio12"; + function = "normal"; + bias-pull-up; + input-enable; + output-disable; + power-source = <1>; /* 1.8 V */ + }; +}; + &pm8550b_eusb2_repeater { vdd18-supply = <&vreg_l15b_1p8>; vdd3-supply = <&vreg_l5b_3p1>; @@ -398,18 +539,101 @@ &qupv3_id_1 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/sm8650/adsp.mbn", + "qcom/sm8650/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8650/cdsp.mbn", + "qcom/sm8650/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8650/modem.mbn", + "qcom/sm8650/modem_dtb.mbn"; + + status = "okay"; +}; + +&sdhc_2 { + cd-gpios = <&pm8550_gpios 12 GPIO_ACTIVE_LOW>; + + vmmc-supply = <&vreg_l9b_2p9>; + vqmmc-supply = <&vreg_l8b_1p8>; + bus-width = <4>; + no-sdio; + no-mmc; + + pinctrl-0 = <&sdc2_default>, <&sdc2_card_det_n>; + pinctrl-1 = <&sdc2_sleep>, <&sdc2_card_det_n>; + pinctrl-names = "default", "sleep"; + + status = "okay"; +}; + &sleep_clk { clock-frequency = <32000>; }; &tlmm { gpio-reserved-ranges = <32 8>; + + disp0_resetn_active: disp0-resetn-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_resetn_suspend: disp0-resetn-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync_active: mdp-vsync-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync_suspend: mdp-vsync-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart15 { status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1c_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + /* * DPAUX -> WCD9395 -> USB_SBU -> USB-C * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> USB-C @@ -421,7 +645,16 @@ &usb_1 { }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH v3 7/8] arm64: dts: qcom: sm8650-mtp: add interconnect dependent device nodes 2023-11-21 11:00 ` [PATCH v3 7/8] arm64: dts: qcom: sm8650-mtp: " Neil Armstrong @ 2023-11-22 19:41 ` Konrad Dybcio 0 siblings, 0 replies; 15+ messages in thread From: Konrad Dybcio @ 2023-11-22 19:41 UTC (permalink / raw) To: Neil Armstrong, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel On 11/21/23 12:00, Neil Armstrong wrote: > Now interconnect dependent devices are added in sm8650 DTSI, > now enable more devices for the Qualcomm SM8650 MTP board: > - PCIe > - Display > - DSPs > - SDCard > - UFS > - USB role switch with PMIC Glink > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- [...] If you're going to resend: > &tlmm { > gpio-reserved-ranges = <32 8>; Forgot to ask.. would it be possible to add a comment with what these pins are for? e.g. gpio-reserved-ranges = <32 8>; /* printer serial conenction */ > + > + disp0_resetn_active: disp0-resetn-active-state { ..-reset-n-.. and I guess same for p8 Konrad ^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH v3 8/8] arm64: dts: qcom: sm8650-qrd: add interconnect dependent device nodes 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong ` (6 preceding siblings ...) 2023-11-21 11:00 ` [PATCH v3 7/8] arm64: dts: qcom: sm8650-mtp: " Neil Armstrong @ 2023-11-21 11:00 ` Neil Armstrong 7 siblings, 0 replies; 15+ messages in thread From: Neil Armstrong @ 2023-11-21 11:00 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Now interconnect dependent devices are added in sm8650 DTSI, now enable more devices for the Qualcomm SM8650 QRD board: - PCIe - Display - DSPs - SDCard - UFS - USB role switch with PMIC Glink - Bluetooth Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8650-qrd.dts | 275 +++++++++++++++++++++++++++++++- 1 file changed, 274 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts index f5ce4c889680..b41f90d817bb 100644 --- a/arch/arm64/boot/dts/qcom/sm8650-qrd.dts +++ b/arch/arm64/boot/dts/qcom/sm8650-qrd.dts @@ -23,6 +23,7 @@ / { aliases { serial0 = &uart15; + serial1 = &uart14; }; chosen { @@ -45,6 +46,44 @@ key-volume-up { }; }; + pmic-glink { + compatible = "qcom,sm8650-pmic-glink", + "qcom,sm8550-pmic-glink", + "qcom,pmic-glink"; + #address-cells = <1>; + #size-cells = <0>; + orientation-gpios = <&tlmm 29 GPIO_ACTIVE_HIGH>; + + connector@0 { + compatible = "usb-c-connector"; + reg = <0>; + + power-role = "dual"; + data-role = "dual"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + pmic_glink_hs_in: endpoint { + remote-endpoint = <&usb_1_dwc3_hs>; + }; + }; + + port@1 { + reg = <1>; + + pmic_glink_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; @@ -399,6 +438,81 @@ vreg_l3i_1p2: ldo3 { }; }; +&dispcc { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3i_1p2>; + + status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + pinctrl-0 = <&disp0_resetn_active>, <&mdp_vsync_active>; + pinctrl-1 = <&disp0_resetn_suspend>, <&mdp_vsync_suspend>; + pinctrl-names = "default", "sleep"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1i_0p88>; + + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + +&pcie_1_phy_aux_clk { + clock-frequency = <1000>; +}; + +&pcie0 { + wake-gpios = <&tlmm 96 GPIO_ACTIVE_HIGH>; + perst-gpios = <&tlmm 94 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&pcie0_default_state>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie0_phy { + vdda-phy-supply = <&vreg_l1i_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + &pon_pwrkey { status = "okay"; }; @@ -479,22 +593,172 @@ &pmk8550_rtc { status = "okay"; }; +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; +&remoteproc_adsp { + firmware-name = "qcom/sm8650/adsp.mbn", + "qcom/sm8650/adsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/sm8650/cdsp.mbn", + "qcom/sm8650/cdsp_dtb.mbn"; + + status = "okay"; +}; + +&remoteproc_mpss { + firmware-name = "qcom/sm8650/modem.mbn", + "qcom/sm8650/modem_dtb.mbn"; + + status = "okay"; +}; + &sleep_clk { clock-frequency = <32000>; }; +&spi4 { + status = "okay"; + + touchscreen@0 { + compatible = "goodix,gt9916"; + reg = <0>; + + interrupt-parent = <&tlmm>; + interrupts = <162 IRQ_TYPE_LEVEL_LOW>; + + reset-gpios = <&tlmm 161 GPIO_ACTIVE_LOW>; + + avdd-supply = <&vreg_l14b_3p2>; + + spi-max-frequency = <1000000>; + + touchscreen-size-x = <1080>; + touchscreen-size-y = <2400>; + + pinctrl-0 = <&ts_irq>, <&ts_reset>; + pinctrl-names = "default"; + }; +}; + &tlmm { gpio-reserved-ranges = <32 8>; + + bt_default: bt-default-state { + bt-en-pins { + pins = "gpio17"; + function = "gpio"; + drive-strength = <16>; + bias-disable; + }; + + sw-ctrl-pins { + pins = "gpio18"; + function = "gpio"; + bias-pull-down; + }; + }; + + disp0_resetn_active: disp0-resetn-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + disp0_resetn_suspend: disp0-resetn-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync_active: mdp-vsync-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + mdp_vsync_suspend: mdp-vsync-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + ts_irq: ts-irq-state { + pins = "gpio161"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + output-disable; + }; + + ts_reset: ts-reset-state { + pins = "gpio162"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; +}; + +&uart14 { + status = "okay"; + + bluetooth { + compatible = "qcom,wcn7850-bt"; + + clocks = <&rpmhcc RPMH_RF_CLK1>; + + vddio-supply = <&vreg_l3c_1p2>; + vddaon-supply = <&vreg_l15b_1p8>; + vdddig-supply = <&vreg_s3c_0p9>; + vddrfa0p8-supply = <&vreg_s3c_0p9>; + vddrfa1p2-supply = <&vreg_s1c_1p2>; + vddrfa1p9-supply = <&vreg_s6c_1p8>; + + max-speed = <3200000>; + + enable-gpios = <&tlmm 17 GPIO_ACTIVE_HIGH>; + swctrl-gpios = <&tlmm 18 GPIO_ACTIVE_HIGH>; + + pinctrl-0 = <&bt_default>; + pinctrl-names = "default"; + }; }; &uart15 { status = "okay"; }; +&ufs_mem_hc { + reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; + + vcc-supply = <&vreg_l17b_2p5>; + vcc-max-microamp = <1300000>; + vccq-supply = <&vreg_l1c_1p2>; + vccq-max-microamp = <1200000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l1d_0p88>; + vdda-pll-supply = <&vreg_l3i_1p2>; + + status = "okay"; +}; + /* * DPAUX -> WCD9395 -> USB_SBU -> USB-C * eUSB2 DP/DM -> PM85550HS -> eUSB2 DP/DM -> WCD9395 -> USB-C @@ -506,7 +770,16 @@ &usb_1 { }; &usb_1_dwc3 { - dr_mode = "peripheral"; + dr_mode = "otg"; + usb-role-switch; +}; + +&usb_1_dwc3_hs { + remote-endpoint = <&pmic_glink_hs_in>; +}; + +&usb_1_dwc3_ss { + remote-endpoint = <&pmic_glink_ss_in>; }; &usb_1_hsphy { -- 2.34.1 ^ permalink raw reply related [flat|nested] 15+ messages in thread
end of thread, other threads:[~2023-11-23 13:28 UTC | newest] Thread overview: 15+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-11-21 10:59 [PATCH v3 0/8] arm64: dts: qcom: Introduce SM8650 platforms device tree Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 1/8] dt-bindings: arm: qcom: document SM8650 and the reference boards Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 2/8] arm64: dts: qcom: add initial SM8650 dtsi Neil Armstrong 2023-11-22 8:07 ` Krishna Kurapati PSSNV 2023-11-23 13:28 ` Neil Armstrong 2023-11-22 16:36 ` Konrad Dybcio 2023-11-21 11:00 ` [PATCH v3 3/8] arm64: dts: qcom: pm8550ve: make PMK8550VE SID configurable Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 4/8] arm64: dts: qcom: sm8650: add initial SM8650 MTP dts Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 5/8] arm64: dts: qcom: sm8650: add initial SM8650 QRD dts Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 6/8] arm64: dts: qcom: sm8650: add interconnect dependent device nodes Neil Armstrong 2023-11-21 11:24 ` Dmitry Baryshkov 2023-11-21 13:40 ` Neil Armstrong 2023-11-21 11:00 ` [PATCH v3 7/8] arm64: dts: qcom: sm8650-mtp: " Neil Armstrong 2023-11-22 19:41 ` Konrad Dybcio 2023-11-21 11:00 ` [PATCH v3 8/8] arm64: dts: qcom: sm8650-qrd: " Neil Armstrong
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