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Mon, 16 Mar 2026 07:36:48 -0500 Received: from [172.24.233.20] (a0512632.dhcp.ti.com [172.24.233.20]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 62GCah1g1295891; Mon, 16 Mar 2026 07:36:44 -0500 Message-ID: <7b3660cf-cc5a-47d6-9cc8-362544cfdb37@ti.com> Date: Mon, 16 Mar 2026 18:06:42 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2] dt-bindings: display: ti,am65x-dss: Fix AM62L DSS reg and clock constraints From: Swamil Jain To: Krzysztof Kozlowski CC: , , , , , , , , , , , , , , , References: <20260129150601.185882-1-s-jain1@ti.com> <20260205-spectral-dramatic-jellyfish-cec4e2@quoll> <4b554339-95e1-4980-8899-57ba637ba80c@ti.com> Content-Language: en-US In-Reply-To: <4b554339-95e1-4980-8899-57ba637ba80c@ti.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM2PEPF00003FC4:EE_|SJ0PR10MB4624:EE_ X-MS-Office365-Filtering-Correlation-Id: aee34800-1d20-4377-c031-08de8358b842 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|7416014|376014|56012099003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: FBs2NYfL5GF9CQrSzwsI9/StG4GP6E6ygWOrTp9XvonjU9g8W+Xw6PrK5dLRPzBFVoy0s+sng2hrM6gz+PNpl3VqGpBUvLbEI/8y61H4cE/i1VANQhhpkQ5+Wn39LBCIpYmlNDj8IRVS3KDyWpCf4cSwCGnQSV4pEJP2dCdsNetPLAGNwRLUDMEH057/jUv6l2bClw3EElZ5Oz3jpGwrjl+yO5N/eCY7kHo0h4YRPh7IY9SKGA2HTSAzIyUDpfwgA30NpOmzcaXWMooC5IhYwSAMeKiaAthAztbcw9AunWNJzWOshA6HjOzMSl4qr7piaHkBR0L9/8tQKpTykXdFd7UKkxGGQ7SIFGUwXEP2ekejq8dNLxl/Qs0fjI9arMO855dw95oJCVWk+gNDBLkWi9R/oqJ9lFgkzsQBx015ISqMy3szxUQtKL5gxo3AzsUT X-OriginatorOrg: ti.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Mar 2026 12:37:00.4013 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: aee34800-1d20-4377-c031-08de8358b842 X-MS-Exchange-CrossTenant-Id: e5b49634-450b-4709-8abb-1e2b19b982b7 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=e5b49634-450b-4709-8abb-1e2b19b982b7;Ip=[198.47.21.194];Helo=[flwvzet200.ext.ti.com] X-MS-Exchange-CrossTenant-AuthSource: DM2PEPF00003FC4.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR10MB4624 On 2/6/26 19:48, Swamil Jain wrote: > Hi Krzysztof, > > On 2/5/26 18:55, Krzysztof Kozlowski wrote: >> On Thu, Jan 29, 2026 at 08:36:01PM +0530, Swamil Jain wrote: >>> The AM62L DSS [1] support incorrectly used the same register and >>> clock constraints as AM65x, but AM62L has a single video port. >>> >>> Fix this by adding conditional constraints that properly define the >>> register regions and clocks for AM62L DSS (single video port) versus >>> other AM65x variants (dual video port). >>> >>> [1]: Section 12.7 (Display Subsystem and Peripherals) >>> Link : https://www.ti.com/lit/pdf/sprujb4 >>> >>> Fixes: cb8d4323302c ("dt-bindings: display: ti,am65x-dss: Add support >>> for AM62L DSS") >>> Cc: stable@vger.kernel.org >>> >> >> There are never blank lines between tags. >> > > Sorry, will fix this. > >>> Signed-off-by: Swamil Jain >>> --- >>> Changelog: >>> v1->v2: >>> - Remove oneOf from top level constraints, it makes bindings redundant >>> - Remove minItems from top level constraints >>> - "dma-coherent" property shouldn't be changed in v1 itself >>> - Add description for reg-names, clock and clock-names >>> - Add constraints specific to AM62L and for other SoCs within allOf >>>    check >>> >>> Link to v1: >>> https://lore.kernel.org/all/20251224133150.2266524-1-s-jain1@ti.com/ >>> --- >>>   .../bindings/display/ti/ti,am65x-dss.yaml     | 93 +++++++++++++------ >>>   1 file changed, 67 insertions(+), 26 deletions(-) >>> >>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x- >>> dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x- >>> dss.yaml >>> index 38fcee91211e..dbc9d754cf9e 100644 >>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml >>> @@ -36,38 +36,18 @@ properties: >>>     reg: >>>       description: >>>         Addresses to each DSS memory region described in the SoC's TRM. >>> -    items: >>> -      - description: common DSS register area >>> -      - description: VIDL1 light video plane >>> -      - description: VID video plane >>> -      - description: OVR1 overlay manager for vp1 >>> -      - description: OVR2 overlay manager for vp2 >>> -      - description: VP1 video port 1 >>> -      - description: VP2 video port 2 >>> -      - description: common1 DSS register area >> >> No, I do not understand this change. We spoke so many times, documented >> it, wrotre on presentation slides: broadest constraints are always >> defined in top level. TI received this feedback more than once. >> > > There is no superset constraints since am62l register sequence (common, > vidl1, ovr1, vp1, common1) is different than non-am62l SoCs (common, > vidl1, vid, ...-> here it is different), so thought to adopt this > approach where there is if-else block for each SoC and ran this through > dt-bindings check as well, looking at the replies maybe I misunderstood > what the suggestion was, reading the reply as I understand below is the > suggestion: > > ``` > reg: >     description: >       Addresses to each DSS memory region described in the SoC's TRM. >     oneOf: >       - items: >           - description: common DSS register area >           - description: VIDL1 light video plane >           - description: VID video plane >           - description: OVR1 overlay manager for vp1 >           - description: OVR2 overlay manager for vp2 >           - description: VP1 video port 1 >           - description: VP2 video port 2 >           - description: common1 DSS register area >       - items: >           - description: common DSS register area >           - description: VIDL1 light video plane >           - description: OVR1 overlay manager for vp1 >           - description: VP1 video port 1 >           - description: common1 DSS register area > > .....(Similarly for reg-names, clocks, clock-names,...) > > allOf: >   - if: >       properties: >         compatible: >           contains: >             const: ti,am62l-dss >     then: >       properties: >         clock-names: >           maxItems: 2 >         clocks: >           maxItems: 2 >         reg: >           maxItems: 5 >     else: >       properties: >         clock-names: >           minItems: 3 >         clocks: >           minItems: 3 >         reg: >           minItems: 8 > > ``` > > Could you please confirm on this? Hi Krzysztof, Gentle ping, could you please confirm on the above design? Regards, Swamil. > > Regards, > Swamil. > > >> Sorry guys, but you are not individual contributors which do it in spare >> time. Why the same feedback - already documented - has to be repeated? >> >> Best regards, >> Krzysztof >> >> > >