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Mon, 21 Sep 2026 06:47:08 -0700 (PDT) X-Received: by 2002:a17:903:2f0f:b0:2d8:d4d0:7930 with SMTP id d9443c01a7336-2ddb1b98b90mr155543555ad.20.1789998428217; Mon, 21 Sep 2026 06:47:08 -0700 (PDT) Received: from [192.168.29.146] ([49.43.232.81]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ddc18032d5sm34621395ad.83.2026.09.21.06.47.02 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 21 Sep 2026 06:47:07 -0700 (PDT) Message-ID: <7b5bec8a-87ed-4363-ac62-3e14f7619f13@oss.qualcomm.com> Date: Mon, 21 Sep 2026 19:17:00 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 2/5] dt-bindings: PCI: qcom,shikra-pcie: Document the Shikra PCIe Controller To: Krzysztof Kozlowski Cc: Vinod Koul , Neil Armstrong , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Bjorn Andersson , Chaitanya Chundru , Bartosz Golaszewski , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org References: <20260831-shikra-upstream-v2-0-406661d75afa@oss.qualcomm.com> <20260831-shikra-upstream-v2-2-406661d75afa@oss.qualcomm.com> <20260901-silent-pearl-shrew-c63a16@quoll> Content-Language: en-US From: Sushrut Shree Trivedi In-Reply-To: <20260901-silent-pearl-shrew-c63a16@quoll> Content-Type: text/plain; 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IOW, why does this > need a separate file unlike Eliza? Shikra does not have the Config NoC AXI clock unlike sm8550 / eliza. Apart from that, minItems for reg  and interrupts need to be updated. I actually didn't see any bindings with a clock constraint added for only a single compatible. Do you suggest constraining shikra clock-names and other properties under an if block inside sm8550 binding itself ? > > ... > >> + reset-names = "pci"; >> + >> + power-domains = <&gcc GCC_PCIE_GDSC>; >> + >> + max-link-speed = <2>; >> + >> + operating-points-v2 = <&pcie_opp_table>; >> + >> + pcie_opp_table: opp-table { >> + compatible = "operating-points-v2"; > Are you sure dt-check-style does not complain? ACK'd > >> + >> + /* GEN 1 x1 */ >> + opp-2500000 { >> + opp-hz = /bits/ 64 <2500000>; >> + required-opps = <&rpmpd_opp_low_svs>; >> + opp-peak-kBps = <250000 1>; >> + opp-level = <1>; >> + }; >> + > Best regards, > Krzysztof