[PATCH v4 2/6] dt-bindings: clock: axg-audio: Add mclk and sclk pad clock ids

jiebing chen via B4 Relay
2025-03-19T07:06:40Z

From: jiebing chen <jiebing.chen@amlogic.com>

Add clock IDs for the mclk pads found on s4 SoCs

Signed-off-by: jiebing chen <jiebing.chen@amlogic.com>
---
include/dt-bindings/clock/axg-audio-clkc.h | 11 +++++++++++
1 file changed, 11 insertions(+)

diff --git a/include/dt-bindings/clock/axg-audio-clkc.h b/include/dt-bindings/clock/axg-audio-clkc.h
index 607f23b83fa7287fe0403682ebf827e2df26a1ce..75dde05343d1fa74304ee21c9ec0541a8f51b15e 100644
--- a/include/dt-bindings/clock/axg-audio-clkc.h
+++ b/include/dt-bindings/clock/axg-audio-clkc.h
@@ -162,5 +162,16 @@
#define AUD_CLKID_EARCRX_DMAC_SEL 182
#define AUD_CLKID_EARCRX_DMAC_DIV 183
#define AUD_CLKID_EARCRX_DMAC 184
+#define AUD_CLKID_TDM_MCLK_PAD0_SEL 185
+#define AUD_CLKID_TDM_MCLK_PAD1_SEL 186
+#define AUD_CLKID_TDM_MCLK_PAD0_DIV 187
+#define AUD_CLKID_TDM_MCLK_PAD1_DIV 188
+#define AUD_CLKID_TDM_MCLK_PAD2 189
+#define AUD_CLKID_TDM_MCLK_PAD2_SEL 190
+#define AUD_CLKID_TDM_MCLK_PAD2_DIV 191
+#define AUD_CLKID_TDM_SCLK_PAD3 192
+#define AUD_CLKID_TDM_SCLK_PAD4 193
+#define AUD_CLKID_TDM_LRCLK_PAD3 194
+#define AUD_CLKID_TDM_LRCLK_PAD4 195

#endif /* __AXG_AUDIO_CLKC_BINDINGS_H */

--
2.43.0