Re: [PATCH 2/5] arm64: dts: qcom: Add Kalambo SoC

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 7/20/26 5:04 PM, Gopikrishna Garmidi wrote:
> 
> Hi Konrad,
> 
> Thanks a lot for the review and for catching these
>> On 7/18/26 2:06 PM, Gopikrishna Garmidi wrote:
>>> Introduce support for the Qualcomm Kalambo SoC. It is derived from Mahua
>>> with CPU cluster 0 removed, leaving it with just cluster 1. As a result,
>>> the PDP mailbox and SCP low-priority register windows are updated to
>>> match the reduced CPU complex. Everything else should work as-is.

[...]

> Does this look right to you, or would you prefer re-pointing cluster0's cores in place rather than delete + re-add?

Let's just delete the whole map and re-define it, I think
that's the least painful way to do it

> 
>>
>> [...]
>>
>>> +&pdp0_mbox {
>>> +    reg = <0 0x17610000 0 0x8000>, <0 0x1a980000 0 0x8000>;
>>> +};
>>
>> Are you sure about this change?
> 
> Yes — confirmed against the SoC memory map. The Tx window is the NCC0/NCC1 mailbox instance; dropping the former cluster0 moves the Tx base from NCC0 (0x19980000) to NCC1 (0x1a980000), while reg[0] (Rx) is shared and unchanged. I'll note this in the commit message.

Got it, I overlooked the 0/1 difference in the register name when
comparing

Konrad