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Thu, 24 Sep 2026 02:16:02 -0700 (PDT) X-Received: by 2002:a05:693c:6392:20b0:33c:12b6:2bfb with SMTP id 5a478bee46e88-34002edeeb7mr1515491eec.24.1790241361632; Thu, 24 Sep 2026 02:16:01 -0700 (PDT) Received: from [10.151.37.217] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-33e939fe502sm11845179eec.2.2026.09.24.02.15.55 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 24 Sep 2026 02:16:01 -0700 (PDT) Message-ID: <7bcffc7c-5dda-4ead-a053-7eb4980e43a4@oss.qualcomm.com> Date: Thu, 24 Sep 2026 14:45:53 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 05/11] dt-bindings: clock: qcom: ipq5332-gcc: Describe clock inputs per compatible To: Krzysztof Kozlowski , Bjorn Andersson , Stephen Boyd , Brian Masney , Jerome Brunet , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Georgi Djakov , Konrad Dybcio , Varadarajan Narayanan , Dmitry Baryshkov , Abel Vesa , Gokul Sriram Palanisamy , Sricharan Ramabadhran , Kathiravan T Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org References: <20260921-ipq_clk_changes-v1-0-d242e3d49648@oss.qualcomm.com> <20260921-ipq_clk_changes-v1-5-d242e3d49648@oss.qualcomm.com> <62a5fabc-3a06-42fa-9c6b-6504650e712b@kernel.org> Content-Language: en-US From: Kathiravan Thirumoorthy In-Reply-To: <62a5fabc-3a06-42fa-9c6b-6504650e712b@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwOTI0MDAzOCBTYWx0ZWRfXzlchGJjLPNG9 ooFCxHFykxxuHmAoF+DRSdRn+BebEbqInb5qc+YyTIMAFV3LeLsiEbkGnH0xj2hAWe7nYxuiSS7 Iu7Vgq6qx5QdJNxqb9NKpxU6Sc+sAJ6vFGBjieSsylMUXRk9z2OWdiii5jNnQtUWSnvP8DMoTrV kUfiWHyQP39NtsImhJZKhYlTwFW908vq8zhmnZUcAQeN6C6Yzf5TVtLebKYqzp4NYjjJ3vhi5mQ ZLO7pfPFSfe11YvhZ2tTDPJMUVhX7Z5f+gA0LEHbyzNFoK149Zler2x33mqw8tFphCQ5dw84cNW SFy/vTEc/4aQQtrHuLBEMF+EekwT1qGefsSvfUXuz+md4zsS5euQO/Wj0bphuZEZzQhhPU8dhKl W4YwCL0j7H4cQ1Z8weKc3nYZUNDUebUqpUUUEY2ySyZz3vodkXbJl3Nx26w43atIoJPTNFDu5nU RQXNXvnahFyvW5GAITQ== X-Authority-Analysis: v=2.4 cv=WK/qzXsR c=1 sm=1 tr=0 ts=6ab4ea53 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=VdqzKS8jKosA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=X-K6lUb4N05xD90F8XcA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-Spam-Info: AW1haW4tMjYwOTI0MDAzOCBTYWx0ZWRfX/DUoMdCB4n4k ge4m2TnpE8pJLuPCK8xrWT6p16VD0dE8/XNztdVUm7Y+Oh9DzRRKRwwHpmJ96enAZaVZ7zVpLBq rSY+FIsRVlMv2sMmt0VOR1j1UBxcykE= X-Proofpoint-ORIG-GUID: Z1VzG6kT4ejFwsdY7uXQ7t0BGnHsmy-I X-Proofpoint-GUID: Z1VzG6kT4ejFwsdY7uXQ7t0BGnHsmy-I X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-09-24_02,2026-09-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 clxscore=1015 bulkscore=0 suspectscore=0 adultscore=0 priorityscore=1501 malwarescore=0 lowpriorityscore=0 impostorscore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2609240038 On 9/23/2026 2:17 PM, Krzysztof Kozlowski wrote: > On 21/09/2026 08:19, Kathiravan Thirumoorthy wrote: >> The IPQ5332 and IPQ5424 GCC blocks use different clock input orderings. >> Document the clock inputs in compatible-specific schema constraints instead >> of using a common clock description. >> >> Also add the 375 MHz PPE clock generated by the CMN PLL to the IPQ5424 >> clock input list. >> >> This keeps the binding aligned with the clock ordering used by the >> existing DTS and GCC driver implementations. >> >> Signed-off-by: Kathiravan Thirumoorthy >> --- >> .../bindings/clock/qcom,ipq5332-gcc.yaml | 26 +++++++++++++--------- >> 1 file changed, 16 insertions(+), 10 deletions(-) >> >> diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> index 1230183fc0a9..fb39dffca988 100644 >> --- a/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-gcc.yaml >> @@ -25,14 +25,7 @@ properties: >> >> clocks: >> minItems: 5 >> - items: >> - - description: Board XO clock source >> - - description: Sleep clock source >> - - description: PCIE 2lane PHY pipe clock source >> - - description: PCIE 2lane x1 PHY pipe clock source (For second lane) >> - - description: USB PCIE wrapper pipe clock source >> - - description: PCIE 2-lane PHY2 pipe clock source >> - - description: PCIE 2-lane PHY3 pipe clock source > > You are changing the order which is ABI break. Describe the actual > problem to justify such change. Are you saying this was broken since > beginning or what exactly is not working here? The driver was added by > Qualcomm in 2024, so how did it even work? It's not some 10 yo legacy > where we did some mistakes in binding while converting from TXT. > > Also, I do not get why the list cannot be shared. When the bindings was posted, list is combined for both IPQ5332 and IPQ5424. But the driver wasn't updated and it was following the below order, so was DTS, which is not compatible the DT binding description. enum {         DT_XO,         DT_SLEEP_CLK,         DT_PCIE30_PHY0_PIPE_CLK,         DT_PCIE30_PHY1_PIPE_CLK,         DT_PCIE30_PHY2_PIPE_CLK,         DT_PCIE30_PHY3_PIPE_CLK,         DT_USB_PCIE_WRAPPER_PIPE_CLK,         DT_CMN_PLL_NSS_375M_CLK, }; So I'm splitting the description between IPQ5332 and IPQ5424 to matching with the DTS and the driver description. > > Best regards, > Krzysztof