From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-alma10-1.taild15c8.ts.net [100.103.45.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A70B3BADB7; Fri, 22 May 2026 09:16:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=100.103.45.18 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779441411; cv=none; b=BBpsqjGrxvg4BJH2aeLP9PUlc7Zu2iiJBHiKH6T/5vX5h0Pq/W66rguXjWD2RLU4eFDL3KclWk98SRQZ9AgTO1BhhLfvX4pzCKGvT5VxXL9ykI42s0zOCJQudsKY7kb0ODUa9U738LgaTrKT6odgnSuEsoR6S9rvp/5Ege6TNYQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1779441411; c=relaxed/simple; bh=n+spfNVVS+GI8264VRMvQxK9NQgTox7CsKfUOhYTb4c=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=F1lziJZ7v9TsqKM0UbCCbEC5hME0LcMPjbpM9S2zOkt5X7B9Gf76IC3HFkfnXCR+3/ZqSAjNY68R+4lYqwbOD5m7y4HUu+EYyv/HhW5n39fkmrT9VpUrYvzk4+Jhx79Rc6AUrD5gFu/c//dReJNPRkDmDEy3qgnrJ7AmH3FH328= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=B/NJF9xZ; arc=none smtp.client-ip=100.103.45.18 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="B/NJF9xZ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 49BCD1F000E9; Fri, 22 May 2026 09:16:43 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1779441406; bh=WzBfufw4gsYrpdbP3F7fvJ8me51W/Y5BIcajdiRbGaA=; h=Date:Subject:To:Cc:References:From:In-Reply-To; b=B/NJF9xZWYqY981BOl9XMhydNqyZ58WfjpUI7KVuJ2oFkq/D6D1d8b6jcfvQtVcEO M7d48rvU7scHsCE23bvqZOTWII3DNH8EwAo1V4TFzLEcRmTM+lgZILr/vJh0hdsuXc b/bNeCJlL0elNxZwc5z24JGRRcuf+fGnGTEzBLQLfpRV/AP2qyGB3osg1aELGpiw4F DLYZiufH3bfm7JrarPG2nQS75EZW+QIFtDzCh41Gsn8+hJle97IXohHI/J2znmbtTa DjOVxfxhdr0tXv50SXAm8yu0nkigbgzBN5FfyRg6bLDwjXH7T3Sz0RegKoQBt/3/hq eJ0zQO7YV79yg== Message-ID: <7c458070-a56a-4d49-89fc-efeb388beffc@kernel.org> Date: Fri, 22 May 2026 11:16:41 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 02/10] dt-bindings: clock: Add Amlogic A9 PLL clock controller To: Jian Hu Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Jerome Brunet , Xianwei Zhao , Kevin Hilman , Martin Blumenstingl , linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-amlogic@lists.infradead.org, linux-arm-kernel@lists.infradead.org References: <20260511-b4-a9_clk-v1-0-41cb4071b7c9@amlogic.com> <20260511-b4-a9_clk-v1-2-41cb4071b7c9@amlogic.com> <20260515-subtle-sepia-tuatara-cfee3d@quoll> <40e83bed-e7a0-4c66-806c-c2988c5d0f33@amlogic.com> From: Krzysztof Kozlowski Content-Language: en-US Autocrypt: addr=krzk@kernel.org; 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charset=UTF-8 Content-Transfer-Encoding: 7bit On 22/05/2026 08:20, Jian Hu wrote: > Hi Krzysztof, > > Thanks for your review. > > On 5/15/2026 4:09 PM, Krzysztof Kozlowski wrote: >> [ EXTERNAL EMAIL ] >> >> On Mon, May 11, 2026 at 08:47:24PM +0800, Jian Hu wrote: >>> Add the PLL clock controller dt-bindings for the Amlogic A9 SoC family. >>> >>> Signed-off-by: Jian Hu >>> --- >>> .../bindings/clock/amlogic,a9-pll-clkc.yaml | 110 +++++++++++++++++++++ >>> include/dt-bindings/clock/amlogic,a9-pll-clkc.h | 55 +++++++++++ >>> 2 files changed, 165 insertions(+) >>> >>> diff --git a/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml >>> new file mode 100644 >>> index 000000000000..4ee6013ba1a1 >>> --- /dev/null >>> +++ b/Documentation/devicetree/bindings/clock/amlogic,a9-pll-clkc.yaml >>> @@ -0,0 +1,110 @@ >>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) >>> +# Copyright (C) 2026 Amlogic, Inc. All rights reserved >>> +%YAML 1.2 >>> +--- >>> +$id: http://devicetree.org/schemas/clock/amlogic,a9-pll-clkc.yaml# >>> +$schema: http://devicetree.org/meta-schemas/core.yaml# >>> + >>> +title: Amlogic A9 Series PLL Clock Controller >>> + >>> +maintainers: >>> + - Neil Armstrong >>> + - Jerome Brunet >>> + - Jian Hu >>> + - Xianwei Zhao >>> + >>> +properties: >>> + compatible: >>> + enum: >>> + - amlogic,a9-gp0-pll >>> + - amlogic,a9-hifi0-pll >>> + - amlogic,a9-hifi1-pll >>> + - amlogic,a9-mclk0-pll >>> + - amlogic,a9-mclk1-pll >>> + >>> + reg: >>> + maxItems: 1 >>> + >>> + '#clock-cells': >>> + const: 1 >>> + >>> + clocks: >>> + items: >>> + - description: pll input oscillator gate >>> + - description: fixed input clock source for mclk_sel_0 >>> + - description: u3p2pll input clock source for mclk_sel_0 (optional) >> Second clock is also optional. Drop "(optional)" comment, just >> confusing. > > > GP0 has only one parent clock, while MCLK has three. > > The second and third parent entries of GP0 are vacant, > > so they need to be marked optional. > > I will add the optional property for the second clock in the next revision. How? Read the previous feedback... Best regards, Krzysztof