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From: matthew.gerlach@linux.intel.com
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: lpieralisi@kernel.org, kw@linux.com,
	manivannan.sadhasivam@linaro.org,  robh@kernel.org,
	bhelgaas@google.com, krzk+dt@kernel.org,  conor+dt@kernel.org,
	dinguyen@kernel.org, joyce.ooi@intel.com,
	 linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	 linux-kernel@vger.kernel.org, matthew.gerlach@altera.com,
	 peter.colberg@altera.com
Subject: Re: [PATCH v5 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port
Date: Sat, 1 Feb 2025 11:12:51 -0800 (PST)	[thread overview]
Message-ID: <7c802294-97f6-3e9-4028-686484a525c5@linux.intel.com> (raw)
In-Reply-To: <40a3dced-defe-412d-b5b2-efcc9619d172@kernel.org>



On Thu, 30 Jan 2025, Krzysztof Kozlowski wrote:

> On 29/01/2025 20:42, matthew.gerlach@linux.intel.com wrote:
>>
>>
>> On Wed, 29 Jan 2025, Krzysztof Kozlowski wrote:
>>
>>> On 27/01/2025 18:35, Matthew Gerlach wrote:
>>>> Add the base device tree for support of the PCIe Root Port
>>>> for the Agilex family of chips.
>>>>
>>>> Signed-off-by: Matthew Gerlach <matthew.gerlach@linux.intel.com>
>>>> ---
>>>> v3:
>>>>  - Remove accepted patches from patch set.
>>>>
>>>> v2:
>>>>  - Rename node to fix schema check error.
>>>> ---
>>>>  .../intel/socfpga_agilex_pcie_root_port.dtsi  | 55 +++++++++++++++++++
>>>>  1 file changed, 55 insertions(+)
>>>>  create mode 100644 arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>>>>
>>>> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>>>> new file mode 100644
>>>> index 000000000000..50f131f5791b
>>>> --- /dev/null
>>>> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_pcie_root_port.dtsi
>>>> @@ -0,0 +1,55 @@
>>>> +// SPDX-License-Identifier:     GPL-2.0
>>>
>>> Odd spaces in SPDX tag.
>>
>> Yes, there should only be one space.
>>
>>>
>>>> +/*
>>>> + * Copyright (C) 2024, Intel Corporation
>>>> + */
>>>> +&soc0 {
>>>> +	aglx_hps_bridges: fpga-bus@80000000 {
>>>> +		compatible = "simple-bus";
>>>> +		reg = <0x80000000 0x20200000>,
>>>> +		      <0xf9000000 0x00100000>;
>>>> +		reg-names = "axi_h2f", "axi_h2f_lw";
>>>
>>> Where is this binding defined?
>>
>> The bindings for these reg-names are not currently defined anywhere, but
>
> Then you cannot use them.
>
>> they are also referenced in the following:
>>      Documentation/devicetree/bindings/soc/intel/intel,hps-copy-engine.yaml
>>      arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts
>> I am not exactly sure where the right place is to define them, maybe
>> Documentation/devicetree/bindings/arm/intel,socfpga.yaml. On the other
>> hand, no code references these names; so it might make sense to just
>> remove them.
>
> In general: nowhere, because simple bus does not have such properties.
> It's not about reg-names only - you cannot have reg. You just did not
> define here simple-bus.

I understand. I will remove reg and reg-names.

>
> Best regards,
> Krzysztof
>

Thanks for the review,
Matthew Gerlach

  reply	other threads:[~2025-02-01 19:12 UTC|newest]

Thread overview: 29+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-27 17:35 [PATCH v5 0/5] Add PCIe Root Port support for Agilex family of chips Matthew Gerlach
2025-01-27 17:35 ` [PATCH v5 1/5] dt-bindings: PCI: altera: Add binding for Agilex Matthew Gerlach
2025-01-30  7:34   ` Krzysztof Kozlowski
2025-02-01 18:11     ` matthew.gerlach
2025-01-27 17:35 ` [PATCH v5 2/5] arm64: dts: agilex: add soc0 label Matthew Gerlach
2025-01-29  9:45   ` Krzysztof Kozlowski
2025-01-29 19:10     ` matthew.gerlach
2025-01-27 17:35 ` [PATCH v5 3/5] arm64: dts: agilex: add dtsi for PCIe Root Port Matthew Gerlach
2025-01-29  9:47   ` Krzysztof Kozlowski
2025-01-29 19:42     ` matthew.gerlach
2025-01-30  7:26       ` Krzysztof Kozlowski
2025-02-01 19:12         ` matthew.gerlach [this message]
2025-02-02 14:17           ` Krzysztof Kozlowski
2025-02-02 18:49             ` matthew.gerlach
2025-02-02 19:02               ` Krzysztof Kozlowski
2025-02-04 17:15                 ` matthew.gerlach
2025-01-29 20:43   ` Frank Li
2025-02-01 18:07     ` matthew.gerlach
2025-01-27 17:35 ` [PATCH v5 4/5] arm64: dts: agilex: add dts enabling " Matthew Gerlach
2025-01-29  9:49   ` Krzysztof Kozlowski
2025-01-29 22:54     ` matthew.gerlach
2025-01-30  7:31       ` Krzysztof Kozlowski
2025-02-04 16:57         ` matthew.gerlach
2025-02-05  7:32           ` Krzysztof Kozlowski
2025-01-27 17:35 ` [PATCH v5 5/5] PCI: altera: Add Agilex support Matthew Gerlach
2025-01-29  9:50   ` Krzysztof Kozlowski
2025-01-29 23:03     ` matthew.gerlach
2025-02-03 14:18   ` Manivannan Sadhasivam
2025-02-03 14:42     ` Krzysztof Kozlowski

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