From: Bhupesh Sharma <bhupesh.sharma@linaro.org>
To: Komal Bajaj <quic_kbajaj@quicinc.com>,
Ulf Hansson <ulf.hansson@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org
Subject: Re: [PATCH 2/4] arm: dts: qcom: qdu1000: Add SDHCI node
Date: Fri, 19 May 2023 15:35:51 +0530 [thread overview]
Message-ID: <7cf74a2b-21e3-4a0d-5791-d7d97e21cf30@linaro.org> (raw)
In-Reply-To: <20230519085122.15758-3-quic_kbajaj@quicinc.com>
Hi Komal,
On 5/19/23 2:21 PM, Komal Bajaj wrote:
> Add sdhc node for eMMC on QDU1000 and QRU1000 SoCs.
>
> Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
> ---
> arch/arm64/boot/dts/qcom/qdu1000.dtsi | 60 +++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/qdu1000.dtsi b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> index 734438113bba..6113def66a08 100644
> --- a/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> +++ b/arch/arm64/boot/dts/qcom/qdu1000.dtsi
> @@ -19,6 +19,10 @@
>
> chosen: chosen { };
>
> + aliases {
> + mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
Please use the right comment formats /* text */
Also, just /* eMMC */ would be fine here.
> + };
> +
> cpus {
> #address-cells = <2>;
> #size-cells = <0>;
> @@ -842,6 +846,62 @@
> #hwlock-cells = <1>;
> };
>
> + sdhc_1: mmc@8804000 {
> + compatible = "qcom,qdu1000-sdhci", "qcom,sdhci-msm-v5";
> + reg = <0x0 0x08804000 0x0 0x1000>,
> + <0x0 0x08805000 0x0 0x1000>;
> +
> + reg-names = "hc", "cqhci";
> +
> + interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hc_irq", "pwr_irq";
> +
> + clocks = <&gcc GCC_SDCC5_AHB_CLK>,
> + <&gcc GCC_SDCC5_APPS_CLK>,
> + <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "iface", "core", "xo";
> +
> + /* Add dt entry for gcc hw reset */
Please drop the comment above - it's not needed.
> + resets = <&gcc GCC_SDCC5_BCR>;
> +
> + interconnects = <&system_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &system_noc SLAVE_SDCC_2 0>;
> + interconnect-names = "sdhc-ddr", "cpu-sdhc";
> + power-domains = <&rpmhpd QDU1000_CX>;
> + operating-points-v2 = <&sdhc1_opp_table>;
> +
> + iommus = <&apps_smmu 0x0080 0x0>;
> + dma-coherent;
> +
> + bus-width = <8>;
> + non-removable;
> + supports-cqe;
> +
> + no-sd;
> + no-sd;
Can we club the following 3 together:
non-removable;
no-sd;
no-sd;
And normally these is a part of board file (.dts), right?
Thanks,
Bhupesh
> + mmc-ddr-1_8v;
> + mmc-hs200-1_8v;
> + mmc-hs400-1_8v;
> + mmc-hs400-enhanced-strobe;
> + cap-mmc-hw-reset;
> +
> + qcom,dll-config = <0x0007642c>;
> + qcom,ddr-config = <0x80040868>;
> +
> + status = "disabled";
> +
> + sdhc1_opp_table: opp-table {
> + compatible = "operating-points-v2";
> +
> + opp-384000000 {
> + opp-hz = /bits/ 64 <384000000>;
> + required-opps = <&rpmhpd_opp_min_svs>;
> + };
> + };
> + };
> +
> pdc: interrupt-controller@b220000 {
> compatible = "qcom,qdu1000-pdc", "qcom,pdc";
> reg = <0x0 0xb220000 0x0 0x30000>, <0x0 0x174000f0 0x0 0x64>;
> --
> 2.17.1
>
next prev parent reply other threads:[~2023-05-19 10:06 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 8:51 [PATCH 0/4] arm64: dts: qcom: qdu1000: add SDHCI Komal Bajaj
2023-05-19 8:51 ` [PATCH 1/4] dt-bindings: mmc: sdhci-msm: Document the QDU1000/QRU1000 compatible Komal Bajaj
2023-05-19 10:07 ` Bhupesh Sharma
2023-05-19 11:39 ` Komal Bajaj
2023-05-19 15:56 ` Conor Dooley
2023-05-19 8:51 ` [PATCH 2/4] arm: dts: qcom: qdu1000: Add SDHCI node Komal Bajaj
2023-05-19 10:05 ` Bhupesh Sharma [this message]
2023-05-19 11:55 ` Komal Bajaj
2023-05-20 11:23 ` Konrad Dybcio
2023-05-22 7:02 ` Komal Bajaj
2023-05-19 8:51 ` [PATCH 3/4] arm64: dts: qcom: qdu1000: Add SDHCI1 pin configuration to DTSI Komal Bajaj
2023-05-19 10:15 ` Bhupesh Sharma
2023-05-19 8:51 ` [PATCH 4/4] arm64: dts: qcom: qdu1000-idp: add SDHCI for emmc Komal Bajaj
2023-05-19 10:13 ` Bhupesh Sharma
2023-05-20 11:24 ` Konrad Dybcio
2023-05-22 6:31 ` Komal Bajaj
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=7cf74a2b-21e3-4a0d-5791-d7d97e21cf30@linaro.org \
--to=bhupesh.sharma@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-mmc@vger.kernel.org \
--cc=quic_kbajaj@quicinc.com \
--cc=robh+dt@kernel.org \
--cc=ulf.hansson@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).