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[188.141.3.146]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9e64casm662410f8f.73.2025.03.20.15.06.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 20 Mar 2025 15:06:32 -0700 (PDT) Message-ID: <7dc8700f-0d53-45f5-bfff-2bec71c7053e@linaro.org> Date: Thu, 20 Mar 2025 22:06:31 +0000 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v1 2/3] arm64: dts: qcom: x1e80100: add bus topology for PCIe domain 3 To: Wenbin Yao , andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, quic_qianyu@quicinc.com, sfr@canb.auug.org.au, linux-arm-kernel@lists.infradead.org References: <20250320055502.274849-1-quic_wenbyao@quicinc.com> <20250320055502.274849-3-quic_wenbyao@quicinc.com> Content-Language: en-US From: Bryan O'Donoghue In-Reply-To: <20250320055502.274849-3-quic_wenbyao@quicinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 20/03/2025 05:55, Wenbin Yao wrote: > From: Qiang Yu > > Add pcie3port node to represent the PCIe bridge of PCIe3 so that PCI slot > voltage rails can be described under this node in the board's dts. > > Signed-off-by: Qiang Yu > Signed-off-by: Wenbin Yao > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 46b79fce9..32e8d400a 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -3287,6 +3287,16 @@ opp-128000000 { > opp-peak-kBps = <15753000 1>; > }; > }; > + pcie3port: pcie@0 { Missing newline, please check your dtb checks. > + device_type = "pci"; > + compatible = "pciclass,0604"; > + reg = <0x0 0x0 0x0 0x0 0x0>; > + bus-range = <0x01 0xff>; > + > + #address-cells = <3>; > + #size-cells = <2>; > + ranges; > + }; > }; Why is pice3port the only port to be enabled ? What about the other ports ? > pcie3_phy: phy@1be0000 { > -- > 2.34.1 > > --- bod