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From: Jesse Taube <mr.bossman075@gmail.com>
To: Yixun Lan <dlan@gentoo.org>
Cc: Yangyu Chen <cyy@cyyself.name>,
	Jisheng Zhang <jszhang@kernel.org>,
	Inochi Amaoto <inochiama@outlook.com>,
	Icenowy Zheng <uwu@icenowy.me>,
	Meng Zhang <zhangmeng.kevin@spacemit.com>,
	Meng Zhang <kevin.z.m@hotmail.com>,
	devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org,
	Yixun Lan <dlan@gentoo.org>,
	Linus Walleij <linus.walleij@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor@kernel.org>
Subject: [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3
Date: Sun, 15 Sep 2024 10:45:51 -0400	[thread overview]
Message-ID: <7ede7ca6-f8db-4b38-a1cc-8be3d0db7fae@gmail.com> (raw)


Before pinctrl driver implemented, the uart0 controller reply on
bootloader for setting correct pin mux and configurations.

Now, let's add pinctrl property to uart0 of Bananapi-F3 board.

Signed-off-by: Yixun Lan <dlan@gentoo.org>
---
  arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts |  3 +++
  arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi    | 20 ++++++++++++++++++++
  arch/riscv/boot/dts/spacemit/k1.dtsi            |  5 +++++
  3 files changed, 28 insertions(+)

diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts 
b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
index 023274189b492..bc88d4de25a62 100644
--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
+++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts
@@ -4,6 +4,7 @@
   */

  #include "k1.dtsi"
+#include "k1-pinctrl.dtsi"

  / {
  	model = "Banana Pi BPI-F3";
@@ -15,5 +16,7 @@ chosen {
  };

  &uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart0_2_cfg>;
  	status = "okay";
  };
diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi 
b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
new file mode 100644
index 0000000000000..a8eac5517f857
--- /dev/null
+++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (c) 2024 Yixun Lan <dlan@gentoo.org>
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+
+#define K1_PADCONF(pin, func) (((pin) << 16) | (func))

It would be nice to have a pinfunc header like
arch/arm/boot/dts/nxp/imx/imx7ulp-pinfunc.h.
It would reference and encode the data of "3.2 Pin Multiplex" in
https://developer.spacemit.com/documentation?token=An1vwTwKaigaXRkYfwmcznTXned 
, the document you attached in the summary.

Otherwise,
Acked-by: Jesse Taube <Mr.Bossman075@gmail.com>

+
+&pinctrl {
+	uart0_2_cfg: uart0-2-cfg {
+		uart0-2-pins {
+			pinmux = <K1_PADCONF(68, 2)>,
+				 <K1_PADCONF(69, 2)>;
+
+			bias-pull-up = <0>;
+			drive-strength = <32>;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi 
b/arch/riscv/boot/dts/spacemit/k1.dtsi
index 0777bf9e01183..a2d5f7d4a942a 100644
--- a/arch/riscv/boot/dts/spacemit/k1.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k1.dtsi
@@ -416,6 +416,11 @@ uart9: serial@d4017800 {
  			status = "disabled";
  		};

+		pinctrl: pinctrl@d401e000 {
+			compatible = "spacemit,k1-pinctrl";
+			reg = <0x0 0xd401e000 0x0 0x400>;
+		};
+
  		plic: interrupt-controller@e0000000 {
  			compatible = "spacemit,k1-plic", "sifive,plic-1.0.0";
  			reg = <0x0 0xe0000000 0x0 0x4000000>;

-- 
2.45.2

             reply	other threads:[~2024-09-15 14:45 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-09-15 14:45 Jesse Taube [this message]
2024-09-16  2:45 ` [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 Yixun Lan
2024-09-16 14:18   ` Jesse T
2024-09-16 23:47     ` Yixun Lan
  -- strict thread matches above, loose matches on Subject: below --
2024-09-03 12:26 [PATCH v4 0/3] riscv: spacemit: add pinctrl support to K1 SoC Yixun Lan
2024-09-03 12:26 ` [PATCH v4 3/3] riscv: dts: spacemit: add pinctrl property to uart0 in BPI-F3 Yixun Lan

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