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Wed, 14 May 2025 10:26:24 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id C8B5240044; Wed, 14 May 2025 10:25:13 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 1C3FDB3A736; Wed, 14 May 2025 10:24:03 +0200 (CEST) Received: from [10.48.86.79] (10.48.86.79) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 14 May 2025 10:24:02 +0200 Message-ID: <7f79af9a-2b42-48c0-98c5-6bf2afc61206@foss.st.com> Date: Wed, 14 May 2025 10:24:02 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: (subset)[PATCH v6 0/7] Add STM32MP25 LPTIM support: MFD, PWM, IIO, counter, clocksource To: Fabrice Gasnier , , , CC: , , , , , , , , , , , , , , References: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> Content-Language: en-US From: Alexandre TORGUE In-Reply-To: <20250429125133.1574167-1-fabrice.gasnier@foss.st.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-14_02,2025-05-14_02,2025-02-21_01 Hi Fabrice On 4/29/25 14:51, Fabrice Gasnier wrote: > This series adds support for STM32MP25 to MFD PWM, IIO, counter and > clocksource low-power timer (LPTIM) drivers. > This new variant is managed by using a new DT compatible string, hardware > configuration and version registers. > It comes with a slightly updated register set, some new features and new > interconnect signals inside the SoC. > Same feature list as on STM32MP1x is supported currently. > The device tree files add all instances in stm32mp251 dtsi file. > Following patches are applied on stm32-next: [PATCH v6 5/7] arm64: defconfig: enable STM32 LP timer clockevent driver [PATCH v6 6/7] arm64: dts: st: add low-power timer nodes on stm32mp251 [PATCH v6 7/7] arm64: dts: st: use lptimer3 as tick broadcast source on stm32mp257f-ev1 Thanks Alex