* [PATCH 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP PCIe EP compatibles
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:06 ` [PATCH 2/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6SX " Richard Zhu
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add i.MX6Q and i.MX6QP PCIe EP compatibles.
- Make the interrupts property optional, since i.MX6Q/i.MX6QP PCIe
don't have DMA capability.
- To pass the schema check, specify the clocks property refer to the
different platforms.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
.../bindings/pci/fsl,imx6q-pcie-ep.yaml | 31 ++++++++++++++++---
1 file changed, 27 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
index ee155ed5f181..9b881777c801 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -19,6 +19,8 @@ description: |+
properties:
compatible:
enum:
+ - fsl,imx6q-pcie-ep
+ - fsl,imx6qp-pcie-ep
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8mp-pcie-ep
@@ -46,7 +48,7 @@ properties:
interrupts:
items:
- - description: builtin eDMA interrupter.
+ - description: builtin eDMA interrupter (optional).
interrupt-names:
items:
@@ -56,8 +58,6 @@ required:
- compatible
- reg
- reg-names
- - interrupts
- - interrupt-names
allOf:
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
@@ -77,7 +77,30 @@ allOf:
- const: pcie_bus
- const: pcie_phy
- const: pcie_aux
- else:
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx6q-pcie-ep
+ - fsl,imx6qp-pcie-ep
+ then:
+ properties:
+ clocks:
+ maxItems: 3
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx8mm-pcie-ep
+ - fsl,imx8mp-pcie-ep
+ then:
properties:
clocks:
maxItems: 3
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6SX PCIe EP compatibles
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
2023-08-02 6:06 ` [PATCH 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP PCIe EP compatibles Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:06 ` [PATCH 3/9] dt-bindings: PCI: fsl,imx6q: Add i.MX7D " Richard Zhu
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add i.MX6SX PCIe EP compatibles.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
.../bindings/pci/fsl,imx6q-pcie-ep.yaml | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
index 9b881777c801..26448084340a 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -21,6 +21,7 @@ properties:
enum:
- fsl,imx6q-pcie-ep
- fsl,imx6qp-pcie-ep
+ - fsl,imx6sx-pcie-ep
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8mp-pcie-ep
@@ -62,6 +63,22 @@ required:
allOf:
- $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
- $ref: /schemas/pci/fsl,imx6q-pcie-common.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - fsl,imx6sx-pcie-ep
+ then:
+ properties:
+ clocks:
+ minItems: 4
+ clock-names:
+ items:
+ - const: pcie
+ - const: pcie_bus
+ - const: pcie_phy
+ - const: pcie_inbound_axi
+
- if:
properties:
compatible:
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 3/9] dt-bindings: PCI: fsl,imx6q: Add i.MX7D PCIe EP compatibles
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
2023-08-02 6:06 ` [PATCH 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP PCIe EP compatibles Richard Zhu
2023-08-02 6:06 ` [PATCH 2/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6SX " Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:06 ` [PATCH 4/9] arm: dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP supports Richard Zhu
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add i.MX7D PCIe EP compatibles.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
index 26448084340a..e8518642ba9b 100644
--- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
+++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml
@@ -22,6 +22,7 @@ properties:
- fsl,imx6q-pcie-ep
- fsl,imx6qp-pcie-ep
- fsl,imx6sx-pcie-ep
+ - fsl,imx7d-pcie-ep
- fsl,imx8mm-pcie-ep
- fsl,imx8mq-pcie-ep
- fsl,imx8mp-pcie-ep
@@ -101,6 +102,7 @@ allOf:
enum:
- fsl,imx6q-pcie-ep
- fsl,imx6qp-pcie-ep
+ - fsl,imx7d-pcie-ep
then:
properties:
clocks:
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 4/9] arm: dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP supports
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
` (2 preceding siblings ...)
2023-08-02 6:06 ` [PATCH 3/9] dt-bindings: PCI: fsl,imx6q: Add i.MX7D " Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:06 ` [PATCH 5/9] arm: dts: nxp: Add i.MX6SX PCIe EP support Richard Zhu
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add i.MX6QDL and i.MX6QP PCIe EP supports.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 14 ++++++++++++++
arch/arm/boot/dts/nxp/imx/imx6qp.dtsi | 4 ++++
2 files changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
index bda182edc589..be02f7882c68 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi
@@ -289,6 +289,20 @@ pcie: pcie@1ffc000 {
status = "disabled";
};
+ pcie_ep: pcie-ep@1ffc000 {
+ compatible = "fsl,imx6q-pcie-ep";
+ reg = <0x01ffc000 0x04000>, <0x01000000 0xf00000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
+ <&clks IMX6QDL_CLK_LVDS1_GATE>,
+ <&clks IMX6QDL_CLK_PCIE_REF_125M>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
+
aips1: bus@2000000 { /* AIPS1 */
compatible = "fsl,aips-bus", "simple-bus";
#address-cells = <1>;
diff --git a/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi
index fc164991d2ae..4ca53a4c254c 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6qp.dtsi
@@ -118,3 +118,7 @@ &mmdc0 {
&pcie {
compatible = "fsl,imx6qp-pcie";
};
+
+&pcie_ep {
+ compatible = "fsl,imx6qp-pcie-ep";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 5/9] arm: dts: nxp: Add i.MX6SX PCIe EP support
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
` (3 preceding siblings ...)
2023-08-02 6:06 ` [PATCH 4/9] arm: dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP supports Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:06 ` [PATCH 6/9] arm: dts: nxp: Add i.MX7D " Richard Zhu
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add i.MX6SX PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
index 3a4308666552..fc3a73b408d0 100644
--- a/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx6sx.dtsi
@@ -1465,5 +1465,22 @@ pcie: pcie@8ffc000 {
power-domain-names = "pcie", "pcie_phy";
status = "disabled";
};
+
+ pcie_ep: pcie-ep@8ffc000 {
+ compatible = "fsl,imx6sx-pcie-ep";
+ reg = <0x08ffc000 0x04000>, <0x08000000 0xf00000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ clocks = <&clks IMX6SX_CLK_PCIE_AXI>,
+ <&clks IMX6SX_CLK_LVDS1_OUT>,
+ <&clks IMX6SX_CLK_PCIE_REF_125M>,
+ <&clks IMX6SX_CLK_DISPLAY_AXI>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy", "pcie_inbound_axi";
+ power-domains = <&pd_disp>, <&pd_pci>;
+ power-domain-names = "pcie", "pcie_phy";
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 6/9] arm: dts: nxp: Add i.MX7D PCIe EP support
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
` (4 preceding siblings ...)
2023-08-02 6:06 ` [PATCH 5/9] arm: dts: nxp: Add i.MX6SX PCIe EP support Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:06 ` [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports Richard Zhu
` (3 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add i.MX7D PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
index 4b94b8afb55d..135684f17a20 100644
--- a/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
+++ b/arch/arm/boot/dts/nxp/imx/imx7d.dtsi
@@ -156,6 +156,33 @@ pcie: pcie@33800000 {
fsl,imx7d-pcie-phy = <&pcie_phy>;
status = "disabled";
};
+
+ pcie_ep: pcie-ep@33800000 {
+ compatible = "fsl,imx7d-pcie-ep";
+ reg = <0x33800000 0x4000>,
+ <0x40000000 0x10000000>;
+ reg-names = "dbi", "addr_space";
+ num-lanes = <1>;
+ clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,
+ <&clks IMX7D_PCIE_PHY_ROOT_CLK>;
+ clock-names = "pcie", "pcie_bus", "pcie_phy";
+ assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>,
+ <&clks IMX7D_PCIE_PHY_ROOT_SRC>;
+ assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>,
+ <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
+
+ fsl,max-link-speed = <2>;
+ power-domains = <&pgc_pcie_phy>;
+ resets = <&src IMX7_RESET_PCIEPHY>,
+ <&src IMX7_RESET_PCIE_CTRL_APPS_EN>,
+ <&src IMX7_RESET_PCIE_CTRL_APPS_TURNOFF>;
+ reset-names = "pciephy", "apps", "turnoff";
+ fsl,imx7d-pcie-phy = <&pcie_phy>;
+ num-ib-windows = <4>;
+ num-ob-windows = <4>;
+ status = "disabled";
+ };
};
};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
` (5 preceding siblings ...)
2023-08-02 6:06 ` [PATCH 6/9] arm: dts: nxp: Add i.MX7D " Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 21:54 ` Frank Li
2023-08-02 6:06 ` [PATCH 8/9] PCI: imx6: Add i.MX6SX PCIe EP support Richard Zhu
` (2 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add i.MX6Q and i.MX6QP PCIe EP supports.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 61 ++++++++++++++++++++++++++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 27aaa2a6bf39..4da9553b49b4 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -46,8 +46,10 @@
enum imx6_pcie_variants {
IMX6Q,
+ IMX6Q_EP,
IMX6SX,
IMX6QP,
+ IMX6QP_EP,
IMX7D,
IMX8MQ,
IMX8MM,
@@ -567,7 +569,9 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
break;
case IMX6QP:
+ case IMX6QP_EP:
case IMX6Q:
+ case IMX6Q_EP:
/* power up core phy and enable ref clock */
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
@@ -619,7 +623,9 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
break;
case IMX6QP:
+ case IMX6QP_EP:
case IMX6Q:
+ case IMX6Q_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
@@ -720,11 +726,13 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
IMX6SX_GPR5_PCIE_BTNRST_RESET);
break;
case IMX6QP:
+ case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST,
IMX6Q_GPR1_PCIE_SW_RST);
break;
case IMX6Q:
+ case IMX6Q_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
@@ -777,12 +785,14 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
break;
case IMX6QP:
+ case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
IMX6Q_GPR1_PCIE_SW_RST, 0);
usleep_range(200, 500);
break;
case IMX6Q: /* Nothing to do */
+ case IMX6Q_EP:
case IMX8MM:
case IMX8MM_EP:
case IMX8MP:
@@ -827,8 +837,10 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
switch (imx6_pcie->drvdata->variant) {
case IMX6Q:
+ case IMX6Q_EP:
case IMX6SX:
case IMX6QP:
+ case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2,
IMX6Q_GPR12_PCIE_CTL_2);
@@ -851,8 +863,10 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
switch (imx6_pcie->drvdata->variant) {
case IMX6Q:
+ case IMX6Q_EP:
case IMX6SX:
case IMX6QP:
+ case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6Q_GPR12_PCIE_CTL_2, 0);
break;
@@ -1077,6 +1091,27 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
return 0;
}
+/*
+ * i.MX6Q and i.MX6QP PCIe EP BAR definitions.
+ * +-----------------------------------------------------------------+
+ * | BAR0 | BAR1 | BAR2 | BAR3 | BAR4 | BAR5 |
+ * +----------|----------|----------|----------|----------|----------+
+ * | 64-bit | Disabled | 32-bit | 32-bit | Disabled | Disabled |
+ * | | | | Fixed | | |
+ * | | | | 256Bytes | | |
+ * | Prefetch | | Prefetch | None- | | |
+ * | Memory | | Memory | Prefetch | | |
+ * | | | | IO | | |
+ * +-----------------------------------------------------------------+
+ */
+static const struct pci_epc_features imx6q_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+ .reserved_bar = 1 << BAR_4 | 1 << BAR_5,
+ .align = SZ_64K,
+};
+
static const struct pci_epc_features imx8m_pcie_epc_features = {
.linkup_notifier = false,
.msi_capable = true,
@@ -1088,7 +1123,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
static const struct pci_epc_features*
imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
{
- return &imx8m_pcie_epc_features;
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
+
+ switch (imx6_pcie->drvdata->variant) {
+ case IMX6Q_EP:
+ case IMX6QP_EP:
+ return &imx6q_pcie_epc_features;
+ default:
+ return &imx8m_pcie_epc_features;
+ }
}
static const struct dw_pcie_ep_ops pcie_ep_ops = {
@@ -1157,6 +1201,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
case IMX6QP:
+ case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_PM_TURN_OFF,
IMX6SX_GPR12_PCIE_PM_TURN_OFF);
@@ -1478,6 +1523,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.dbi_length = 0x200,
.gpr = "fsl,imx6q-iomuxc-gpr",
},
+ [IMX6Q_EP] = {
+ .variant = IMX6Q_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
+ .gpr = "fsl,imx6q-iomuxc-gpr",
+ },
[IMX6SX] = {
.variant = IMX6SX,
.flags = IMX6_PCIE_FLAG_IMX6_PHY |
@@ -1493,6 +1544,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.dbi_length = 0x200,
.gpr = "fsl,imx6q-iomuxc-gpr",
},
+ [IMX6QP_EP] = {
+ .variant = IMX6QP_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
+ .gpr = "fsl,imx6q-iomuxc-gpr",
+ },
[IMX7D] = {
.variant = IMX7D,
.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
@@ -1531,8 +1588,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
+ { .compatible = "fsl,imx6q-pcie-ep", .data = &drvdata[IMX6Q_EP], },
{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
+ { .compatible = "fsl,imx6qp-pcie-ep", .data = &drvdata[IMX6QP_EP], },
{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports
2023-08-02 6:06 ` [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports Richard Zhu
@ 2023-08-02 21:54 ` Frank Li
2023-08-03 2:42 ` Hongxing Zhu
0 siblings, 1 reply; 14+ messages in thread
From: Frank Li @ 2023-08-02 21:54 UTC (permalink / raw)
To: Richard Zhu
Cc: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt,
linux-pci, devicetree, linux-arm-kernel, linux-kernel, kernel,
linux-imx
On Wed, Aug 02, 2023 at 02:06:49PM +0800, Richard Zhu wrote:
> Add i.MX6Q and i.MX6QP PCIe EP supports.
>
> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> ---
> drivers/pci/controller/dwc/pci-imx6.c | 61 ++++++++++++++++++++++++++-
> 1 file changed, 60 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
> index 27aaa2a6bf39..4da9553b49b4 100644
> --- a/drivers/pci/controller/dwc/pci-imx6.c
> +++ b/drivers/pci/controller/dwc/pci-imx6.c
> @@ -46,8 +46,10 @@
>
> enum imx6_pcie_variants {
> IMX6Q,
> + IMX6Q_EP,
> IMX6SX,
> IMX6QP,
> + IMX6QP_EP,
> IMX7D,
> IMX8MQ,
> IMX8MM,
> @@ -567,7 +569,9 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
> IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
> break;
> case IMX6QP:
> + case IMX6QP_EP:
> case IMX6Q:
> + case IMX6Q_EP:
> /* power up core phy and enable ref clock */
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
> @@ -619,7 +623,9 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
> clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
> break;
> case IMX6QP:
> + case IMX6QP_EP:
> case IMX6Q:
> + case IMX6Q_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> @@ -720,11 +726,13 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
> IMX6SX_GPR5_PCIE_BTNRST_RESET);
> break;
> case IMX6QP:
> + case IMX6QP_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_SW_RST,
> IMX6Q_GPR1_PCIE_SW_RST);
> break;
> case IMX6Q:
> + case IMX6Q_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> @@ -777,12 +785,14 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
> IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
> break;
> case IMX6QP:
> + case IMX6QP_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> IMX6Q_GPR1_PCIE_SW_RST, 0);
>
> usleep_range(200, 500);
> break;
> case IMX6Q: /* Nothing to do */
> + case IMX6Q_EP:
> case IMX8MM:
> case IMX8MM_EP:
> case IMX8MP:
> @@ -827,8 +837,10 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
>
> switch (imx6_pcie->drvdata->variant) {
> case IMX6Q:
> + case IMX6Q_EP:
> case IMX6SX:
> case IMX6QP:
> + case IMX6QP_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6Q_GPR12_PCIE_CTL_2,
> IMX6Q_GPR12_PCIE_CTL_2);
> @@ -851,8 +863,10 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
>
> switch (imx6_pcie->drvdata->variant) {
> case IMX6Q:
> + case IMX6Q_EP:
> case IMX6SX:
> case IMX6QP:
> + case IMX6QP_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6Q_GPR12_PCIE_CTL_2, 0);
> break;
> @@ -1077,6 +1091,27 @@ static int imx6_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> return 0;
> }
>
> +/*
> + * i.MX6Q and i.MX6QP PCIe EP BAR definitions.
> + * +-----------------------------------------------------------------+
> + * | BAR0 | BAR1 | BAR2 | BAR3 | BAR4 | BAR5 |
> + * +----------|----------|----------|----------|----------|----------+
> + * | 64-bit | Disabled | 32-bit | 32-bit | Disabled | Disabled |
> + * | | | | Fixed | | |
> + * | | | | 256Bytes | | |
> + * | Prefetch | | Prefetch | None- | | |
> + * | Memory | | Memory | Prefetch | | |
> + * | | | | IO | | |
> + * +-----------------------------------------------------------------+
> + */
> +static const struct pci_epc_features imx6q_pcie_epc_features = {
> + .linkup_notifier = false,
> + .msi_capable = true,
> + .msix_capable = false,
> + .reserved_bar = 1 << BAR_4 | 1 << BAR_5,
> + .align = SZ_64K,
> +};
> +
> static const struct pci_epc_features imx8m_pcie_epc_features = {
> .linkup_notifier = false,
> .msi_capable = true,
> @@ -1088,7 +1123,16 @@ static const struct pci_epc_features imx8m_pcie_epc_features = {
> static const struct pci_epc_features*
> imx6_pcie_ep_get_features(struct dw_pcie_ep *ep)
> {
> - return &imx8m_pcie_epc_features;
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> +
> + switch (imx6_pcie->drvdata->variant) {
> + case IMX6Q_EP:
> + case IMX6QP_EP:
> + return &imx6q_pcie_epc_features;
> + default:
> + return &imx8m_pcie_epc_features;
Could you add "const struct pci_epc_features" *epc_features in drvdata?
if (imx6_pcie->drvdata->epc_features)
return imx6_pcie->drvdata->epc_features;
return &imx8m_pcie_epc_features;
Needn't change this code if new chip added in future.
Frank
> + }
> }
>
> static const struct dw_pcie_ep_ops pcie_ep_ops = {
> @@ -1157,6 +1201,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
> switch (imx6_pcie->drvdata->variant) {
> case IMX6SX:
> case IMX6QP:
> + case IMX6QP_EP:
> regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> IMX6SX_GPR12_PCIE_PM_TURN_OFF,
> IMX6SX_GPR12_PCIE_PM_TURN_OFF);
> @@ -1478,6 +1523,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .dbi_length = 0x200,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> },
> + [IMX6Q_EP] = {
> + .variant = IMX6Q_EP,
> + .mode = DW_PCIE_EP_TYPE,
> + .flags = IMX6_PCIE_FLAG_IMX6_PHY,
> + .gpr = "fsl,imx6q-iomuxc-gpr",
See above comments
.epc_feature = &imx6q_pcie_epc_features;
Frank
> + },
> [IMX6SX] = {
> .variant = IMX6SX,
> .flags = IMX6_PCIE_FLAG_IMX6_PHY |
> @@ -1493,6 +1544,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> .dbi_length = 0x200,
> .gpr = "fsl,imx6q-iomuxc-gpr",
> },
> + [IMX6QP_EP] = {
> + .variant = IMX6QP_EP,
> + .mode = DW_PCIE_EP_TYPE,
> + .flags = IMX6_PCIE_FLAG_IMX6_PHY,
> + .gpr = "fsl,imx6q-iomuxc-gpr",
> + },
> [IMX7D] = {
> .variant = IMX7D,
> .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
> @@ -1531,8 +1588,10 @@ static const struct imx6_pcie_drvdata drvdata[] = {
>
> static const struct of_device_id imx6_pcie_of_match[] = {
> { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
> + { .compatible = "fsl,imx6q-pcie-ep", .data = &drvdata[IMX6Q_EP], },
> { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
> { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
> + { .compatible = "fsl,imx6qp-pcie-ep", .data = &drvdata[IMX6QP_EP], },
> { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
> { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
> { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 14+ messages in thread* RE: [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports
2023-08-02 21:54 ` Frank Li
@ 2023-08-03 2:42 ` Hongxing Zhu
0 siblings, 0 replies; 14+ messages in thread
From: Hongxing Zhu @ 2023-08-03 2:42 UTC (permalink / raw)
To: Frank Li
Cc: l.stach@pengutronix.de, shawnguo@kernel.org,
lpieralisi@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, linux-pci@vger.kernel.org,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, kernel@pengutronix.de, dl-linux-imx
Hi Frank:
Thanks for your reply.
> -----Original Message-----
> From: Frank Li <frank.li@nxp.com>
> Sent: 2023年8月3日 5:54
> To: Hongxing Zhu <hongxing.zhu@nxp.com>
> Cc: l.stach@pengutronix.de; shawnguo@kernel.org; lpieralisi@kernel.org;
> robh+dt@kernel.org; krzysztof.kozlowski+dt@linaro.org;
> linux-pci@vger.kernel.org; devicetree@vger.kernel.org;
> linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> kernel@pengutronix.de; dl-linux-imx <linux-imx@nxp.com>
> Subject: Re: [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports
>
> On Wed, Aug 02, 2023 at 02:06:49PM +0800, Richard Zhu wrote:
> > Add i.MX6Q and i.MX6QP PCIe EP supports.
> >
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> > drivers/pci/controller/dwc/pci-imx6.c | 61
> > ++++++++++++++++++++++++++-
> > 1 file changed, 60 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/controller/dwc/pci-imx6.c
> > b/drivers/pci/controller/dwc/pci-imx6.c
> > index 27aaa2a6bf39..4da9553b49b4 100644
> > --- a/drivers/pci/controller/dwc/pci-imx6.c
> > +++ b/drivers/pci/controller/dwc/pci-imx6.c
> > @@ -46,8 +46,10 @@
> >
> > enum imx6_pcie_variants {
> > IMX6Q,
> > + IMX6Q_EP,
> > IMX6SX,
> > IMX6QP,
> > + IMX6QP_EP,
> > IMX7D,
> > IMX8MQ,
> > IMX8MM,
> > @@ -567,7 +569,9 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie
> *imx6_pcie)
> > IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
> > break;
> > case IMX6QP:
> > + case IMX6QP_EP:
> > case IMX6Q:
> > + case IMX6Q_EP:
> > /* power up core phy and enable ref clock */
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); @@ -619,7
> +623,9 @@ static
> > void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
> > clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
> > break;
> > case IMX6QP:
> > + case IMX6QP_EP:
> > case IMX6Q:
> > + case IMX6Q_EP:
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > IMX6Q_GPR1_PCIE_REF_CLK_EN, 0);
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, @@
> -720,11
> > +726,13 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie
> *imx6_pcie)
> > IMX6SX_GPR5_PCIE_BTNRST_RESET);
> > break;
> > case IMX6QP:
> > + case IMX6QP_EP:
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > IMX6Q_GPR1_PCIE_SW_RST,
> > IMX6Q_GPR1_PCIE_SW_RST);
> > break;
> > case IMX6Q:
> > + case IMX6Q_EP:
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, @@
> -777,12
> > +785,14 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie
> *imx6_pcie)
> > IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
> > break;
> > case IMX6QP:
> > + case IMX6QP_EP:
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
> > IMX6Q_GPR1_PCIE_SW_RST, 0);
> >
> > usleep_range(200, 500);
> > break;
> > case IMX6Q: /* Nothing to do */
> > + case IMX6Q_EP:
> > case IMX8MM:
> > case IMX8MM_EP:
> > case IMX8MP:
> > @@ -827,8 +837,10 @@ static void imx6_pcie_ltssm_enable(struct device
> > *dev)
> >
> > switch (imx6_pcie->drvdata->variant) {
> > case IMX6Q:
> > + case IMX6Q_EP:
> > case IMX6SX:
> > case IMX6QP:
> > + case IMX6QP_EP:
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> > IMX6Q_GPR12_PCIE_CTL_2,
> > IMX6Q_GPR12_PCIE_CTL_2);
> > @@ -851,8 +863,10 @@ static void imx6_pcie_ltssm_disable(struct device
> > *dev)
> >
> > switch (imx6_pcie->drvdata->variant) {
> > case IMX6Q:
> > + case IMX6Q_EP:
> > case IMX6SX:
> > case IMX6QP:
> > + case IMX6QP_EP:
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> > IMX6Q_GPR12_PCIE_CTL_2, 0);
> > break;
> > @@ -1077,6 +1091,27 @@ static int imx6_pcie_ep_raise_irq(struct
> dw_pcie_ep *ep, u8 func_no,
> > return 0;
> > }
> >
> > +/*
> > + * i.MX6Q and i.MX6QP PCIe EP BAR definitions.
> > + * +-----------------------------------------------------------------+
> > + * | BAR0 | BAR1 | BAR2 | BAR3 | BAR4 | BAR5
> |
> > + * +----------|----------|----------|----------|----------|----------+
> > + * | 64-bit | Disabled | 32-bit | 32-bit | Disabled | Disabled |
> > + * | | | | Fixed | |
> |
> > + * | | | | 256Bytes | |
> |
> > + * | Prefetch | | Prefetch | None- | | |
> > + * | Memory | | Memory | Prefetch | |
> |
> > + * | | | | IO | |
> |
> > + *
> > ++-----------------------------------------------------------------+
> > + */
> > +static const struct pci_epc_features imx6q_pcie_epc_features = {
> > + .linkup_notifier = false,
> > + .msi_capable = true,
> > + .msix_capable = false,
> > + .reserved_bar = 1 << BAR_4 | 1 << BAR_5,
> > + .align = SZ_64K,
> > +};
> > +
> > static const struct pci_epc_features imx8m_pcie_epc_features = {
> > .linkup_notifier = false,
> > .msi_capable = true,
> > @@ -1088,7 +1123,16 @@ static const struct pci_epc_features
> > imx8m_pcie_epc_features = { static const struct pci_epc_features*
> > imx6_pcie_ep_get_features(struct dw_pcie_ep *ep) {
> > - return &imx8m_pcie_epc_features;
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
> > +
> > + switch (imx6_pcie->drvdata->variant) {
> > + case IMX6Q_EP:
> > + case IMX6QP_EP:
> > + return &imx6q_pcie_epc_features;
> > + default:
> > + return &imx8m_pcie_epc_features;
>
> Could you add "const struct pci_epc_features" *epc_features in drvdata?
>
> if (imx6_pcie->drvdata->epc_features)
> return imx6_pcie->drvdata->epc_features;
>
> return &imx8m_pcie_epc_features;
>
>
> Needn't change this code if new chip added in future.
Good suggestion, would follow this method to simple .get_features codes.
Thanks.
>
> Frank
>
> > + }
> > }
> >
> > static const struct dw_pcie_ep_ops pcie_ep_ops = { @@ -1157,6 +1201,7
> > @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
> > switch (imx6_pcie->drvdata->variant) {
> > case IMX6SX:
> > case IMX6QP:
> > + case IMX6QP_EP:
> > regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
> > IMX6SX_GPR12_PCIE_PM_TURN_OFF,
> > IMX6SX_GPR12_PCIE_PM_TURN_OFF);
> > @@ -1478,6 +1523,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .dbi_length = 0x200,
> > .gpr = "fsl,imx6q-iomuxc-gpr",
> > },
> > + [IMX6Q_EP] = {
> > + .variant = IMX6Q_EP,
> > + .mode = DW_PCIE_EP_TYPE,
> > + .flags = IMX6_PCIE_FLAG_IMX6_PHY,
> > + .gpr = "fsl,imx6q-iomuxc-gpr",
>
> See above comments
> .epc_feature = &imx6q_pcie_epc_features;
Got that. Thanks.
>
> Frank
>
> > + },
> > [IMX6SX] = {
> > .variant = IMX6SX,
> > .flags = IMX6_PCIE_FLAG_IMX6_PHY |
> > @@ -1493,6 +1544,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
> > .dbi_length = 0x200,
> > .gpr = "fsl,imx6q-iomuxc-gpr",
> > },
> > + [IMX6QP_EP] = {
> > + .variant = IMX6QP_EP,
> > + .mode = DW_PCIE_EP_TYPE,
> > + .flags = IMX6_PCIE_FLAG_IMX6_PHY,
> > + .gpr = "fsl,imx6q-iomuxc-gpr",
> > + },
> > [IMX7D] = {
> > .variant = IMX7D,
> > .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND, @@ -1531,8
> +1588,10 @@
> > static const struct imx6_pcie_drvdata drvdata[] = {
> >
> > static const struct of_device_id imx6_pcie_of_match[] = {
> > { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
> > + { .compatible = "fsl,imx6q-pcie-ep", .data = &drvdata[IMX6Q_EP], },
> > { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
> > { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
> > + { .compatible = "fsl,imx6qp-pcie-ep", .data = &drvdata[IMX6QP_EP],
> > +},
> > { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
> > { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
> > { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 8/9] PCI: imx6: Add i.MX6SX PCIe EP support
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
` (6 preceding siblings ...)
2023-08-02 6:06 ` [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:06 ` [PATCH 9/9] PCI: imx6: Add i.MX7D " Richard Zhu
2023-08-02 6:51 ` [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Ahmad Fatoum
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add the i.MX6SX PCIe EP support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index 4da9553b49b4..bcc83c9d0ec5 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -48,6 +48,7 @@ enum imx6_pcie_variants {
IMX6Q,
IMX6Q_EP,
IMX6SX,
+ IMX6SX_EP,
IMX6QP,
IMX6QP_EP,
IMX7D,
@@ -361,6 +362,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
break;
case IMX6SX:
+ case IMX6SX_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_RX_EQ_MASK,
IMX6SX_GPR12_PCIE_RX_EQ_2);
@@ -559,6 +561,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
+ case IMX6SX_EP:
ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
if (ret) {
dev_err(dev, "unable to enable pcie_axi clock\n");
@@ -620,6 +623,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
{
switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
+ case IMX6SX_EP:
clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
break;
case IMX6QP:
@@ -717,6 +721,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
reset_control_assert(imx6_pcie->apps_reset);
break;
case IMX6SX:
+ case IMX6SX_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
@@ -781,6 +786,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
break;
case IMX6SX:
+ case IMX6SX_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
break;
@@ -839,6 +845,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
case IMX6Q:
case IMX6Q_EP:
case IMX6SX:
+ case IMX6SX_EP:
case IMX6QP:
case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -865,6 +872,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
case IMX6Q:
case IMX6Q_EP:
case IMX6SX:
+ case IMX6SX_EP:
case IMX6QP:
case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -1200,6 +1208,7 @@ static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
/* Others poke directly at IOMUXC registers */
switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
+ case IMX6SX_EP:
case IMX6QP:
case IMX6QP_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
@@ -1363,6 +1372,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
switch (imx6_pcie->drvdata->variant) {
case IMX6SX:
+ case IMX6SX_EP:
imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
"pcie_inbound_axi");
if (IS_ERR(imx6_pcie->pcie_inbound_axi))
@@ -1536,6 +1546,12 @@ static const struct imx6_pcie_drvdata drvdata[] = {
IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx6q-iomuxc-gpr",
},
+ [IMX6SX_EP] = {
+ .variant = IMX6SX_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .flags = IMX6_PCIE_FLAG_IMX6_PHY,
+ .gpr = "fsl,imx6q-iomuxc-gpr",
+ },
[IMX6QP] = {
.variant = IMX6QP,
.flags = IMX6_PCIE_FLAG_IMX6_PHY |
@@ -1590,6 +1606,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
{ .compatible = "fsl,imx6q-pcie-ep", .data = &drvdata[IMX6Q_EP], },
{ .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
+ { .compatible = "fsl,imx6sx-pcie-ep", .data = &drvdata[IMX6SX_EP], },
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
{ .compatible = "fsl,imx6qp-pcie-ep", .data = &drvdata[IMX6QP_EP], },
{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 9/9] PCI: imx6: Add i.MX7D PCIe EP support
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
` (7 preceding siblings ...)
2023-08-02 6:06 ` [PATCH 8/9] PCI: imx6: Add i.MX6SX PCIe EP support Richard Zhu
@ 2023-08-02 6:06 ` Richard Zhu
2023-08-02 6:51 ` [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Ahmad Fatoum
9 siblings, 0 replies; 14+ messages in thread
From: Richard Zhu @ 2023-08-02 6:06 UTC (permalink / raw)
To: l.stach, shawnguo, lpieralisi, robh+dt, krzysztof.kozlowski+dt
Cc: hongxing.zhu, linux-pci, devicetree, linux-arm-kernel,
linux-kernel, kernel, linux-imx
Add the i.MX7D PCIe EP mode support.
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
---
drivers/pci/controller/dwc/pci-imx6.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c
index bcc83c9d0ec5..c1b9cc065963 100644
--- a/drivers/pci/controller/dwc/pci-imx6.c
+++ b/drivers/pci/controller/dwc/pci-imx6.c
@@ -52,6 +52,7 @@ enum imx6_pcie_variants {
IMX6QP,
IMX6QP_EP,
IMX7D,
+ IMX7D_EP,
IMX8MQ,
IMX8MM,
IMX8MP,
@@ -358,6 +359,7 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
0);
break;
case IMX7D:
+ case IMX7D_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
break;
@@ -589,6 +591,7 @@ static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
break;
case IMX7D:
+ case IMX7D_EP:
break;
case IMX8MM:
case IMX8MM_EP:
@@ -637,6 +640,7 @@ static void imx6_pcie_disable_ref_clk(struct imx6_pcie *imx6_pcie)
IMX6Q_GPR1_PCIE_TEST_PD);
break;
case IMX7D:
+ case IMX7D_EP:
regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
@@ -710,6 +714,7 @@ static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
{
switch (imx6_pcie->drvdata->variant) {
case IMX7D:
+ case IMX7D_EP:
case IMX8MQ:
case IMX8MQ_EP:
reset_control_assert(imx6_pcie->pciephy_reset);
@@ -762,6 +767,7 @@ static int imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
reset_control_deassert(imx6_pcie->pciephy_reset);
break;
case IMX7D:
+ case IMX7D_EP:
reset_control_deassert(imx6_pcie->pciephy_reset);
/* Workaround for ERR010728, failure of PCI-e PLL VCO to
@@ -853,6 +859,7 @@ static void imx6_pcie_ltssm_enable(struct device *dev)
IMX6Q_GPR12_PCIE_CTL_2);
break;
case IMX7D:
+ case IMX7D_EP:
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MM:
@@ -879,6 +886,7 @@ static void imx6_pcie_ltssm_disable(struct device *dev)
IMX6Q_GPR12_PCIE_CTL_2, 0);
break;
case IMX7D:
+ case IMX7D_EP:
case IMX8MQ:
case IMX8MQ_EP:
case IMX8MM:
@@ -1387,6 +1395,7 @@ static int imx6_pcie_probe(struct platform_device *pdev)
"pcie_aux clock source missing or invalid\n");
fallthrough;
case IMX7D:
+ case IMX7D_EP:
if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
imx6_pcie->controller_id = 1;
@@ -1571,6 +1580,11 @@ static const struct imx6_pcie_drvdata drvdata[] = {
.flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
.gpr = "fsl,imx7d-iomuxc-gpr",
},
+ [IMX7D_EP] = {
+ .variant = IMX7D_EP,
+ .mode = DW_PCIE_EP_TYPE,
+ .gpr = "fsl,imx7d-iomuxc-gpr",
+ },
[IMX8MQ] = {
.variant = IMX8MQ,
.gpr = "fsl,imx8mq-iomuxc-gpr",
@@ -1610,6 +1624,7 @@ static const struct of_device_id imx6_pcie_of_match[] = {
{ .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
{ .compatible = "fsl,imx6qp-pcie-ep", .data = &drvdata[IMX6QP_EP], },
{ .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
+ { .compatible = "fsl,imx7d-pcie-ep", .data = &drvdata[IMX7D_EP], },
{ .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
{ .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
{ .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 0/9] Add legacy i.MX PCIe EP mode supports
2023-08-02 6:06 [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Richard Zhu
` (8 preceding siblings ...)
2023-08-02 6:06 ` [PATCH 9/9] PCI: imx6: Add i.MX7D " Richard Zhu
@ 2023-08-02 6:51 ` Ahmad Fatoum
2023-08-02 14:08 ` Hongxing Zhu
9 siblings, 1 reply; 14+ messages in thread
From: Ahmad Fatoum @ 2023-08-02 6:51 UTC (permalink / raw)
To: Richard Zhu, l.stach, shawnguo, lpieralisi, robh+dt,
krzysztof.kozlowski+dt
Cc: devicetree, linux-pci, linux-kernel, linux-imx, kernel,
linux-arm-kernel
Hello Richard,
On 02.08.23 08:06, Richard Zhu wrote:
> Add legacy 32bit i.MX PCIe EP mode support
>
> The PCI controller contained in i.MX6/7 legacy SOCs is one dual mode
> PCIe controller, and can work either as RC or EP.
>
> This series add i.MX6/7 PCIe EP mode supports. And had been verified
> on i.MX6 sabresd and i.MX7 SDB boards.
>
> In the verification, one board PCIe is used as RC, the other one is used
> as EP.
> Use the cross TX/RX differential cable connect the two PCIe ports of
> these two boards.
>
> +-----------+ +------------+
> | PCIe TX |<-------------->|PCIe RX |
> | | | |
> | Board | | Board |
> | | | |
> | PCIe RX |<-------------->|PCIe TX |
> +-----------+ +------------+
I am curious what software you are running on both sides to test?
Do you use CONFIG_PCI_EPF_TEST? What do you run on RC side?
Thanks,
Ahmad
>
> [PATCH 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP PCIe
> [PATCH 2/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6SX PCIe EP
> [PATCH 3/9] dt-bindings: PCI: fsl,imx6q: Add i.MX7D PCIe EP
> [PATCH 4/9] arm: dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP supports
> [PATCH 5/9] arm: dts: nxp: Add i.MX6SX PCIe EP support
> [PATCH 6/9] arm: dts: nxp: Add i.MX7D PCIe EP support
> [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP PCIe EP supports
> [PATCH 8/9] PCI: imx6: Add i.MX6SX PCIe EP support
> [PATCH 9/9] PCI: imx6: Add i.MX7D PCIe EP support
>
> Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 50 +++++++++++++++++++++++++++++++++++++++++----
> arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 14 +++++++++++++
> arch/arm/boot/dts/nxp/imx/imx6qp.dtsi | 4 ++++
> arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 17 +++++++++++++++
> arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 27 ++++++++++++++++++++++++
> drivers/pci/controller/dwc/pci-imx6.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-
> 6 files changed, 200 insertions(+), 5 deletions(-)
>
>
>
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 14+ messages in thread* RE: [PATCH 0/9] Add legacy i.MX PCIe EP mode supports
2023-08-02 6:51 ` [PATCH 0/9] Add legacy i.MX PCIe EP mode supports Ahmad Fatoum
@ 2023-08-02 14:08 ` Hongxing Zhu
0 siblings, 0 replies; 14+ messages in thread
From: Hongxing Zhu @ 2023-08-02 14:08 UTC (permalink / raw)
To: Ahmad Fatoum, l.stach@pengutronix.de, shawnguo@kernel.org,
lpieralisi@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org
Cc: devicetree@vger.kernel.org, linux-pci@vger.kernel.org,
linux-kernel@vger.kernel.org, dl-linux-imx, kernel@pengutronix.de,
linux-arm-kernel@lists.infradead.org
Hi Ahmad:
Thanks for your concerns.
> -----Original Message-----
> From: Ahmad Fatoum <a.fatoum@pengutronix.de>
> Sent: 2023年8月2日 14:52
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; l.stach@pengutronix.de;
> shawnguo@kernel.org; lpieralisi@kernel.org; robh+dt@kernel.org;
> krzysztof.kozlowski+dt@linaro.org
> Cc: devicetree@vger.kernel.org; linux-pci@vger.kernel.org;
> linux-kernel@vger.kernel.org; dl-linux-imx <linux-imx@nxp.com>;
> kernel@pengutronix.de; linux-arm-kernel@lists.infradead.org
> Subject: Re: [PATCH 0/9] Add legacy i.MX PCIe EP mode supports
>
> Hello Richard,
>
> On 02.08.23 08:06, Richard Zhu wrote:
> > Add legacy 32bit i.MX PCIe EP mode support
> >
> > The PCI controller contained in i.MX6/7 legacy SOCs is one dual mode
> > PCIe controller, and can work either as RC or EP.
> >
> > This series add i.MX6/7 PCIe EP mode supports. And had been verified
> > on i.MX6 sabresd and i.MX7 SDB boards.
> >
> > In the verification, one board PCIe is used as RC, the other one is
> > used as EP.
> > Use the cross TX/RX differential cable connect the two PCIe ports of
> > these two boards.
> >
> > +-----------+ +------------+
> > | PCIe TX |<-------------->|PCIe RX |
> > | | | |
> > | Board | | Board |
> > | | | |
> > | PCIe RX |<-------------->|PCIe TX |
> > +-----------+ +------------+
>
> I am curious what software you are running on both sides to test?
> Do you use CONFIG_PCI_EPF_TEST? What do you run on RC side?
Yes, it is.
Beside PCI_EPF_TEST, the CONFIG_PCI_ENDPOINT_TEST is used too.
And the pcitest program is used on RC side to verify the MSI and data IO tests features.
Best Regards
Richard Zhu
>
> Thanks,
> Ahmad
>
> >
> > [PATCH 1/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6Q and i.MX6QP PCIe
> > [PATCH 2/9] dt-bindings: PCI: fsl,imx6q: Add i.MX6SX PCIe EP [PATCH
> > 3/9] dt-bindings: PCI: fsl,imx6q: Add i.MX7D PCIe EP [PATCH 4/9] arm:
> > dts: nxp: Add i.MX6QDL and i.MX6QP PCIe EP supports [PATCH 5/9] arm:
> > dts: nxp: Add i.MX6SX PCIe EP support [PATCH 6/9] arm: dts: nxp: Add
> > i.MX7D PCIe EP support [PATCH 7/9] PCI: imx6: Add i.MX6Q and i.MX6QP
> > PCIe EP supports [PATCH 8/9] PCI: imx6: Add i.MX6SX PCIe EP support
> > [PATCH 9/9] PCI: imx6: Add i.MX7D PCIe EP support
> >
> > Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 50
> +++++++++++++++++++++++++++++++++++++++++----
> > arch/arm/boot/dts/nxp/imx/imx6qdl.dtsi | 14
> +++++++++++++
> > arch/arm/boot/dts/nxp/imx/imx6qp.dtsi | 4
> ++++
> > arch/arm/boot/dts/nxp/imx/imx6sx.dtsi | 17
> +++++++++++++++
> > arch/arm/boot/dts/nxp/imx/imx7d.dtsi | 27
> ++++++++++++++++++++++++
> > drivers/pci/controller/dwc/pci-imx6.c | 93
> +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> +++++++++++++++++++++-
> > 6 files changed, 200 insertions(+), 5 deletions(-)
> >
> >
> >
>
> --
> Pengutronix e.K. |
> |
> Steuerwalder Str. 21 |
> http://www.pen/
> gutronix.de%2F&data=05%7C01%7Chongxing.zhu%40nxp.com%7Ccc783fc2b1
> 0340518e0108db9324ec3f%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7
> C0%7C638265559019809339%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4w
> LjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000%7C%
> 7C%7C&sdata=tC3JGc%2Bo5z5211vCtpbcnO5%2FYC2ghM1te%2FwGOgC9ue8
> %3D&reserved=0 |
> 31137 Hildesheim, Germany | Phone: +49-5121-206917-0
> |
> Amtsgericht Hildesheim, HRA 2686 | Fax:
> +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 14+ messages in thread